CN113140514A - 半导体装置与其制作方法 - Google Patents

半导体装置与其制作方法 Download PDF

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Publication number
CN113140514A
CN113140514A CN202110435884.3A CN202110435884A CN113140514A CN 113140514 A CN113140514 A CN 113140514A CN 202110435884 A CN202110435884 A CN 202110435884A CN 113140514 A CN113140514 A CN 113140514A
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layer
gate
dielectric layer
gate electrode
forming
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CN202110435884.3A
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王俊傑
白岳青
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US17/169,892 external-priority patent/US11742404B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN113140514A publication Critical patent/CN113140514A/zh
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    • H01L21/8232—Field-effect technology
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    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract

一种半导体装置与其制作方法，在制作半导体装置的方法中，通过移除牺牲栅极电极形成栅极空间，在栅极空间中形成栅极介电层，在栅极介电层上形成导电层以完全填充栅极空间，凹陷栅极介电层及导电层以形成凹陷的栅极电极，以及在凹陷的栅极电极上形成接触金属层。凹陷的栅极电极并不包含钨，并且接触金属层包含钨。

Description

半导体装置与其制作方法
技术领域
本揭露的一些实施方式是关于半导体装置与其制作方法，尤其是关于栅极与其制作方法。
背景技术
随着半导体业界已进展至纳米技术制程节点以追求更高装置密度、更高效能及更低成本，源于制造及设计问题所造成的挑战已致使三维设计的研发，诸如，多栅极场效晶体管(multi-gate field effect transistor，FET)，包含鳍式场效晶体管(FinFET)及全环绕栅极(gate-all-around，GAA)场效晶体管。在鳍式场效晶体管中，栅极电极邻近通道区域的三个侧表面，在通道区域间有插入的(interposed)栅极介电层。鳍式场效晶体管的栅极电极包含通过栅极替代技术形成的一或多层金属性材料。
发明内容
根据本揭露的一个态样，在一种制作半导体装置的方法中，通过移除牺牲栅极电极形成栅极空间，在栅极空间中形成栅极介电层，在栅极介电层上形成导电层以完全填充栅极空间，凹陷栅极介电层及导电层以形成凹陷的栅极电极，以及在凹陷的栅极电极上形成接触金属层。凹陷的栅极电极并不包含钨层，并且接触金属层包含钨。
根据本揭露的其他态样，在一种制作半导体装置的方法中，形成自置于基板之上的隔离绝缘层突出的鳍式结构，在鳍式结构之上形成牺牲栅极介电层，在牺牲栅极介电层之上形成牺牲栅极电极层，形成栅极侧壁间隔物，形成一或多个介电层；通过移除牺牲栅极电极层及牺牲栅极介电层来形成栅极空间，在形成栅极空间之后，凹陷栅极侧壁间隔物；在栅极空间中形成栅极介电层；在栅极介电层上形成导电层以完全填充栅极空间，凹陷栅极介电层及导电层以形成凹陷的栅极电极，以及在凹陷的栅极电极上形成接触金属层。
根据本揭露的另一态样，一种半导体装置包含自置于基板之上的隔离绝缘层突出并且具有通道区域的鳍式结构、源极/漏极磊晶层、至于通道区域上的栅极介电层，以及置于栅极介电层上的栅极电极层。栅极电极层包含下部分及上部分，并且下部分包含导电层，导电层中的至少一者具有U形截面，并且导电层中的至少一者并不具有U形截面。
附图说明
当结合附图阅读时，根据以下详细描述可最佳理解本揭露。应强调，根据业界的标准做法，各种特征并未按比例绘制，并且仅用于例示的目的。事实上，出于论述清楚的目的，可任意地增大或缩小各种特征的尺寸。
图1展示根据本揭露的实施例的用于制作半导体装置的顺序制程的多个阶段中的一者；
图2展示根据本揭露的实施例的用于制作半导体装置的顺序制程的多个阶段中的一者；
图3展示根据本揭露的实施例的用于制作半导体装置的顺序制程的多个阶段中的一者；
图4展示根据本揭露的实施例的用于制作半导体装置的顺序制程的多个阶段中的一者；
图5展示根据本揭露的实施例的用于制作半导体装置的顺序制程的多个阶段中的一者；
图6展示根据本揭露的实施例的用于制作半导体装置的顺序制程的多个阶段中的一者；
图7展示根据本揭露的实施例的用于制作半导体装置的顺序制程的多个阶段中的一者；
图8展示根据本揭露的实施例的用于制作半导体装置的顺序制程的多个阶段中的一者；
图9展示根据本揭露的实施例的用于制作半导体装置的顺序制程的多个阶段中的一者；
图10展示根据本揭露的实施例的用于制作半导体装置的顺序制程的多个阶段中的一者；
图11展示根据本揭露的实施例的用于制作半导体装置的顺序制程的多个阶段中的一者；
图12展示根据本揭露的实施例的用于制作半导体装置的顺序制程的多个阶段中的一者；
图13展示根据本揭露的实施例的用于制作半导体装置的顺序制程的多个阶段中的一者；
图14展示根据本揭露的实施例的用于制作半导体装置的顺序制程的多个阶段中的一者；
图15展示根据本揭露的实施例的用于制作半导体装置的顺序制程的多个阶段中的一者；
图16展示根据本揭露的实施例的用于制作半导体装置的顺序制程的多个阶段中的一者；
图17A、图17B、图17C及图17D展示根据本揭露的实施例的用于制作半导体装置的顺序制程的各个阶段；
图18A、图18B、图18C、图18D、图18E及图18F展示根据本揭露的实施例的用于制作半导体装置的顺序制程的各个阶段；
图19A、图19B、图19C、图19D、图19E、图19F及图19G展示根据本揭露的实施例的用于制作半导体装置的顺序制程的各个阶段；
图20A、图20B及图20C展示根据本揭露的实施例的用于制作半导体装置的顺序制程的各个阶段；
图21展示根据本揭露的实施例的用于制作场效晶体管装置的顺序制程的多个阶段中的一者；
图22A、图22B、图22C、图22D、图22E、图22F及图22G展示根据本揭露的实施例的用于制作半导体装置的顺序制程的各个阶段。
【符号说明】
10:基板
11:下部分
12:掺杂剂
15:遮罩层
15A:第一遮罩层
15B:第二遮罩层
20:鳍式结构
22:衬垫层
25:鳍式结构
30:层
40:牺牲栅极结构
42:牺牲栅极介电层
44:牺牲栅极电极层
45:侧壁间隔物/包覆层
46:氮化硅垫层
48:遮罩层
49:栅极空间
50:源极/漏极磊晶层
52:孔隙
60:绝缘衬垫层
65:层间介电层
81:界面层
82:栅极介电层
83:阻障层
84:功函数调整材料层
84-1:功函数调整材料层
84-2:功函数调整材料层
85:功函数调整材料层
86:阻断金属层
87:接触金属层
88:栅极电极
88A:下部栅极电极
90:顶盖绝缘层
110:接触孔
120:硅化物层
130:导电材料
135:第二层间介电层
140:第三层间介电层
145:栅极触点
181:钨层
183:钨层
185:顶盖绝缘层
200:假性鳍式结构
205:下层
210:中间层
215:上层
230:分隔栓塞
X1-X1:线
Y1-Y1:线
X:方向
Y:方向
Z:方向
T1:厚度
T2:厚度
D1:距离
D2:距离
具体实施方式
应当理解，以下揭示内容提供用于实施本揭露的不同特征的许多不同实施例或实例。下文描述部件及配置的具体实施例或实例以简化本揭露。当然，此些仅仅是实例且并非意欲限制。举例而言，元件的尺寸并不限于所揭示的范围或值，但是可能视装置的制程条件及/或期望性质而定。此外，在以下描述中，在第二特征之上或在其上形成第一特征可包含将第一特征及第二特征形成为直接接触的实施例，且亦可包含可在第一特征与第二特征之间夹置形成额外特征以使得第一特征与第二特征可不直接接触的实施例。出于简单与清晰的目的，各种特征可以不同比例绘制。
此外，出于简洁的目的，可在本文中使用诸如“之下”、“下方”、“下”、“上方”、“上”等空间相对术语来描述一个元件或特征相对于另一元件或特征的关系，如图中所例示。空间相对术语意欲涵盖装置使用时或操作时除图中所描绘的定向以外的不同定向。可以其他方式来定向装置(旋转90度或以其他定向)，且可同样相应地解释本文所使用的空间相对描述词。另外，术语“由.....制成”可能意味“包含”或“由...组成”。
在栅极替代技术中，首先在通道区域之上形成包含牺牲栅极电极(由例如多晶硅制成)的牺牲栅极结构，并且随后由金属栅极结构替代牺牲栅极结构。在金属栅极鳍式场效晶体管中，装置效能受金属栅极剖面(形状)设计的影响，并且金属栅极剖面通常视牺牲栅极电极的剖面而定。在一些鳍式场效晶体管装置中，在以栅极替代制程形成金属栅极结构之后，金属栅极结构的上部分为凹陷的，并且在凹陷的栅极结构之上形成顶盖绝缘层以保护金属栅极电极与相邻导电触点之间的隔离区域。此外，在进阶的鳍式场效晶体管装置中，具有不同阈值电压的各种场效晶体管(n通道及p通道场效晶体管)制作在一个装置上，并且场效晶体管可具有不同金属(例如，功函数调整金属)结构。用以形成栅极顶盖的栅极凹陷蚀刻可能受金属结构的影响，并且期望在不管金属结构的情况下，将金属栅极结构凹陷至期望的高度。在本揭露中，提供一种通过调整牺牲栅极电极的剖面(形状)来控制凹陷的金属栅极结构的高度的方法。
图1至图16展示根据本揭露的实施例的用于制作场效晶体管装置的顺序制程。应当理解，可在图1至图16所示的制程之前、期间及之后提供额外操作，并且针对方法的额外实施例，可替代或消除一些下文所描述的操作中。操作/制程的顺序为可互换的。
如图1所示，将杂质离子(掺杂剂)12布植至硅基板10中以形成阱区域。执行离子布植以防止冲穿效应。
在实施例中，基板10在至少其表面部分上包含单晶半导体层。基板10可包含单晶半导体材料，诸如但不限于硅(Si)、锗(Ge)、硅锗(SiGe)、砷化镓(GaAs)、锑化铟(InSb)、磷化镓(GaP)、锑化镓(GaSb)、砷化铟铝(InAlAs)、砷化铟镓(InGaAs)、锑磷化镓(GaSbP)、砷锑化镓(GaAsSb)及磷化铟(InP)。在此实施例中，基板10由硅制成。
基板10可在其表面区域中包含一或多个缓冲层(未展示)。缓冲层可以用以自基板至源极/漏极区域逐渐改变晶格常数。缓冲层可由磊晶生长的单晶半导体材料形成，诸如但不限于硅、锗、锗锡(GeSn)、硅锗、砷化镓、锑化铟、磷化镓、锑化镓、砷化铟铝、砷化铟镓、锑磷化镓、砷锑化镓、氮化镓(GaN)、磷化镓(GaP)及磷化铟。在特定实施例中，基板10包含在硅基板10上磊晶生长的硅锗(SiGe，silicon germanium)缓冲层。硅锗缓冲层的锗浓度的锗原子百分比可自最底缓冲层的30％增长至最顶缓冲层的70％。
基板10可包含已适当地掺杂杂质(例如，p型或n型导电性)的各种区域。例如，掺杂剂12为针对n型鳍式场效晶体管的硼(BF2)及针对p型Fin场效晶体管的磷。
在图2中，在基板10之上形成遮罩层15。在一些实施例中，遮罩层15包含第一遮罩层15A及第二遮罩层15B。在一些实施例中，第一遮罩层15A由氮化硅制成，并且第二遮罩层15B由氧化硅制成。在其他实施例中，第一遮罩层15A由氧化硅制成，并且第二遮罩层15B由氮化硅(SiN)制成。第一及第二遮罩层15A与15B由化学气相沉积(chemical vapordeposition，CVD)形成，包含低压化学气相沉积(low pressure chemical vapordeposition，LPCVD)及电浆增强化学气相沉积(plasma enhanced CVD，PECVD)、物理气相沉积(physical vapor deposition，PVD)、原子层沉积(atomic layer deposition，ALD)，或其他适当制程。通过使用图案化操作(包含光微影及蚀刻)，将遮罩层15图案化为遮罩图案。
接着，如图3所示，通过使用图案化后的遮罩层15，将基板10图案化为在X方向上延伸的鳍式结构25。在图3中，两个鳍式结构25配置在Y方向上。但是，鳍式结构的数目并不限于两个，并且可以少至一个以及三个或更多个。在一些实施例中，在鳍式结构25的两侧上形成一或多个假性鳍式结构，以便改进图案化操作中的图案保真性。
可通过任何适当方法图案化鳍式结构25。例如，可使用一或多个光微影制程(包含双图案化或多图案化制程)图案化鳍式结构。通常，双图案化或多图案化制程结合光微影与自对准制程，从而允许创建例如间距小于原本使用单个直接光微影制程能够获得的间距的图案。例如，在实施例中，在基板之上形成牺牲层，并且使用光微影制程图案化牺牲层。使用自对准制程在图案化后的牺牲层旁边形成间隔物。然后移除牺牲层，然后可以使用剩余间隔物来图案化鳍式结构。
在形成鳍式结构25之后，在基板10之上形成包含一或多层绝缘材料的绝缘材料层，以使得鳍式结构完全嵌入在绝缘层中。用于绝缘层的绝缘材料可包含通过低压化学气相沉积、电浆化学气相沉积或可流动式化学气相沉积形成的氧化硅、氮化硅、氮氧化硅(SiON)、碳氮氧化硅(SiOCN)、碳氮化硅(SiCN)、掺杂氟的硅酸盐玻璃(fluorine-dopedsilicate glass，FSG)或低介电常数(k)介电材料。可在形成绝缘层之后执行退火操作。然后，执行平坦化操作(诸如，化学机械研磨(chemical mechanical polishing，CMP)方法及/或回蚀方法)，如此一来，自绝缘材料层30暴露最上方的鳍式结构25的上表面，如图4所示。
在一些实施例中，在形成绝缘材料层30之前，在图3的结构之上形成一或多个衬垫层22，如图4所示。衬垫层22包含氮化硅、氮氧化硅、碳氮化硅、碳氮氧化硅及氧化硅中的一或多者。
然后，如图5所示，凹陷绝缘材料层30以形成隔离绝缘层30，以暴露鳍式结构20的上部分。在此操作中，鳍式结构25通过隔离绝缘层30而彼此电性隔离，隔离绝缘层30亦称为浅沟槽隔离(shallow trench isolation，STI)。鳍式结构的下部分11嵌入在隔离绝缘层30中。
在形成在隔离绝缘层30之后，形成牺牲栅极介电层42，如图6所示。牺牲栅极介电层42包含一或多层绝缘材料，诸如，以氧化硅为主的材料。在实施例中，使用通过化学气相沉积形成的氧化硅。在一些实施例中，牺牲栅极介电层42的厚度介于约1纳米至约5纳米的范围内。
图7例示在暴露的鳍式结构25之上形成牺牲栅极结构40之后的结构。牺牲栅极结构40包含牺牲栅极电极层44及牺牲栅极介电层42。在鳍式结构25的一部分之上形成牺牲栅极结构40，此部分将成为通道区域。首先通过在鳍式结构之上包覆地沉积牺牲栅极介电层42来形成牺牲栅极结构40。然后，在牺牲栅极介电层42上以及在鳍式结构25之上包覆地沉积牺牲栅极电极层44，使得鳍式结构25完全嵌入在牺牲栅极电极层44中。牺牲栅极电极层44包含硅，诸如多晶硅或非晶硅。在一些实施例中，牺牲栅极电极层44经受平坦化操作。使用化学气相沉积(包含低压化学气相沉积及电浆增强化学气相沉积)、物理气相沉积、原子层沉积或其他适当制程来沉积牺牲栅极介电层42及牺牲栅极电极层44。随后，在牺牲栅极电极层44之上形成遮罩层。遮罩层包含氮化硅垫层46及氧化硅遮罩层48。
接着，在遮罩层上执行图案化操作，并且将牺牲栅极电极层44图案化为牺牲栅极结构40，如图7所示。下文将更详细地解释牺牲栅极结构40的图案化操作。
在一些实施例中，牺牲栅极结构40包含牺牲栅极介电层42、牺牲栅极电极层44(例如，多晶硅)、氮化硅垫层46以及氧化硅遮罩层48。通过图案化牺牲栅极结构40，在牺牲栅极结构40的相对侧上部分地暴露鳍式结构20的上部分，借此限定源极/漏极(S/D，source/drain，S/D)区域，如图7所示。在本揭露中，源极及漏极能够互换地使用，并且其结构实质上相同。在图7中，形成一个牺牲栅极结构，但是牺牲栅极结构40的数目并不限于一个。在一些实施例中，两个或多个牺牲栅极结构配置在X方向上。在某些实施例中，在牺牲栅极结构40的两侧上形成一或多个假性牺牲栅极结构，以便改进图案保真性。
在形成牺牲栅极结构40之后，通过使用化学气相沉积或其他适当方法来共形地形成用于侧壁间隔物45的绝缘材料的包覆层45，如图8所示。以共形方式沉积包覆层45，使包覆层45形成为在垂直表面(诸如，侧壁)、水平表面以及牺牲栅极结构40的顶部上具有实质上相等的厚度。在一些实施例中，将包覆层45沉积为介于约2纳米至约10纳米的范围内的厚度。在实施例中，包覆层45的绝缘材料为以氮化硅为主的材料，诸如，氮化硅、氮氧化硅、碳氮氧化硅或碳氮化硅以及其组合。
此外，如图9所示，在牺牲栅极结构40的相对侧壁上形成侧壁间隔物45，随后，向下凹陷源极/漏极区域的鳍式结构至隔离绝缘层30的上表面以下。在形成包覆层45之后，使用例如反应性离子蚀刻(reactive ion etching，RIE)在包覆层45上执行非等向性蚀刻。在非等向性蚀刻制程期间，自水平表面移除大多数绝缘材料，从而留下在垂直表面上的介电间隔物层，诸如，牺牲栅极结构40的侧壁及鳍式结构25的侧壁。可自侧壁间隔物45暴露遮罩层48。在一些实施例中，可随后执行等向性蚀刻以自暴露的鳍式结构25的源极/漏极区域的上部分移除绝缘材料。
随后，通过使用干式蚀刻及/或湿式蚀刻，向下凹陷源极/漏极区域的鳍式结构至隔离绝缘层30的上表面以下。如图9所示，在暴露的鳍式结构(鳍式侧壁)的源极/漏极区域上形成的侧壁间隔物45部分地留下。然而，在其他实施例中，完全移除在暴露的鳍式结构的源极/漏极区域上形成的侧壁间隔物45。在全环绕栅极场效晶体管的情况下，在凹陷源极/漏极区域之后形成内间隔物。
随后，如图10所示，形成源极/漏极磊晶层50。源极/漏极磊晶层50包含一或多层用于n通道场效晶体管的硅、磷化硅(SiP)、碳化硅(SiC)及碳磷化硅(SiCP)或用于p通道场效晶体管的硅、硅锗、锗、锗锡(GeSn)及硅锗锡(SiGeSn)。通过使用化学气相沉积、原子层沉积或分子束磊晶(molecular beam epitaxy，MBE)的磊晶生长方法来形成源极/漏极磊晶层50。
如图10所示，源极/漏极磊晶层50自凹陷的鳍式结构各别地生长。在一些实施例中，所生长的磊晶层在隔离绝缘层上方合并，并且形成孔隙52。
随后，形成作为蚀刻终止层的绝缘衬垫层60，然后形成层间介电(interlayerdielectric，ILD)层65，如图11所示。绝缘衬垫层60由氮化硅为主的材料(诸如，氮化硅)制成，并且在后续蚀刻操作中充当接触蚀刻终止层。用于层间介电层65的材料包含包含硅、氧、碳及/或轻的化合物，诸如，氧化硅、碳氢氧化硅(SiCOH)及碳氧化硅。有机材料(诸如，聚合物)可用于层间介电层65。在形成层间介电层65之后，执行平坦化操作，诸如化学机械研磨，以暴露牺牲栅极电极层44的顶部分，如图11所示。
接着，如图12所示，移除牺牲栅极电极层44及牺牲栅极介电层42，借此暴露栅极空间49中的鳍式结构。在移除牺牲栅极结构期间，层间介电层65保护源极/漏极磊晶层50。可使用电浆干式蚀刻及/或湿式蚀刻来移除牺牲栅极结构。当牺牲栅极电极层44为多晶硅，并且层间介电层65为氧化硅时，可使用湿式蚀刻剂(诸如，氢氧化四甲基铵(TMAH)溶液)来选择性地移除牺牲栅极电极层44。此后，使用电浆干式蚀刻及/或湿式蚀刻移除牺牲栅极介电层42。
在移除牺牲栅极结构之后，在暴露的鳍式结构20周围形成栅极介电层82，并且在栅极介电层82上形成栅极电极88，如图13所示。
在某些实施例中，栅极介电层82包含一或多层介电材料，诸如，氧化硅、氮化硅或高k介电材料、其他适当介电材料，及/或其组合。高k介电材料的例子包含二氧化铪(HfO2)、氧化硅铪(HfSiO)、氮氧化硅铪(HfSiON)、氧化钽铪(HfTaO)、氧化钛铪(HfTiO)、氧化铪锆(HfZrO)、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他适当高介电常数介电材料及/或其组合。在一些实施例中，栅极介电层82包含在通道层与介电材料之间形成的界面层。
可通过化学气相沉积、原子层沉积或任何适当方法来形成栅极介电层82。在一个实施例中，使用高度共形的沉积制程(诸如，原子层沉积)来形成栅极介电层82，以便确保形成在通道区域上的栅极介电层82具有均一厚度。在一些实施例中，栅极介电层82的厚度介于约1纳米至约6纳米的范围内。
在栅极介电层82上形成栅极电极88。栅极电极88包含一或多层导电材料，诸如，多晶硅、铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、氮化钛(TiN)、氮化钨(WN)、钛铝(TiAl)、氮化钛铝(TiAlN)、碳氮化钽(TaCN)、碳化钽(TaC)、氮化钽硅(TaSiN)、金属合金、其他适当材料及/或其组合。
可通过化学气相沉积、原子层沉积、电镀或其他适当方法来形成栅极电极88。亦可在层间介电层65的上表面之上沉积栅极电极88。然后，通过使用例如化学机械研磨来平坦化在层间介电层65之上形成的栅极介电层82及栅极电极88，直至显露出层间介电层65的顶表面为止。
在平坦化操作之后，凹陷栅极电极88，并且在凹陷的栅极电极88之上形成顶盖绝缘层90，如图13所示。在一些实施例中，顶盖绝缘层90包含一或多层氮化硅为主的材料，诸如氮化硅。可通过在沉积绝缘材料后，接着进行平坦化操作来形成顶盖绝缘层90。
在本揭露的某些实施例中，在栅极介电层82与栅极电极88之间插入一或多个功函数调整层(未展示)。功函数调整层由导电材料制成，诸如，单层氮化钛、氮化钽、碳化钽铝(TaAlC)、碳化钛(TiC)、碳化钽(TaC)、钴、铝、钛铝、铪钛(HfTi)、硅化钛(TiSi)、硅化钽(TaSi)或碳化钛铝(TiAlC)，或多层两种或更多种这些材料。对于n通道场效晶体管，将氮化钽、碳化钽铝、氮化钛、碳化钛、钴、钛铝、铪钛、硅化钛及硅化钽中的一或多者用作功函数调整层，并且对于p通道场效晶体管，将氮化钨、碳氮化钨(WCN)、钨、钌、钴、氮化钛或氮硅化钛(TiSiN)中的一或多者用作功函数调整层。可通过原子层沉积、物理气相沉积、化学气相沉积、电子束蒸发或其他适当制程来形成功函数调整层。此外，针对可能使用不同金属层的n通道场效晶体管及p通道场效晶体管，可单独地形成功函数调整层。
随后，通过使用干式蚀刻在层间介电层65中形成接触孔110，如图14所示。在一些实施例中，蚀刻源极/漏极磊晶层50的上部分。
在源极/漏极磊晶层50之上形成硅化物层120，如图15所示。硅化物层120包含硅化钨(WSi)、硅化钴(CoSi)、硅化镍(NiSi)、硅化钛(TiSi)、硅化钼(MoSi)及硅化钽(TaSi)中的一或多者。然后，在接触孔110中形成导电材料130，如图16所示。导电材料130包含钴、镍、钨、钛、钽、铜、铝、氮化钛及氮化钽中的一或多者。
应当理解，鳍式场效晶体管经过另外的CMOS制程以形成各种特征，诸如，触点/通孔件、互连金属层、介电层、钝化层等等。
图17A至图19G展示根据本揭露的实施例的用于栅极替代操作的顺序制程。应当理解，可在图17A至图19G所示的制程之前、期间及之后提供额外操作，并且针对方法的额外实施例，可替代或消除一些下文所描述的操作。操作/制程的顺序为可互换的。如通过前述实施例解释的材料、制程、方法、尺寸及/或组态可应用至以下实施例，并且可省略其详细描述。
图17A至图17D展示在移除牺牲栅极结构(牺牲栅极电极层44及牺牲栅极介电层42)之后的各种图，借此形成栅极空间49，如参照图12所描述。图17A为沿图17D的线X1-X1的截面图(平面图或投影图)，图17B为沿图17D的线Y1-Y1的截面图，并且图17C为沿图17D的Y2-Y2的截面图。在一些实施例中，在形成层间介电层65之前形成充当蚀刻终止层的绝缘衬垫层60。在一些实施例中，绝缘衬垫层60包含氮化硅。在一些实施例中，在层间介电层65之上形成额外介电层66。在一些实施例中，额外介电层66包含氮化硅。
在一些实施例中，凹陷栅极侧壁间隔物45的上部分，如图17B及图17C所示。在一些实施例中，在移除牺牲栅极介电层期间凹陷栅极侧壁间隔物45，并且在其他实施例中，执行一或多个干式及/或湿式蚀刻操作以凹陷栅极侧壁间隔物45。在一些实施例中，在凹陷栅极侧壁间隔物45之后，最上表面仅由氮化硅为主的材料(例如，氮化硅)(绝缘衬垫层60及介电层66)制成。
图18A至图19G为第17B或17C图所示的栅极空间49及环绕层的放大图。如图18A所示，在鳍式结构20的通道区域上形成界面层81，并且在界面层81及栅极侧壁间隔物45的内壁上形成栅极介电层82。在一些实施例中，在绝缘衬垫层60及额外介电层66的上表面之上形成栅极介电层82。在一些实施例中，通过原子层沉积制程形成栅极介电层82以在高深宽比结构之上共形地形成层。在一些实施例中，栅极空间49的深宽比(高度/底部直径或面积)介于约7至约25的范围内。
然后，如图18B所示，在栅极介电层82之上形成阻障层83。在一些实施例中，阻障层83包含钽、氮化钽、钛、氮化钛或氮硅化钛中的一或多层。在一些实施例中，阻障层83的厚度介于约1纳米至约3纳米的范围内。在一些实施例中，并不形成阻障层83。在一些实施例中，阻障层83底部的厚度比侧面的厚度厚。在一些实施例中，阻障层83底部的厚度为侧面厚度的约0.5倍至3倍。
此外，如图18C所示，在阻障层83之上形成一或多个第一功函数调整材料(workfunction adjustment material，WFM)层84。在一些实施例中，第一功函数调整材料层84为p型功函数调整材料，诸如，氮化钨、碳氮化钨、钨、钌、钴、氮化钛或氮硅化钛。在一些实施例中，第一功函数调整材料层84的厚度介于约0.5纳米至约10纳米的范围内，并且在其他实施例中，介于约1纳米至约2纳米的范围内。在一些实施例中，第一功函数调整材料层84底部的厚度为侧面厚度的约0.8倍至2倍。当第一功函数调整材料层由氮化钛制成时，自包含四氯化钛(TiCl4)及氨(NH3)的源气体形成氮化钛层。在一些实施例中，氮化钛层含有作为杂质的氯。在一些实施例中，氮化钛层中的钛浓度介于原子百分比约10％至约80％的范围内。当钛浓度过小时，氮化钛的抗性增大，并且当钛浓度过高时，钛扩散可能致使各种问题(例如，冲穿)。
然后，如图18D所示，移除第一功函数调整材料层84的上部分，以使得第一功函数调整材料层84的最上部分低于绝缘衬垫层60及额外介电层66的最上部分。在一些实施例中，第一功函数调整材料层84的最上部分低于栅极侧壁间隔物45的最上部分，并且在其他实施例中，第一功函数调整材料层84的最上部分等于或高于栅极侧壁间隔物45的最上部分并且低于绝缘衬垫层60及额外介电层66的最上部分(参见图17B)。
此外，如图18E所示，在第一功函数调整材料层84之上形成一或多个第二功函数调整材料层85。在一些实施例中，第二功函数调整材料层85是n型功函数调整材料材料，诸如，钛铝、钛硅铝(TiSiAl)、碳化钛铝、钽铝(TaAl)或碳化钽铝。在一些实施例中，第二功函数调整材料层85的厚度介于约0.5纳米至约6纳米的范围内，并且在其他实施例中，介于约2纳米至约5纳米的范围内。在一些实施例中，第二功函数调整材料层85底部的厚度与侧面厚度相同或最高可达侧面厚度的3倍。
当第二功函数调整材料层85由碳化钛铝制成时，自包含四氯化钛及有机铝(例如，三乙基铝)的源气体形成碳化钛铝层。在一些实施例中，碳化钛铝层含有作为杂质的氯。在一些实施例中，碳化钛铝层中的铝浓度介于园子百分比约5％至约80％的范围内。当铝浓度过小时，碳化钛铝层的抗性增大，并且当铝浓度过高时，铝扩散可能致使各种问题(例如，阈值电压(Vt)偏移)。在一些实施例中，p型场效晶体管包含p型功函数调整材料及n型功函数调整材料两者，如图18E所示，并且n型场效晶体管并不包含第一功函数调整材料层(p型功函数调整材料)84(参见图19F)。在一些实施例中，类似于相对于图18D所解释的操作，移除第二功函数调整材料层85的上部分。
在形成功函数调整材料层84、85之后，使用一或多个沉积及化学机械研磨操作，在功函数调整材料层之上形成阻断金属层86，阻断金属层86也可称为胶层，如图18F所示。在一些实施例中，阻断金属层86包含钽、氮化钽、钛、氮化钛或氮硅化钛中的一或多者。在某些实施例中，使用氮化钛。在其他实施例中，使用碳氮化钨。在一些实施例中，阻障层83、第一功函数调整材料层84、第二功函数调整材料层85及阻断金属层86中的任一者皆不包含含有钨原子百分比超过90％的金属钨层。在一些实施例中，阻断金属层86的厚度介于约3纳米至约20纳米的范围内。如图18F所示，当栅极介电层82、阻障层83及功函数调整材料层84、85在Y方向(源极至漏极方向)上包含U形截面(具有底部及两个垂直部分)时，阻断金属层86完全填充栅极空间49。在一些实施例中，由于栅极侧壁间隔物45为凹陷的，将均由氮化硅制成的绝缘衬垫层60及额外介电层66用作化学机械研磨终止层，以执行化学机械研磨。因此，在化学机械研磨操作中并不研磨氧化硅或氧化硅为主的材料。
然后，如图19A所示，通过一或多个蚀刻操作来凹陷层的上部分，层在栅极空间中形成。在一些实施例中，在蚀刻操作中，亦蚀刻侧壁间隔物45的上部分及/或栅极介电层82的上部分。如图19A所示，在一些实施例中，阻断金属层86的顶部低于第一功函数调整材料层84及第二功函数调整材料层85的顶部，并且功函数调整材料层的顶部低于栅极介电层82的顶部。在其他实施例中，阻断金属层86的顶部高于功函数调整材料层中任一者或两者的顶部。
随后，如图19B所示，在凹陷的层之上形成接触金属层87。在一些实施例中，接触金属层87包含钨、钽、锡、铌、钌、钴或钼。在一些实施例中，通过使用金属卤化物(氯化物)气体(例如，五氯化钽(TaCl5)、四氯化锡(SnCl4)、五氯化铌(NbCl5)或四氯化钼(MoCl4))的原子层沉积制程来形成接触金属层87。在一些实施例中，接触金属层87包含无氟金属，例如，通过将五氯化钨(WCl5)作为源气体而形成的无氟钨。在一些实施例中，原子层沉积制程为与蚀刻制程相结合的选择性沉积制程，使得接触金属层87自金属性下层(诸如，阻障层、功函数调整材料层及阻断金属层)生长，并且并无金属层自介电层生长。由于当形成接触金属层87时栅极空间49的深宽比为高(例如，3至20)，使用金属卤化物气体的原子层沉积制程有效地形成接触金属层87而并不形成孔隙。此外，随着金属栅极间距缩小，栅极空间的宽度不足以形成额外(例如，牺牲)层。通过使用在功函数调整材料层正上方的选择性沉积，有可能减小对金属栅极结构的损坏。
在一些实施例中，接触金属层87的厚度T1介于约1纳米至约10纳米的范围内。当接触金属层87的厚度过小时，可能无法充分形成由钨制成的稍后形成的栅极触点，因为接触金属层87可充当钨层的晶种层。当接触金属层87的厚度过大时，可能在栅极侧壁间隔物45之上形成接触金属层，此可能致使漏泄。在一些实施例中，接触金属层87上表面的最下部分位于阻断金属层86正上方。在一些实施例中，接触金属层87的顶部低于栅极侧壁间隔物45的顶部。
在一些实施例中，接触金属层87在栅极介电层82上的厚度T2(例如，在栅极介电层的垂直部分的厚度的中心处)介于约0.1纳米至约1纳米的范围内。当厚度过小时，可能致使接触金属层87侧壁上的损坏，并且当厚度过大时，可能在接触金属层87中形成接缝。
在一些实施例中，接触金属层87的沉积包含插在两个或更多个沉积制程之间的清洗操作。在一些实施例中，清洗操作包含热水清洗(例如，摄氏80度或更高)及/或氧气处理。
在前述实施例中，在栅极空间中形成的层的厚度是沿栅极空间的中心处的Z方向(基板表面的法向方向)量测，除非另有说明。
此外，如图19C所示，在接触金属层87之上形成栅极顶盖绝缘层90。在一些实施例中，栅极顶盖绝缘层90包含氮化硅、氮氧化硅及/或碳氮氧化硅或任何其他适当材料。图19D展示对应于图17D的线X1-X1的截面图，并且图19E展示对应于图17D的Y2-Y2线的隔离绝缘层之上的截面图。在第19D中，省略了阻障层。如图19D所示，第一功函数调整材料层84、第二功函数调整材料层85、阻断金属层86及接触金属层87(及视情况地，阻障层83)可统称为金属栅极电极88。在一些实施例中，如图19D所示，接触金属层87上表面的最低点位于两个相邻鳍式结构20之间。
在一些实施例中，在n型场效晶体管中，并不形成第一功函数调整材料层(p型材料层)，如第19F及19G图所示。图19G展示对应于图17D的线X1-X1的隔离绝缘层之上的截面图。在图19G中，省略了阻障层。如图19G所示，第二功函数调整材料层85、阻断金属层86及接触金属层87(及视情况地，阻障层83)可统称为金属栅极电极88。
图20A、图20B及图20C展示在形成栅极触点145之后的截面图。图20A展示对应于图17D的线Y1-Y1的鳍式结构20之上的截面图，并且图20B展示对应于图17D的Y2-Y2线的隔离绝缘层30之上的截面图。图20C展示沿X方向的截面。
在一些实施例中，在形成栅极顶盖绝缘层90之后，形成第二层间介电层135及第三层间介电层140，并且使用一或多个微影术及蚀刻操作在接触金属层87之上形成接触孔。然后，通过一或多种导电材料填充接触孔以形成栅极触点145。在一些实施例中，栅极触点145包含使用六氟化钨(WF6)或四氟化钨(WF4)作为源气体形成的钨。在一些实施例中，相比接触金属层87，栅极触点145包含更多杂质(例如，氟、氮及/或氧)。在沉积钨之后，执行化学机械研磨操作以自第三层间介电层140的上表面移除过量钨。如图20A及图20B所示，与接触金属层87上表面的侧壁间隔物45接触的边缘部分高于接触金属层87上表面的中心。在一些实施例中，接触金属层87的最高点位于栅极侧壁间隔物45与阻障层83及功函数调整材料层84、85中的其中一者的垂直部分之间。在图20C的X方向截面中，阻障层83、第二功函数调整材料层85及阻断金属层86统称为下部栅极电极88A。如图20C所示，并不包含钨的下部栅极电极88A具有壁形状(非U形)，并且在下部栅极电极88A上形成由钨制成的接触金属层87。
如图20C所示，在一些实施例中，在功能电路中所使用的主动鳍式结构20之间形成一或多个假性鳍式结构200。在一些实施例中，假性鳍式结构200包含下层205、中间层210及上层215，以上所有的下层205、中间层210及上层215由一或多种介电材料制成。在一些实施例中，下层205及上层215包含氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮氧化硅或任何其他适当材料中的一或多者。在一些实施例中，中间层210由不同于下层及上层的材料制成，并且包含高介电常数介电材料，诸如，氧化铪、氧化铝或任何其他适当材料。
此外，在一些实施例中，提供将一个金属栅极电极与相邻者实体地和电性隔离的分隔栓塞(或壁)230，如图20C所示。在一些实施例中，通过图案化牺牲栅极电极以形成开口以及通过绝缘材料填充开口来形成分隔栓塞230。在一些实施例中，以与假性鳍式结构200顶部接触的方式形成分隔栓塞230。在其他实施例中，分隔栓塞230与隔离绝缘层30接触。在一些实施例中，栅极触点145位于鳍式结构20上方，并且在其他实施例中，栅极触点145位于假性鳍式结构200上方。
如图21所示，在一些实施例中，由水平线与连接接触金属层87上表面的最下部分(或栅极空间的中心线与接触金属层的上表面的交叉点)与接触金属层87上表面的最高部分的线形成的角度介于约30度至约60度的范围内。当角度过小时，可能致使接触金属层87侧壁上的损坏，并且可能难以通过已知沉积技术使角度大于60度。
当栅极空间的中心线与栅极侧壁间隔物45的内侧壁之间的距离为距离D2时，接触金属层87的最高部分位于距栅极空间中心的距离D1处，其中，在一些实施例中，0.7≤D1/D2≤1.0。在其他实施例中，0.8≤D1/D2≤0.95。当最高部分位于此等范围内时，接触金属层有效地保护含铝的第二功函数调整材料层85不受用于形成栅极触点的后续化学机械研磨操作的影响。
图22A至图22G展示根据本揭露的实施例的用于栅极替代操作的顺序制程。应当理解，可在图22A至图22G所示的制程之前、期间及之后提供额外操作，并且针对方法的额外实施例，可替代或消除一些下文所描述的操作中。操作/制程的顺序为可互换的。如通过前述实施例解释的材料、制程、方法、尺寸及/或组态可应用至以下实施例，并且可省略其详细描述。
在图22A至图22G中，制作了用于栅极长度等于或小于约14纳米(并且大于例如约5纳米)的窄通道场效晶体管以及栅极长度等于或大于20纳米(并且小于例如约1微米)的长通道场效晶体管的金属栅极结构。在图22A至图22G中，展示了具有不同阈值电压(并且具有不同功函数调整材料)的两个p型窄通道场效晶体管PMOS1及PMOS2、n型窄通道场效晶体管NMOS1以及n型长通道场效晶体管NMOS2。然而，半导体装置可包含两个或更多个n型窄通道场效晶体管、三个或更多个p型窄通道场效晶体管、一或多个p型长通道场效晶体管及/或两个或更多个n型长通道场效晶体管。
如图22A所示，类似于图18C，针对第一p型场效晶体管PMOS1及第二p型场效晶体管PMOS2，在栅极介电层82之上各别地形成第一p型功函数调整材料层84-1及第二p型功函数调整材料层84-2。并不针对n型场效晶体管NMOS1及NMOS2形成p型功函数调整材料层。在一些实施例中，在形成功函数调整材料层之前形成阻障层，类似于图18B。在一些实施例中，第一p型功函数调整材料层84-1及第二p型功函数调整材料层84-2由不同材料及/或不同厚度制成。在一些实施例中，第一p型功函数调整材料层84-1包含钛为主的材料(氮化钛、氮硅化钛等等)，并且第二p型功函数调整材料层84-2包含钨为主的材料(氮化钨、碳氮化钨、钨等等)。
然后，类似于图18D，移除p型功函数调整材料层84-1及84-2的上部分，以使得p型功函数调整材料层的最上部分低于蚀刻终止层(绝缘衬垫层60)及额外介电层66的最上部分，如图22B所示。
此外，类似于图18E，针对p型场效晶体管PMOS1、PMOS2及n型场效晶体管NOMS1、NMOS2形成n型功函数调整材料层85，如图22C所示。接着，类似于图18F，使用一或多个沉积及化学机械研磨操作，在功函数调整材料层84-1、84-2及85之上形成阻断金属层86，阻断金属层86也可称为胶层，如图22D所示。在一些实施例中，当在展示U形截面的长通道场效晶体管NMOS2的栅极空间中共形地形成阻断金属层86时，阻断金属层86完全填充窄通道场效晶体管PMOS1、PMOS2及NMOS1的栅极空间。
然后，如图22E所示，在长通道n型场效晶体管NMOS2中的阻断金属层(胶层)86上形成一或多个导电层。在一些实施例中，导电层包含通过原子层沉积制程形成的钨层181及通过化学气相沉积制程形成的钨层183。此外，在导电层之上形成顶盖绝缘层185。通过一或多个沉积及化学机械研磨操作形成导电层及/或顶盖绝缘层185。在一些实施例中，顶盖绝缘层185包含氮化硅。
随后，类似于图19A，通过一或多个蚀刻操作来凹陷在栅极空间中形成的层的上部分，如图22F所示。在一些实施例中，在蚀刻操作中，并不蚀刻顶盖绝缘层185，因此保护顶盖绝缘层185底部的钨层181、183。
然后，类似于图19B，在凹陷的结构之上形成接触金属层87，如图22G所示。随后，形成栅极顶盖绝缘层90。在形成图22G所示的结构之后，在接触金属层87之上形成一或多个介电层(例如，层间介电质)。
本文所描述的各种实施例或实例提供优于现有技术的若干优势。在本揭露的实施例中，由于栅极空间完全由阻断金属层(胶层)填充，金属栅极电极中的钨层中并不形成接缝。此外，在凹陷的功函数调整材料层之上形成的钨层可保护功函数调整材料层不受在后续执行的化学机械研磨操作中所使用的化学品的影响。
应当理解，本文不必论述所有优势，所有实施例或实例并不要求特定优势，并且其他实施例或实例可提供不同优势。
根据本揭露的一个态样，在一种制作半导体装置的方法中，通过移除牺牲栅极电极形成栅极空间，在栅极空间中形成栅极介电层，在栅极介电层上形成导电层以完全填充栅极空间，凹陷栅极介电层及导电层以形成凹陷的栅极电极，以及在凹陷的栅极电极上形成接触金属层。凹陷的栅极电极并不包含钨层，并且接触金属层包含钨。在前述以及以下实施例中的一或多者中，导电层中的至少一者具有U形截面，并且导电层中的至少一者并不具有U形截面。在前述以及以下实施例中的一或多者中，导电层中并不具有U形截面的至少一者包含氮化钛或碳氮化钨。在前述以及以下实施例中的一或多者中，接触金属层覆盖栅极介电层的顶部。在前述以及以下实施例中的一或多者中，接触金属层的上表面具有朝向凹陷的栅极电极的凸出形状。在前述以及以下实施例中的一或多者中，凸出形状具有角度介于30度至60度的斜率。在前述以及以下实施例中的一或多者中，通过使用无氟钨源气体的原子层沉积来形成接触金属层。
根据本揭露的另一态样，在一种制作半导体装置的方法中，形成自置于基板之上的隔离绝缘层突出的鳍式结构，在鳍式结构之上形成牺牲栅极介电层，在牺牲栅极介电层之上形成牺牲栅极电极层，形成栅极侧壁间隔物，形成一或多个介电层；通过移除牺牲栅极电极层及牺牲栅极介电层来形成栅极空间，在形成栅极空间之后，凹陷栅极侧壁间隔物；在栅极空间中形成栅极介电层；在栅极介电层上形成导电层以完全填充栅极空间，凹陷栅极介电层及导电层以形成凹陷的栅极电极，以及在凹陷的栅极电极上形成接触金属层。在前述以及以下实施例中的一或多者中，一或多个介电层包含在栅极侧壁间隔物的侧面上共形地形成的蚀刻终止层，及在蚀刻终止层上形成的层间介电层。在前述以及以下实施例中的一或多者中，层间介电层包含氧化硅层及氮化硅层，两者均接触蚀刻终止层。在前述以及以下实施例中的一或多者中，蚀刻终止层包含氮化硅。在前述以及以下实施例中的一或多者中，在凹陷的栅极侧壁间隔物的顶部并且形成栅极介电层，栅极介电层接触蚀刻终止层。在前述以及以下实施例中的一或多者中，接触金属层为通过使用金属氯化物气体的沉积方法来形成的钨、钽、锡、铌或钼中的一者。在前述以及以下实施例中的一或多者中，在接触金属层之上形成栅极顶盖绝缘层，在栅极顶盖绝缘层之上形成一或多个介电层，以及形成接触金属层的栅极触点。在前述以及以下实施例中的一或多者中，接触金属层包含低于栅极接触的含量的氟。
根据本揭露的另一态样，一种半导体装置包含自置于基板之上的隔离绝缘层突出并且具有通道区域的鳍式结构、源极/漏极磊晶层、至于通道区域上的栅极介电层，以及置于栅极介电层上的栅极电极层。栅极电极层包含下部分及上部分，并且下部分包含导电层，导电层中的至少一者具有U形截面，并且导电层中的至少一者并不具有U形截面。在前述以及以下实施例中的一或多者中，上部分由钨制成。在前述以及以下实施例中的一或多者中，栅极介电层的截面具有U形状，并且上部分覆盖栅极介电层的U形的垂直部分的顶部。在前述以及以下实施例中的一或多者中，上部分的上表面具有朝向下部分的凸出形状，并且凸出形状具有角度介于30度至60度的斜率。在前述以及以下实施例中的一或多者中，半导体装置还包含与上部分接触并且具有高于上部分的氟浓度的栅极触点。
前述概述了若干实施例或实例的特征，使得熟悉此项技术者可更好地理解本揭露的诸态样。熟悉此项技术者应当理解，他们可容易地将本揭露用作设计或修改其他制程与结构的基础，以用于实施与本文介绍的实施例或实例相同的目的及/或达成相同的优点。熟悉此项技术者亦应认识到，此类等效构造并不偏离本揭露的精神及范畴，而是可在不偏离本揭露的精神及范畴的情况下进行各种改变、替换及更改。

Claims (10)

1.一种制作一半导体装置的方法，其特征在于，包含：
通过移除一牺牲栅极电极形成一栅极空间；
形成一栅极介电层于该栅极空间中；
形成多个导电层于该栅极介电层上以完全填充该栅极空间；
凹陷该栅极介电层及所述多个导电层以形成一凹陷的栅极电极；以及
形成一接触金属层于该凹陷的栅极电极上，
其中该凹陷的栅极电极并不包含一钨层，并且
该接触金属层包含钨。
2.如权利要求1所述的方法，其特征在于，该接触金属层覆盖该栅极介电层的一顶部。
3.如权利要求1所述的方法，其特征在于，该接触金属层的一上表面具有朝向该凹陷的栅极电极的一凸出形状。
4.一种制作一半导体装置的方法，其特征在于，包含：
形成自置于一基板之上的一隔离绝缘层突出的一鳍式结构；
形成一牺牲栅极介电层于该鳍式结构之上；
形成一牺牲栅极电极层于该牺牲栅极介电层之上；
形成多个栅极侧壁间隔物；
形成一或多个介电层；
通过移除该牺牲栅极电极层及该牺牲栅极介电层来形成一栅极空间；
在形成该栅极空间之后，凹陷所述多个栅极侧壁间隔物；
形成一栅极介电层于该栅极空间中；
形成多个导电层于该栅极介电层上以完全填充该栅极空间；
凹陷该栅极介电层及所述多个导电层以形成一凹陷的栅极电极；以及
形成一接触金属层于该凹陷的栅极电极上。
5.如权利要求4所述的方法，其特征在于，该一或多个介电层包含在所述多个栅极侧壁间隔物的多个侧面上共形地形成的一蚀刻终止层，及在该蚀刻终止层上形成的一层间介电层。
6.如权利要求5所述的方法，其特征在于，该层间介电层包含一氧化硅层及一氮化硅层，该氧化硅层及该氮化硅层均接触该蚀刻终止层。
7.如权利要求5所述的方法，其特征在于，还包含：
形成一栅极顶盖绝缘层于该接触金属层之上；
形成一或多个介电层于该栅极顶盖绝缘层之上；以及
形成接触该接触金属层的一栅极触点。
8.一种半导体装置，其特征在于，包含：
一鳍式结构，自置于一基板之上的一隔离绝缘层突出并且具有一通道区域；
一源极/漏极磊晶层；
一栅极介电层，置于该通道区域上；以及
一栅极电极层，置于该栅极介电层上，其中：
该栅极电极层包含一下部分及一上部分，并且
该下部分包含多个导电层，所述多个导电层中的至少一者具有U形截面，并且所述多个导电层中的至少一者并不具有U形截面。
9.如权利要求8所述的半导体装置，其特征在于，其中：
该栅极介电层在一截面上具有一U形，并且
该栅极电极层的该上部分覆盖该栅极介电层的该U形的一垂直部分的一顶部。
10.如权利要求8所述的半导体装置，其特征在于，其中：
该栅极电极层的该上部分的一上表面具有朝向该下部分的一凸出形状，并且
该凸出形状具有一角度介于30度至60度的一斜率。
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