CN113130323B - Manufacturing method of embedded SiP epitaxial layer - Google Patents
Manufacturing method of embedded SiP epitaxial layer Download PDFInfo
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- CN113130323B CN113130323B CN202110330208.XA CN202110330208A CN113130323B CN 113130323 B CN113130323 B CN 113130323B CN 202110330208 A CN202110330208 A CN 202110330208A CN 113130323 B CN113130323 B CN 113130323B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 53
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 53
- 239000010703 silicon Substances 0.000 claims abstract description 53
- 238000000407 epitaxy Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000013078 crystal Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 50
- 239000007789 gas Substances 0.000 claims description 34
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 21
- 239000011574 phosphorus Substances 0.000 claims description 21
- 229910052698 phosphorus Inorganic materials 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 239000012159 carrier gas Substances 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 claims description 6
- 229910003818 SiH2Cl2 Inorganic materials 0.000 claims description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 238000007796 conventional method Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention discloses a manufacturing method of an embedded SiP epitaxial layer, which comprises the following steps: etching the silicon substrate to form a plurality of grooves; filling an embedded SiP epitaxial layer in the groove, wherein the embedded SiP epitaxial layer comprises the following sub-steps: step 21, forming a SiP seed crystal layer on silicon on the inner side surface of the groove; step 22, performing selective epitaxial growth to form a SiP main body layer on the surface of the SiP seed crystal layer; the SiP main body layer in the groove has a structure that the thickness at the side surface is larger than the thickness at the middle position, and the SiP main body layer is concave in the middle; and step 23, performing selective epitaxial growth to form a top silicon layer on the surface of the SiP main body layer, and filling the middle concave structure of the SiP main body layer by the top silicon layer by utilizing the characteristic that the step coverage capability of silicon epitaxy is superior to that of SiP epitaxy. The invention can improve the step coverage of the embedded SiP epitaxial layer in the groove and thus improve the roughness of the surface of the embedded SiP epitaxial layer.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing an embedded SiP epitaxial layer.
Background
With the development of technology, the Critical Dimension (CD) of the device is smaller and smaller, and when the process node of the device is below 14nm, the source region and the drain region of the NMOS need to adopt an embedded SiP epitaxial layer to change the stress of the channel region, so as to improve the mobility of carriers and thus the performance of the device. For a source region and a drain region of a 14nm NMOS, a U-shaped groove is formed by dry etching, then SiP is grown in the groove and divided into two layers, one layer which is closely attached to the groove wall is a first layer (L1), namely a SiP seed crystal layer (buffer layer), then a second layer (L2), and the second layer is a main layer (bulk layer). The growth of the L2 layer presents a thick near the sides of the sidewall and thin in the middle due to process problems, which directly affects the device performance.
The prior art method is described in further detail below with reference to the accompanying drawings:
as shown in fig. 1A to 1C, the structure of the device in each step of the conventional method for manufacturing an embedded SiP epitaxial layer is schematically shown; the existing manufacturing method of the embedded SiP epitaxial layer comprises the following steps:
step one, as shown in fig. 1A, a groove 105 is formed in a silicon substrate 101 by adopting a dry etching process, and the cross section of the groove 105 is in a U-shaped structure. The silicon substrate 101 has a single crystal structure and a circular top view, and therefore the silicon substrate 101 is generally a wafer structure.
Typically, a gate structure is formed on the silicon substrate 101, and the grooves 105 are self-aligned in the grooves 105 formed on both sides of the gate structure.
The gate structure includes a gate dielectric layer and a polysilicon gate 102 stacked in sequence.
A top hard mask layer 103 is covered on the top of the polysilicon gate 102, and a side wall 104 is formed on the side surface of the polysilicon gate 102.
Typically, the material of the top hard mask layer 103 comprises silicon oxide or silicon nitride.
The material of the side wall 104 includes silicon oxide or silicon nitride.
And secondly, filling an embedded SiP epitaxial layer 106 in the groove 105. Typically, the epitaxial growth process of the embedded SiP epitaxial layer 106 is a selective epitaxial growth process.
The filling process of the embedded SiP epitaxial layer 106 comprises two substeps, which are sequentially:
as shown in fig. 1B, the SiP seed layer 106a is formed. The SiP seed layer 106a provides a SiP seed for the subsequent SiP bulk layer 106b, as well as a buffer layer between Si and the SiP bulk layer 106 b.
As shown in fig. 1C, selective epitaxial growth is performed to form a SiP bulk layer 106b on the surface of the SiP seed layer 106 a; the SiP body layer 106b has a thickness at the side of the recess 105 greater than that at the middle of the recess 105 in the recess 105, and the SiP body layer 106b has a structure of being concave in the middle. The intermediate recessed structure of the SiP body layer 106b is shown as 107.
The doping concentration of the SiP bulk layer 106b is greater than the doping concentration of the SiP seed layer 106a.
The intermediate recessed structure 107 of the SiP body layer 106b may deteriorate the roughness of the surface of the embedded SiP epitaxial layer 106. As shown in fig. 2, a TEM photograph of an embedded SiP epitaxial layer formed by a conventional method for manufacturing an embedded SiP epitaxial layer; the top surface of the embedded SiP epitaxial layer 106' has a central recessed structure that ultimately affects the performance of the device.
Disclosure of Invention
The invention aims to provide a manufacturing method of an embedded SiP epitaxial layer, which can improve the step coverage of the embedded SiP epitaxial layer in a groove and further improve the roughness of the surface of the embedded SiP epitaxial layer.
In order to solve the technical problems, the manufacturing method of the embedded SiP epitaxial layer provided by the invention comprises the following steps:
etching the silicon substrate to form a plurality of grooves.
Filling an embedded SiP epitaxial layer in the groove, wherein the embedded SiP epitaxial layer comprises the following sub-steps:
and step 21, performing selective epitaxial growth to form a SiP seed crystal layer on the silicon on the inner side surface of the groove.
Step 22, performing selective epitaxial growth to form a SiP main body layer on the surface of the SiP seed crystal layer; the SiP main body layer in the groove has a thickness at the side surface of the groove which is larger than that at the middle position of the groove, and is in a structure with a concave middle.
And 23, performing selective epitaxial growth to form a top silicon layer on the surface of the SiP main body layer, and filling the middle concave structure of the SiP main body layer by the top silicon layer by utilizing the characteristic that the step coverage capability of silicon epitaxy is superior to that of SiP epitaxy, and stacking the SiP seed crystal layer, the SiP main body layer and the top silicon layer to form the embedded SiP epitaxial layer.
A further improvement is that the doping concentration of the SiP bulk layer is greater than the doping concentration of the SiP seed layer.
In the second step, the selective epitaxial growth of the step 21, the step 22 and the step 23 is continuously carried out, and the process conditions of the selective epitaxial growth of the step 21 and the step 22 comprise: the temperature is 500-800 ℃, and the cavity pressure is 1-100 torr; the process gas comprises: silicon source gas, phosphorus source gas, HCl and carrier gas.
And regulating the phosphorus doping concentration in the SiP seed crystal layer and the SiP main body layer by regulating the flow of the phosphorus source gas, wherein the larger the flow of the phosphorus source gas is, the larger the phosphorus doping concentration is.
The process conditions for the selective epitaxial growth of step 23 include: the temperature is 500-800 ℃, and the cavity pressure is 1-100 torr; the process gas comprises: silicon source gas, HCl, and carrier gas.
A further improvement is that the silicon source gas comprises SiH2Cl2 or SiH4, the phosphorus source gas comprises PH3, and the carrier gas comprises H2 and N2.
The further improvement is that the gas flow rate of the carrier gas is 1 slm-50 slm, the flow rate of the silicon source gas is 1 sccm-1000 sccm, the flow rate of the phosphorus source gas is 1 sccm-1000 sccm, and the flow rate of the HCl is 1 sccm-1000 sccm.
In a further improvement, in the first step, a gate structure is formed on the silicon substrate, and the grooves are formed on two sides of the gate structure in a self-aligned mode.
The gate structure comprises a gate dielectric layer and a polysilicon gate which are sequentially overlapped.
And a top hard mask layer is covered on the top of the polysilicon gate, and a side wall is formed on the side surface of the polysilicon gate.
In the first step, the etching process for forming the grooves is dry etching or dry etching humidifying etching; the cross section of the groove is of a U-shaped structure or of a sigma-shaped structure.
The embedded SiP epitaxial layers are formed on two sides of the grid structure of the NMOS tube, and the method further comprises the step of performing source drain injection in the embedded SiP epitaxial layers on two sides of the NMOS tube to form a source region and a drain region.
Further improvement is that the technical nodes of the NMOS tube comprise 40nm, 28nm and below 14 nm.
In a further improvement, in the process node below 14nm, the NMOS is a FinFET, and in the first step, the fin body is formed on the silicon substrate.
In a further improvement, in the first step, the groove is formed in the fin body.
A further improvement is that the gate structure in step one is the final gate structure.
The method is characterized in that the final gate structure is a metal gate, and the method further comprises the step of replacing the gate structure with a high-dielectric-constant metal gate, wherein the high-dielectric-constant metal gate comprises a second gate dielectric layer and a metal gate, and the second gate dielectric layer comprises a high-dielectric-constant material.
A further improvement is that the metal gate includes an N-type work function layer therein.
A further improvement is that the high dielectric constant material comprises hafnium oxide.
Aiming at the defect that the step coverage of the SiP epitaxy is poor, so that a rough structure with thick side walls and thin middle part of the SiP main body layer can appear, a silicon epitaxy process is added after the SiP main body layer is formed, the middle concave structure of the SiP main body layer is filled up by utilizing the characteristic that the step coverage of the silicon epitaxy is better than the step coverage of the SiP epitaxy through a top silicon layer formed by the silicon epitaxy, the step coverage of an embedded SiP epitaxial layer in a groove can be improved, the roughness of the surface of the embedded SiP epitaxial layer is improved, and the performance of a device can be improved.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIGS. 1A-1C are schematic views of a device structure at various steps in a conventional method for fabricating an embedded SiP epitaxial layer;
fig. 2 is a TEM photograph of an embedded SiP epitaxial layer formed by a conventional method for manufacturing an embedded SiP epitaxial layer;
FIG. 3 is a flow chart of a method of fabricating an embedded SiP epitaxial layer according to an embodiment of the present invention;
fig. 4A to fig. 4D are schematic views of device structures in steps of a method for manufacturing an embedded SiP epitaxial layer according to an embodiment of the present invention;
fig. 5 is a TEM photograph of an embedded SiP epitaxial layer formed by the method for manufacturing an embedded SiP epitaxial layer according to the embodiment of the present invention.
Detailed Description
As shown in fig. 3, a flowchart of a method for manufacturing an embedded SiP epitaxial layer 6 according to an embodiment of the present invention is shown; as shown in fig. 4A to 4D, the device structure of the embedded SiP epitaxial layer 6 according to the embodiment of the present invention in each step of the manufacturing method is schematically shown; the manufacturing method of the embedded SiP epitaxial layer 6 comprises the following steps:
step one, as shown in fig. 4A, etching is performed on the silicon substrate 1to form a plurality of grooves 5.
A gate structure is formed on the silicon substrate 1, and the grooves 5 are formed on two sides of the gate structure in a self-aligned manner.
The gate structure comprises a gate dielectric layer and a polysilicon gate 2 which are sequentially overlapped.
The top of the polysilicon gate 2 is covered with a top hard mask layer 3, and a side wall 4 is formed on the side surface of the polysilicon gate 2.
In the embodiment of the present invention, the etching process for forming the groove 5 is dry etching, and the cross section of the groove 5 has a U-shaped structure. In other embodiments can also be: the etching process for forming the groove 5 is dry etching and humidifying etching; the cross section of the groove 5 is sigma-type.
Step two, filling an embedded SiP epitaxial layer 6 in the groove 5, which comprises the following sub-steps:
in step 21, as shown in fig. 4B, selective epitaxial growth is performed to form a SiP seed layer 6a on the silicon on the inner side surface of the recess 5. The SiP seed layer 6a provides a SiP seed for the subsequent SiP bulk layer 6b, as well as a buffer layer between Si and the SiP bulk layer.
Step 22, as shown in fig. 4C, performing selective epitaxial growth to form a SiP bulk layer 6b on the surface of the SiP seed layer 6 a; the SiP body layer 6b has a thickness at the side of the recess 5 greater than that at the middle of the recess 5 in the recess 5, and the SiP body layer 6b has a structure of being concave in the middle. The intermediate recessed structure of the SiP body layer 6b is shown as 7.
The doping concentration of the SiP bulk layer 6b is greater than the doping concentration of the SiP seed layer 6a.
In step 23, as shown in fig. 4D, a top silicon layer 6c is formed on the surface of the SiP main body layer 6b by performing selective epitaxial growth, and the embedded SiP epitaxial layer 6 is formed by stacking the SiP seed layer 6a, the SiP main body layer 6b and the top silicon layer 6c by using the characteristic that the step coverage capability of silicon epitaxy is better than that of SiP epitaxy, so that the top silicon layer 6c fills up the middle concave structure of the SiP main body layer 6 b.
In the second step, the selective epitaxial growth of step 21, step 22 and step 23 is continuously performed, and the process conditions of the selective epitaxial growth of step 21 and step 22 include: the temperature is 500-800 ℃, and the cavity pressure is 1-100 torr; the process gas comprises: silicon source gas, phosphorus source gas, HCl and carrier gas.
The phosphorus doping concentration in the SiP seed layer 6a and the SiP bulk layer 6b is adjusted by adjusting the flow rate of the phosphorus source gas, the larger the flow rate of the phosphorus source gas is, the larger the phosphorus doping concentration is.
The process conditions for the selective epitaxial growth of step 23 include: the temperature is 500-800 ℃, and the cavity pressure is 1-100 torr; the process gas comprises: silicon source gas, HCl, and carrier gas.
The silicon source gas comprises SiH2Cl2 or SiH4, the phosphorus source gas comprises PH3, and the carrier gas comprises H2 and N2.
The flow rate of the carrier gas is 1 slm-50 slm, the flow rate of the silicon source gas is 1 sccm-1000 sccm, the flow rate of the phosphorus source gas is 1 sccm-1000 sccm, and the flow rate of the HCl is 1 sccm-1000 sccm.
The embedded SiP epitaxial layers 6 are formed on two sides of the grid structure of the NMOS tube, and the second step further comprises the step of injecting source and drain into the embedded SiP epitaxial layers 6 on two sides of the NMOS tube to form a source region and a drain region.
The technical nodes of the NMOS tube comprise 40nm, 28nm and below 14 nm.
In the process node below 14nm, the NMOS is a FinFET, and in the first step, a fin body is formed on the silicon substrate 1. The grooves 5 are formed in the fin body. The gate structure covers the top surface and the sides of the fin body.
In the embodiment of the invention, the final gate structure is a metal gate, and the subsequent step further comprises the step of replacing the gate structure with a high-dielectric-constant metal gate, wherein the high-dielectric-constant metal gate comprises a second gate dielectric layer and a metal gate, and the second gate dielectric layer comprises a high-dielectric-constant material. The metal gate comprises an N-type work function layer. The high dielectric constant material includes hafnium oxide. In other embodiments can also be: the gate structure in the first step is a final gate structure.
Aiming at the defect that the step coverage performance of the SiP epitaxy is poor, so that a rough structure with thick side walls and thin middle part of the SiP main body layer 6b can appear, a silicon epitaxy process is added after the SiP main body layer 6b is formed, the middle concave structure of the SiP main body layer 6b is filled up through a top silicon layer 6c formed by silicon epitaxy by utilizing the characteristic that the step coverage performance of the silicon epitaxy is better than that of the SiP epitaxy, and finally, the step coverage performance of the embedded SiP epitaxial layer 6 in the groove 5 can be improved, and the roughness of the surface of the embedded SiP epitaxial layer 6 can be improved.
As shown in fig. 5, a TEM photograph of the embedded SiP epitaxial layer formed by the method for manufacturing the embedded SiP epitaxial layer according to the embodiment of the present invention shows that the surface of the embedded SiP epitaxial layer 6' is flat, has no concave structure, and has good roughness.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (15)
1. The manufacturing method of the embedded SiP epitaxial layer is characterized by comprising the following steps of:
step one, forming a grid structure on a silicon substrate, etching the silicon substrate, and forming a plurality of grooves on two sides of the grid structure in a self-aligned mode;
filling an embedded SiP epitaxial layer in the groove, wherein the embedded SiP epitaxial layer comprises the following sub-steps:
step 21, performing selective epitaxial growth to form a SiP seed crystal layer on the silicon on the inner side surface of the groove;
step 22, performing selective epitaxial growth to form a SiP main body layer on the surface of the SiP seed crystal layer; the SiP main body layer in the groove has a thickness which is larger at the side surface of the groove than at the middle position of the groove, and is in a structure with a concave middle;
and 23, performing selective epitaxial growth to form a top silicon layer on the surface of the SiP main body layer, and filling the middle concave structure of the SiP main body layer by the top silicon layer by utilizing the characteristic that the step coverage capability of silicon epitaxy is superior to that of SiP epitaxy, and stacking the SiP seed crystal layer, the SiP main body layer and the top silicon layer to form the embedded SiP epitaxial layer.
2. The method for manufacturing an embedded SiP epitaxial layer according to claim 1, wherein: the doping concentration of the SiP main body layer is larger than that of the SiP seed crystal layer.
3. The method for manufacturing an embedded SiP epitaxial layer according to claim 1, wherein: in the second step, the selective epitaxial growth of step 21, step 22 and step 23 is continuously performed, and the process conditions of the selective epitaxial growth of step 21 and step 22 include: the temperature is 500-800 ℃, and the cavity pressure is 1-100 torr; the process gas comprises: silicon source gas, phosphorus source gas, HCl and carrier gas;
adjusting the phosphorus doping concentration in the SiP seed crystal layer and the SiP main body layer by adjusting the flow of the phosphorus source gas, wherein the larger the flow of the phosphorus source gas is, the larger the phosphorus doping concentration is;
the process conditions for the selective epitaxial growth of step 23 include: the temperature is 500-800 ℃, and the cavity pressure is 1-100 torr; the process gas comprises: silicon source gas, HCl, and carrier gas.
4. A method of manufacturing an embedded SiP epitaxial layer as claimed in claim 3, wherein: the silicon source gas comprises SiH2Cl2 or SiH4, the phosphorus source gas comprises PH3, and the carrier gas comprises H2 and N2.
5. The method for manufacturing an embedded SiP epitaxial layer according to claim 4, wherein: the flow rate of the carrier gas is 1 slm-50 slm, the flow rate of the silicon source gas is 1 sccm-1000 sccm, the flow rate of the phosphorus source gas is 1 sccm-1000 sccm, and the flow rate of the HCl is 1 sccm-1000 sccm.
6. The method for manufacturing an embedded SiP epitaxial layer according to claim 1, wherein:
the gate structure comprises a gate dielectric layer and a polysilicon gate which are sequentially overlapped;
and a top hard mask layer is covered on the top of the polysilicon gate, and a side wall is formed on the side surface of the polysilicon gate.
7. The method for manufacturing an embedded SiP epitaxial layer according to claim 1, wherein: in the first step, the etching process for forming the groove is dry etching or dry etching humidifying etching; the cross section of the groove is of a U-shaped structure or of a sigma-shaped structure.
8. The method for manufacturing an embedded SiP epitaxial layer according to claim 6, wherein: the embedded SiP epitaxial layers are formed on two sides of the grid structure of the NMOS tube, and the method further comprises the step of injecting source and drain into the embedded SiP epitaxial layers on two sides of the NMOS tube to form a source region and a drain region.
9. The method for manufacturing an embedded SiP epitaxial layer according to claim 8, wherein: the technical nodes of the NMOS tube comprise 40nm, 28nm and below 14 nm.
10. The method for manufacturing an embedded SiP epitaxial layer according to claim 9, wherein: in the process node below 14nm, the NMOS is a FinFET, and in the first step, a fin body is formed on the silicon substrate.
11. The method for manufacturing an embedded SiP epitaxial layer according to claim 10, wherein: in the first step, the groove is formed in the fin body.
12. The method for manufacturing an embedded SiP epitaxial layer according to claim 8, wherein: the gate structure in the first step is a final gate structure.
13. The method for manufacturing an embedded SiP epitaxial layer according to claim 8, wherein: the final gate structure is a metal gate, and the subsequent step further comprises the step of replacing the gate structure with a high-dielectric-constant metal gate, wherein the high-dielectric-constant metal gate comprises a second gate dielectric layer and a metal gate, and the second gate dielectric layer comprises a high-dielectric-constant material.
14. The method for manufacturing an embedded SiP epitaxial layer according to claim 13, wherein: the metal gate comprises an N-type work function layer.
15. The method for manufacturing an embedded SiP epitaxial layer according to claim 13, wherein: the high dielectric constant material includes hafnium oxide.
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