CN109473480A - NMOS tube and its manufacturing method - Google Patents

NMOS tube and its manufacturing method Download PDF

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Publication number
CN109473480A
CN109473480A CN201811267159.4A CN201811267159A CN109473480A CN 109473480 A CN109473480 A CN 109473480A CN 201811267159 A CN201811267159 A CN 201811267159A CN 109473480 A CN109473480 A CN 109473480A
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China
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layer
silicon
gate structure
nmos tube
phosphorus
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陈品翰
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

The invention discloses a kind of NMOS tubes, comprising: is formed with p-well on the surface of silicon substrate；Gate structure is formed on p-well surface；It is formed in the two sides of gate structure fluted；Embedded epitaxial layer in a groove, embedded epitaxial layer include: silicon seed layer, silicon phosphorus body layer, and the shielded layer between silicon phosphorus body layer and silicon seed layer is projected into the silicon cap layer of groove top；Silicon phosphorus body layer has the structure of phosphorus heavy doping, and the quantity that the phosphorus that shielded layer is used to reduce embedded epitaxial layer is extended out into the p-well of side is to reduce and prevent the influence of the channel of the phosphorus pair extended out.The invention also discloses a kind of manufacturing methods of NMOS tube.The present invention can improve the short-channel effect of device and thereby improve the stability of device.

Description

NMOS tube and its manufacturing method
Technical field
The present invention relates to semiconductor integrated circuit manufacturing field, in particular to a kind of NMOS tube；The invention further relates to one kind The manufacturing method of NMOS tube.
Background technique
HKMG has the gate dielectric layer and metal gate (MG) of high dielectric constant (HK), therefore is commonly abbreviated as in this field HKMG.Using in the MOS transistor of HKMG, the source region of NMOS and drain region often use embedded epitaxial layer, and NMOS's is embedded The material of epitaxial layer is usually SiP, changes the stress of the channel region of NMOS by embedded epitaxial layer and is formed with conducive to improvement The tensile stress of the mobility of the electronics of the channel region of NMOS, so as to improve NMOS channel region electron mobility, reduce ditch Road resistance.
With the development of technology, the critical size (CD) of device is smaller and smaller, and the technology node of such as existing HKMG technique is CD has reached 28nm hereinafter, this makes the short-channel effect (short channel effect) of device increasingly severe, makes device The stability of the performance of part such as device is by serious influence.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of NMOS tubes, can improve the short-channel effect of device, improve The stability of device.For this purpose, the present invention also provides a kind of manufacturing methods of NMOS tube.
In order to solve the above technical problems, NMOS tube provided by the invention includes:
P-well is formed on the surface of silicon substrate.
It is formed with gate structure on the p-well surface, the p-well surface covered by the gate structure is used to form ditch Road.
It is formed in the p-well of the two sides of the gate structure fluted.
The embedded epitaxial layer in the groove, the embedded epitaxial layer include:
It is formed in the silicon seed layer (Si seed) of the inner surface of the groove, the silicon phosphorus (SiP) that the groove is filled Body layer (Body), the shielded layer (barrier layer) between the silicon phosphorus body layer and the silicon seed layer are prominent To the silicon cap layer (Cap) of the groove top.
The silicon cap layer covers the surface of the silicon seed layer, the silicon phosphorus body layer and the shielded layer.
The silicon phosphorus body layer has the structure of phosphorus heavy doping.The shielded layer is for reducing the embedded epitaxial layer Quantity that phosphorus is extended out into the p-well of side to reduce and prevent the influence of the channel of the phosphorus pair extended out, so as to Improve the short-channel effect of device and thereby improves the stability of device.
A further improvement is that the gate structure is HKMG.
A further improvement is that be formed in the embedded epitaxial layer of the gate structure two sides by N+ district's groups at Source region and drain region.
A further improvement is that the material of the shielded layer is silicon carbide (SiC).
A further improvement is that the gate structure is defined by pseudo- grid structure, dummy gate structure is in the source region and institute It states after drain region is formed and removes, and form the gate structure in the region of dummy gate structure removal.
Dummy gate structure includes the first gate dielectric layer and polysilicon puppet grid for being formed in the p-well surface.
A further improvement is that the groove autoregistration is defined in the two sides of the polysilicon puppet grid, the source region and institute State the two sides that drain region autoregistration is defined in the polysilicon puppet grid.
A further improvement is that the two sides of the groove are all in " ∑ " shape.
A further improvement is that the two sides in dummy gate structure are formed with silicon nitride spacer.
A further improvement is that also while being integrated with PMOS tube, the length of the channel of the NMOS tube on the silicon substrate Degree is 28nm or less.
In order to solve the above technical problems, the manufacturing method of NMOS tube provided by the invention includes the following steps:
Step 1: providing the silicon substrate that surface is formed with p-well, pseudo- grid structure, the puppet grid are formed on the surface of the p-well The p-well surface of structure institute overlay area is used to form channel.
Step 2: performing etching to form groove to the silicon in the p-well of dummy gate structure two sides.
Step 3: forming embedded epitaxial layer in the groove, including as follows step by step:
Step 31, the inner surface formation silicon seed layer in the groove.
Step 32 forms shielded layer on the silicon seed layer surface.
Step 33, formation silicon phosphorus body layer fill the groove.
Step 34 forms silicon cap layer, and the silicon cap layer is by the silicon seed layer, the silicon phosphorus body layer and the screen The surface covering and the silicon cap layer for covering layer are projected into the groove top.
The silicon phosphorus body layer has the structure of phosphorus heavy doping.The shielded layer is for reducing the embedded epitaxial layer Quantity that phosphorus is extended out into the p-well of side to reduce and prevent the influence of the channel of the phosphorus pair extended out, so as to Improve the short-channel effect of device and thereby improves the stability of device.
Step 4: carrying out self aligned N+ ion implanting in the embedded epitaxial layer of the two sides of dummy gate structure Form source region and drain region.
Step 5: removal dummy gate structure, forms the gate structure of NMOS tube in dummy gate structure removal region.
A further improvement is that the gate structure is HKMG.
A further improvement is that dummy gate structure includes the first gate dielectric layer and polycrystalline for being formed in the p-well surface Silicon puppet grid.
A further improvement is that the groove autoregistration is defined in the two sides of the polysilicon puppet grid.
A further improvement is that the two sides of the groove are all in " ∑ " shape.
A further improvement is that the two sides in dummy gate structure are formed with silicon nitride spacer.
A further improvement is that the material of the shielded layer is silicon carbide.
A further improvement is that also while being integrated with PMOS tube, the length of the channel of the NMOS tube on the silicon substrate Degree is 28nm or less.
The present invention has done special setting to the superimposed layer structure of the embedded epitaxial layer of NMOS tube, is being located in groove The silicon seed layer of side surface and will groove filling silicon phosphorus body layer between increase shielded layer, moreover, the phosphorus doping of shielded layer For the structure being lightly doped, the shielded layer that this phosphorus is lightly doped the phosphorus diffusion of the silicon phosphorus body layer of phosphorus heavy doping can be carried out buffering or Stop, thus the quantity that the phosphorus for reducing embedded epitaxial layer is extended out into the p-well of side, also to can be reduced and prevent to extend out The influence of the channel of phosphorus pair, so as to improve the short-channel effect of device and thereby the stability of device can be improved.
The present invention is especially suitable in the 28nm technique NMOS tube below with HKMG, and NMOS tube can and PMOS tube one It rises and is integrated on same silicon substrate.The present invention will not adversely affect PMOS tube.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Figure 1A-Figure 1B is the device junction composition in each step of the manufacturing method of existing NMOS tube；
Fig. 2A-Fig. 2 B is the device junction composition in each step of the manufacturing method of NMOS tube of the embodiment of the present invention.
Specific embodiment
The manufacturing method of existing NMOS tube:
The manufacturing method that existing NMOS tube is first introduced before the embodiment of the present invention is discussed in detail, such as Figure 1A to Figure 1B It is shown, it is the device junction composition in each step of the manufacturing method of existing NMOS tube；The manufacturing method of existing NMOS tube includes such as Lower step:
Step 1: as shown in Figure 1A, providing the silicon substrate that surface is formed with p-well 101, being formed on the surface of the p-well 101 101 surface of the p-well of pseudo- grid structure, dummy gate structure institute overlay area is used to form channel 103.
Dummy gate structure includes the first gate dielectric layer and polysilicon puppet grid 102 for being formed in 101 surface of p-well.
Silicon nitride spacer is formed in the two sides of dummy gate structure.
Step 2: as shown in Figure 1A, the silicon in the p-well 101 of dummy gate structure two sides is performed etching to be formed it is recessed Slot 104.
104 autoregistration of groove is defined in the two sides of the polysilicon puppet grid 102.
The two sides of the groove 104 are all in " ∑ " shape.
Step 3: as shown in Figure 1B, forming embedded epitaxial layer in the groove 104, including as follows step by step:
Step 31, the inner surface formation silicon seed layer 105a in the groove 104.
Step 32, formation silicon phosphorus body layer 105b fill the groove 104.
Step 34 forms silicon cap layer 105C, and the silicon cap layer 105c is by the silicon seed layer 105c and the silicon phosphorus The surface of body layer 105b covers and the silicon cap layer 105d is projected into 104 top of groove.
Step 4: carrying out self aligned N+ ion implanting in the embedded epitaxial layer of the two sides of dummy gate structure Form source region and drain region.
Step 5: removal dummy gate structure, forms the gate structure of NMOS tube in dummy gate structure removal region.
The gate structure is HKMG.
Also be integrated with PMOS tube simultaneously on the silicon substrate, the length of the channel 103 of the NMOS tube for 1028nm with Under.
In the NMOS tube that existing method is formed, the phosphorus doping of the silicon phosphorus body layer 105b is easy to diffuse into the P outside The channel 103 can in trap 101 and finally be had an impact, be easy to reduce the length of the channel 103 further, thus It can aggravate the short-channel effect of device, finally influence the stability of device.
Device of the embodiment of the present invention:
The structure of device of the embodiment of the present invention can refer to structure shown in Fig. 2 B, and NMOS tube of the embodiment of the present invention include:
P-well 1 is formed on the surface of silicon substrate.
It is formed with gate structure on 1 surface of p-well, is used to form by 1 surface of the p-well that the gate structure covers Channel 3, the channel 3 are only just formed when device is opened, are also just increased on the gate structure in the grid of threshold voltage The meeting transoid of the p-well 1 of the gate structure bottom is when pole tension to form the channel 3.
Fluted 4 are formed in the p-well 1 of the two sides of the gate structure.
The embedded epitaxial layer in the groove 4, the embedded epitaxial layer include:
It is formed in the silicon seed layer 5a of the inner surface of the groove 4, the silicon phosphorus body layer 5b that the groove 4 is filled, Shielded layer 5c between the silicon phosphorus body layer 5b and the silicon seed layer 5a is projected into the silicon lid at 4 top of groove Cap layers 5d.
The silicon cap layer 5d covers the surface of the silicon seed layer 5a, the silicon phosphorus body layer 5b and the shielded layer 5c Lid.
The silicon phosphorus body layer 5b has the structure of phosphorus heavy doping, and the material of the shielded layer 5c is silicon carbide.The screen Layer 5c is covered for reducing the quantity that the phosphorus of the embedded epitaxial layer is extended out into the p-well 1 of side to reduce and prevent The influence of the channel 3 of the phosphorus pair extended out, so as to improve 3 effect of short channel of device and thereby improve the stabilization of device Degree.
In the embodiment of the present invention, the gate structure is HKMG.The embedded extension in the gate structure two sides Layer in be formed with by N+ district's groups at source region and drain region.
The gate structure is defined by pseudo- grid structure, and dummy gate structure is gone after the source region and the drain region are formed It removes, and forms the gate structure in the region of dummy gate structure removal.Dummy gate structure includes being formed in the p-well The first gate dielectric layer such as gate oxide and polysilicon puppet grid 2 on 1 surface.Namely dummy gate structure is only shown in Fig. 2 B, also Do not show that the gate structure, the gate structure can re-form after dummy gate structure removal.
4 autoregistration of groove is defined in the two sides of the polysilicon puppet grid 2, and the source region and the drain region autoregistration are fixed Justice is in the two sides of the polysilicon puppet grid 2.
The two sides of the groove 4 are all in " ∑ " shape.
Silicon nitride spacer is formed in the two sides of dummy gate structure.
PMOS tube is gone back while is integrated on the silicon substrate, and the length of the channel 3 of the NMOS tube is 28nm or less.
The embodiment of the present invention has done special setting to the superimposed layer structure of the embedded epitaxial layer of NMOS tube, recessed being located at The silicon seed layer 5a of the inner surface of slot 4 and shielded layer 5c will be increased between silicon phosphorus body layer 5b that groove 4 is filled, moreover, The phosphorus doping of shielded layer 5c is the structure being lightly doped, and the shielded layer 5c that this phosphorus is lightly doped can be to the silicon phosphorus body layer of phosphorus heavy doping The phosphorus diffusion of 5b is buffered or is stopped, thus the quantity that the phosphorus for reducing embedded epitaxial layer is extended out into the p-well 1 of side, To can be reduced and prevent the influence of the channel 3 of the phosphorus pair extended out, so as to improve 3 effect of short channel of device and thereby can change The stability of kind device.
The embodiment of the present invention especially suitable in the 28nm technique NMOS tube below with HKMG, and NMOS tube can and PMOS tube is integrated in together on same silicon substrate.
It is the device architecture in each step of the manufacturing method of NMOS tube of the embodiment of the present invention as shown in Fig. 2A to Fig. 2 B Figure, the manufacturing method of NMOS tube of the embodiment of the present invention include the following steps:
Step 1: as shown in Figure 2 A, providing the silicon substrate that surface is formed with p-well 1, forming pseudo- grid on the surface of the p-well 1 1 surface of the p-well of structure, dummy gate structure institute overlay area is used to form channel 3.
Dummy gate structure includes the first gate dielectric layer and polysilicon puppet grid 2 for being formed in 1 surface of p-well.
Silicon nitride spacer is formed in the two sides of dummy gate structure.
Step 2: as shown in Figure 2 A, performing etching to form groove to the silicon in the p-well 1 of dummy gate structure two sides 4。
4 autoregistration of groove is defined in the two sides of the polysilicon puppet grid 2.
The two sides of the groove 4 are all in " ∑ " shape.
Step 3: as shown in Figure 2 B, forming embedded epitaxial layer in the groove 4, including as follows step by step:
Step 31, the inner surface formation silicon seed layer 5a in the groove 4.
Step 32 forms shielded layer 5c on the surface the silicon seed layer 5a.
Step 33, formation silicon phosphorus body layer 5b fill the groove 4.
Step 34 forms silicon cap layer 5d, and the silicon cap layer 5d is by the silicon seed layer 5a, the silicon phosphorus body layer 5b Surface covering and the silicon cap layer 5d with the shielded layer 5c are projected into 4 top of groove.
The silicon phosphorus body layer 5b has the structure of phosphorus heavy doping, and the material of the shielded layer 5c is silicon carbide.The screen Layer 5c is covered for reducing the quantity that the phosphorus of the embedded epitaxial layer is extended out into the p-well 1 of side to reduce and prevent The influence of the channel 3 of the phosphorus pair extended out, so as to improve 3 effect of short channel of device and thereby improve the stabilization of device Degree.
Step 4: carrying out self aligned N+ ion implanting in the embedded epitaxial layer of the two sides of dummy gate structure Form source region and drain region.
Step 5: removal dummy gate structure, forms the gate structure of NMOS tube in dummy gate structure removal region.
The gate structure is HKMG.
PMOS tube is gone back while is integrated on the silicon substrate, and the length of the channel 3 of the NMOS tube is 28nm or less.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered It is considered as protection scope of the present invention.

Claims (15)

1. a kind of NMOS tube characterized by comprising
P-well is formed on the surface of silicon substrate；
It is formed with gate structure on the p-well surface, the p-well surface covered by the gate structure is used to form channel；
It is formed in the p-well of the two sides of the gate structure fluted；
The embedded epitaxial layer in the groove, the embedded epitaxial layer include:
It is formed in the silicon seed layer of the inner surface of the groove, the silicon phosphorus body layer that the groove is filled is located at the silicon Shielded layer between phosphorus body layer and the silicon seed layer is projected into the silicon cap layer of the groove top；
The silicon cap layer covers the surface of the silicon seed layer, the silicon phosphorus body layer and the shielded layer；
The silicon phosphorus body layer has a structure of phosphorus heavy doping, the shielded layer be used to reduce the phosphorus of the embedded epitaxial layer to The quantity extended out in the p-well of side is to reduce and prevent the influence of the channel of the phosphorus pair extended out, so as to improve The short-channel effect of device and thereby the stability for improving device.
2. NMOS tube as described in claim 1, it is characterised in that: the gate structure is HKMG；In the gate structure two Be formed in the embedded epitaxial layer of side by N+ district's groups at source region and drain region.
3. NMOS tube as described in claim 1, it is characterised in that: the material of the shielded layer is silicon carbide.
4. NMOS tube as claimed in claim 2, it is characterised in that: the gate structure is defined by pseudo- grid structure, the puppet grid Structure removes after the source region and the drain region are formed, and forms the grid in the region of dummy gate structure removal Structure；
Dummy gate structure includes the first gate dielectric layer and polysilicon puppet grid for being formed in the p-well surface.
5. NMOS tube as claimed in claim 4, it is characterised in that: the groove autoregistration is defined in the polysilicon puppet grid Two sides, the source region and the drain region autoregistration are defined in the two sides of the polysilicon puppet grid.
6. NMOS tube as claimed in claim 1 or 5, it is characterised in that: the two sides of the groove are all in " ∑ " shape.
7. NMOS tube as claimed in claim 4, it is characterised in that: be formed with silicon nitride side in the two sides of dummy gate structure Wall.
8. NMOS tube as described in claim 1, it is characterised in that: it goes back on the silicon substrate while being integrated with PMOS tube, institute The length for stating the channel of NMOS tube is 28nm or less.
9. a kind of manufacturing method of NMOS tube, which comprises the steps of:
Step 1: providing the silicon substrate that surface is formed with p-well, pseudo- grid structure, dummy gate structure are formed on the surface of the p-well The p-well surface of institute overlay area is used to form channel；
Step 2: performing etching to form groove to the silicon in the p-well of dummy gate structure two sides；
Step 3: forming embedded epitaxial layer in the groove, including as follows step by step:
Step 31, the inner surface formation silicon seed layer in the groove；
Step 32 forms shielded layer on the silicon seed layer surface；
Step 33, formation silicon phosphorus body layer fill the groove；
Step 34 forms silicon cap layer, and the silicon cap layer is by the silicon seed layer, the silicon phosphorus body layer and the shielded layer Surface covering and the silicon cap layer be projected into the groove top；
The silicon phosphorus body layer has a structure of phosphorus heavy doping, the shielded layer be used to reduce the phosphorus of the embedded epitaxial layer to The quantity extended out in the p-well of side is to reduce and prevent the influence of the channel of the phosphorus pair extended out, so as to improve The short-channel effect of device and thereby the stability for improving device；
It is formed Step 4: carrying out self aligned N+ ion implanting in the embedded epitaxial layer of the two sides of dummy gate structure Source region and drain region；
Step 5: removal dummy gate structure, forms the gate structure of NMOS tube in dummy gate structure removal region.
10. the manufacturing method of NMOS tube as claimed in claim 9, it is characterised in that: the gate structure is HKMG.
11. the manufacturing method of NMOS tube as claimed in claim 10, it is characterised in that: dummy gate structure includes being formed in institute State first gate dielectric layer and polysilicon puppet grid on p-well surface.
12. the manufacturing method of NMOS tube as claimed in claim 9, it is characterised in that: the groove autoregistration is defined in described The two sides of polysilicon puppet grid.
13. the manufacturing method of the NMOS tube as described in claim 9 or 12, it is characterised in that: the two sides of the groove are all in " ∑ " shape.
14. the manufacturing method of NMOS tube as claimed in claim 9, it is characterised in that: the material of the shielded layer is silicon carbide.
15. the manufacturing method of NMOS tube as described in claim 1, it is characterised in that: on the silicon substrate also while integrated There is PMOS tube, the length of the channel of the NMOS tube is 28nm or less.
CN201811267159.4A 2018-10-29 2018-10-29 NMOS tube and its manufacturing method Pending CN109473480A (en)

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