CN110767741B - NMOS (N-channel metal oxide semiconductor) tube and manufacturing method thereof - Google Patents
NMOS (N-channel metal oxide semiconductor) tube and manufacturing method thereof Download PDFInfo
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- CN110767741B CN110767741B CN201910986161.5A CN201910986161A CN110767741B CN 110767741 B CN110767741 B CN 110767741B CN 201910986161 A CN201910986161 A CN 201910986161A CN 110767741 B CN110767741 B CN 110767741B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title description 4
- 229910044991 metal oxide Inorganic materials 0.000 title description 2
- 150000004706 metal oxides Chemical class 0.000 title description 2
- FYNBDWDEBZXMSV-UHFFFAOYSA-N [As].[P].[Si] Chemical compound [As].[P].[Si] FYNBDWDEBZXMSV-UHFFFAOYSA-N 0.000 claims abstract description 78
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 72
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 72
- 239000011574 phosphorus Substances 0.000 claims abstract description 72
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 44
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims abstract description 44
- 238000009792 diffusion process Methods 0.000 claims abstract description 11
- 230000007423 decrease Effects 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 26
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 230000002829 reductive effect Effects 0.000 description 16
- 230000007547 defect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention discloses an NMOS tube, comprising: grooves formed in the P-well on both sides of the gate structure; the grooves are filled with embedded epitaxial layers, and the embedded epitaxial layers comprise at least one gradient silicon phosphorus arsenic epitaxial layer; the bottom gradient silicon phosphorus arsenic epitaxial layer contacts with the bottom surface and the side surface of the groove; the phosphorus doping concentration of the gradient silicon phosphorus arsenic epitaxial layer gradually increases and the arsenic doping concentration gradually decreases in the direction from the bottom surface of the groove upwards and from the side surface inwards, and the gradient change of the phosphorus doping concentration and the arsenic doping concentration in the gradient silicon phosphorus arsenic epitaxial layer forms a structure for reducing the outward diffusion of phosphorus. The invention also discloses a manufacturing method of the NMOS tube. The invention can effectively reduce the phosphorus expansion of the embedded epitaxial layer, improve the tensile stress of the embedded epitaxial layer and improve the performance of the device.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to an NMOS tube; the invention also relates to a manufacturing method of the NMOS tube.
Background
HKMG has a gate dielectric layer of high dielectric constant (HK) and a Metal Gate (MG), and is commonly abbreviated in the art as HKMG. In the MOS transistor adopting the HKMG, the source region and the drain region of the NMOS are often embedded epitaxial layers, the material of the embedded epitaxial layers of the NMOS is usually SiP, and the stress of the channel region of the NMOS is changed through the embedded epitaxial layers and tensile stress which is beneficial to improving the mobility of electrons of the channel region of the NMOS is formed, so that the electron mobility of the channel region of the NMOS can be improved, and the channel resistance is reduced.
Along with the continuous development of semiconductor technology, in order to increase the electron mobility of the NMOS structure, an epitaxial strain technology is often selected to implant into the source region or the drain region, that is, an embedded epitaxial layer is formed in the source region or the drain region, and tensile stress is generated in the channel by the embedded epitaxial layer to increase the electron mobility, so that the channel resistance is reduced. In the prior art, the material of the embedded epitaxial layer of the NMOS is usually silicon phosphide (SiP), and the phosphorus doping concentration in the silicon phosphide epitaxial layer is usually more than 1E21cm -3 The resistivity is about 0.6 ohm-cm.
In the prior art, after forming an embedded epitaxial layer composed of a silicon phosphide epitaxial layer, a plurality of thermal processes are further included, for example, an NMOS transistor is generally manufactured integrally with a PMOS transistor, after the silicon phosphide epitaxial layer of the NMOS transistor is formed, an embedded epitaxial layer composed of a germanium-silicon epitaxial layer of the PMOS transistor is also formed, a thermal annealing treatment is further performed, a high process temperature is adopted in a growth process and a thermal annealing treatment process of the germanium-silicon epitaxial layer, and the high process temperature causes phosphorus in the silicon phosphide epitaxial layer to be outwards diffused, namely, phosphorus is outwards diffused (out diffusion), so that the phosphorus is outwards diffused, for example, various problems are brought: after phosphorus expansion, phosphorus doping in the silicon phosphide epitaxial layer is reduced, so that tensile stress of the silicon phosphide epitaxial layer is reduced, and electron mobility of a channel region is reduced; phosphorus out-diffusion can diffuse part of the phosphorus into the channel region, thereby affecting the performance of the device; finally, the process window of the subsequent process of the device is reduced, and the process difficulty is increased.
Therefore, in the continuous shrinking generation of transistors, how to continuously increase the tensile stress and effectively reduce the external expansion of the doping element and increase the process window of the subsequent process in the embedded epitaxial process of the NMOS transistor has become an important issue nowadays.
Disclosure of Invention
The invention aims to solve the technical problem of providing an NMOS tube which can effectively reduce the phosphorus expansion of an embedded epitaxial layer, improve the tensile stress of the embedded epitaxial layer and improve the performance of a device. Therefore, the invention also provides a manufacturing method of the NMOS tube.
In order to solve the above technical problems, the NMOS transistor provided by the present invention includes:
a channel region composed of a P-well is formed on the surface of the silicon substrate.
A gate structure is formed on the channel region surface, and the channel region surface covered by the gate structure is used for forming a channel.
Grooves are formed in the P-well at two sides of the gate structure.
The grooves are filled with embedded epitaxial layers, and the embedded epitaxial layers comprise at least one gradient silicon phosphorus arsenic epitaxial layer; and the bottom layer of the gradient silicon phosphorus arsenic epitaxial layer is contacted with the bottom surface and the side surface of the groove.
And the phosphorus doping concentration of the gradient silicon phosphorus arsenic epitaxial layer gradually increases and the arsenic doping concentration gradually decreases in the directions from the bottom surface of the groove to the top and from the side to the inside, and the gradient change of the phosphorus doping concentration and the arsenic doping concentration in the gradient silicon phosphorus arsenic epitaxial layer forms a structure for reducing the outward diffusion of phosphorus.
Further improving that the total doping concentration of phosphorus and arsenic in the gradient silicon phosphorus arsenic epitaxial layer is more than 1E21cm after the embedded epitaxial layer is subjected to thermal annealing treatment -3 。
A further improvement is that the resistivity of the gradient silicon phosphorus arsenic epitaxial layer is the same at each depth.
A fin body is formed on the silicon substrate, the P well is formed in the fin body, and the grid structure covers the side face of the fin body or covers the side face and the top surface of the fin body; the grooves are formed in the fin bodies on two sides of the gate structure.
A further improvement is that the grid structure is HKMG; and forming a source region and a drain region which are formed by the N+ regions in the embedded epitaxial layer at two sides of the grid structure.
A further improvement is that the gate structure is defined by a dummy gate structure that is removed after the source and drain regions are formed and the gate structure is formed in the region where the dummy gate structure is removed.
The dummy gate structure comprises a first gate dielectric layer and a polysilicon dummy gate formed on the surface of the channel region.
The groove is self-aligned on two sides of the polycrystalline silicon pseudo gate, and the source region and the drain region are self-aligned on two sides of the polycrystalline silicon pseudo gate.
Further improvements are that the profile of the grooves comprises a U-shape and a sigma-shape.
In order to solve the technical problems, the manufacturing method of the NMOS transistor provided by the invention comprises the following steps:
providing a silicon substrate with a P well formed on the surface, wherein a channel region consists of the P well in a selected region, forming a pseudo gate structure on the surface of the channel region, and forming a channel on the surface of the channel region in a region covered by the pseudo gate structure.
And step two, etching silicon in the P well at two sides of the pseudo gate structure to form grooves.
Filling an embedded epitaxial layer in the groove, wherein the embedded epitaxial layer comprises at least one gradient silicon phosphorus arsenic epitaxial layer; and the bottom layer of the gradient silicon phosphorus arsenic epitaxial layer is contacted with the bottom surface and the side surface of the groove.
In the growth process of the gradient silicon phosphorus arsenic epitaxial layer, the flow of the phosphorus doping source gas is gradually changed from low to high, and the flow of the arsenic doping source gas is gradually changed from high to low, so that the phosphorus doping concentration of the gradient silicon phosphorus arsenic epitaxial layer gradually increases and the arsenic doping concentration gradually decreases from the bottom surface of the groove to the inner side, and the gradient change of the phosphorus and arsenic doping concentration in the gradient silicon phosphorus arsenic epitaxial layer forms a structure for reducing the outward diffusion of phosphorus.
And fourthly, performing self-aligned N+ ion implantation in the embedded epitaxial layers at two sides of the pseudo gate structure to form a source region and a drain region.
And fifthly, removing the pseudo gate structure, and forming a gate structure of the NMOS tube in the pseudo gate structure removing area.
Further improving that the total doping concentration of phosphorus and arsenic in the gradient silicon phosphorus arsenic epitaxial layer is more than 1E21cm after the embedded epitaxial layer is subjected to thermal annealing treatment -3 。
A further improvement is that the resistivity of the gradient silicon phosphorus arsenic epitaxial layer is the same at each depth.
A further improvement is that the grid structure is HKMG; the dummy gate structure comprises a first gate dielectric layer and a polysilicon dummy gate formed on the surface of the channel region.
Further improvements are that the profile of the grooves comprises a U-shape and a sigma-shape.
In a further improvement, the first step further includes a step of forming a fin body on the silicon substrate, wherein the P-well is formed in the fin body, and the dummy gate structure covers the side surface of the fin body or the gate structure covers the side surface and the top surface of the fin body; the grooves are formed in the fin bodies on two sides of the pseudo gate structure.
A further improvement is that the phosphorus doping source gas is PH 3 The arsenic doping source gas is AsH 3 。
The embedded epitaxial layer of the NMOS tube is specially arranged, the embedded epitaxial layer comprises at least one gradient silicon phosphorus arsenic epitaxial layer, and the bottom gradient silicon phosphorus arsenic epitaxial layer contacts with the bottom surface and the side surface of the groove, namely, the embedded epitaxial layer can be formed by one gradient silicon phosphorus arsenic epitaxial layer, can also be formed by laminating a plurality of gradient silicon phosphorus arsenic epitaxial layers or is formed by laminating one gradient silicon phosphorus arsenic epitaxial layer with other epitaxial layers such as silicon phosphorus epitaxial layers, but the bottom gradient silicon phosphorus arsenic epitaxial layer contacts with the bottom surface and the side surface of the groove; in the gradient doping structure of phosphorus, the closer to the outer side, the lower the phosphorus doping concentration of the gradient silicon phosphorus arsenic epitaxial layer is, the lower the phosphorus doping concentration of the outer side of the gradient silicon phosphorus arsenic epitaxial layer can effectively reduce phosphorus expansion, the tensile stress of the embedded epitaxial layer, namely the tensile stress of silicon on a channel region, is reduced, the adverse effect on the channel region is reduced, so that the channel leakage is reduced, and finally the subsequent process window can be increased.
Meanwhile, the invention is also provided with the gradient doping structure of arsenic, and the gradient doping of arsenic and phosphorus can form a complementary effect, so that the resistivity of each depth of the embedded epitaxial layer is kept unchanged, and a smooth ultra-low resistance epitaxial effect can be provided.
Meanwhile, the gradient doping structure of arsenic and the gradient doping structure of phosphorus can gradually increase the tensile stress of the gradient silicon phosphorus arsenic epitaxial layer from top to bottom, and can reduce defects such as stacking fault (stacking fault) defects.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a device block diagram of an NMOS tube according to an embodiment of the present invention;
FIG. 2 is a graph showing the flow rate of phosphorus doped source gas and arsenic doped source gas over time in a method for fabricating an NMOS tube according to an embodiment of the present invention;
FIG. 3 is a graph comparing phosphorus and arsenic expansion curves;
fig. 4 is a resistivity curve and a tensile stress curve of a graded silicon phosphorus arsenic epitaxial layer of an NMOS tube according to an embodiment of the present invention.
Detailed Description
As shown in fig. 1, the NMOS transistor according to the embodiment of the present invention is a device structure diagram; the NMOS tube of the embodiment of the invention comprises:
a channel region 3 composed of P-wells 2 is formed on the surface of the silicon substrate 1, and in fig. 1, only the P-wells 2 located at the bottom of the gate structure 4 are used as the channel region 3.
A gate structure 4 is formed on the surface of the channel region 3, and the surface of the channel region 3 covered by the gate structure 4 is used to form a channel.
A recess 5 is formed in the P-well 2 on both sides of the gate structure 4.
The grooves 5 are filled with embedded epitaxial layers 6, and the embedded epitaxial layers 6 comprise at least one gradient silicon phosphorus arsenic epitaxial layer; the bottom-most gradient silicon phosphorus arsenic epitaxial layer is contacted with the bottom surface and the side surface of the groove 5. In the embodiment of the present invention, the embedded epitaxial layer 6 is directly composed of a gradient silicon phosphorus arsenic epitaxial layer. In other embodiments can also be: forming the embedded epitaxial layer 6 by stacking a plurality of gradient silicon phosphorus arsenic epitaxial layers; alternatively, the embedded epitaxial layer 6 may be formed by stacking one graded silicon phosphorus arsenic epitaxial layer on top of another epitaxial layer such as a silicon phosphide epitaxial layer, but the bottom-most graded silicon phosphorus arsenic epitaxial layer is in contact with the bottom surface and sides of the recess.
The phosphorus doping concentration of the gradient silicon phosphorus arsenic epitaxial layer gradually increases and the arsenic doping concentration gradually decreases from the bottom surface of the groove 5 upwards and from the side inwards, and the gradient change of the phosphorus and arsenic doping concentration in the gradient silicon phosphorus arsenic epitaxial layer forms a structure for reducing the outward diffusion of phosphorus.
The embedded epitaxial layer 6 is subjected to thermal annealing treatment, and the total doping concentration of phosphorus and arsenic in the gradient silicon phosphorus arsenic epitaxial layer is more than 1E21cm -3 。
The resistivity of the gradient silicon phosphorus arsenic epitaxial layer at each depth is the same.
A fin body is formed on the silicon substrate 1, the P well 2 is formed in the fin body, and the grid structure 4 covers the side surface of the fin body or the grid structure 4 covers the side surface and the top surface of the fin body; the grooves 5 are formed in the fin body at both sides of the gate structure 4.
The grid structure 4 is HKMG; source and drain regions composed of n+ regions are formed in the embedded epitaxial layer 6 on both sides of the gate structure 4.
The gate structure 4 is defined by a dummy gate structure that is removed after the formation of the source region and the drain region, and the gate structure 4 is formed in a region where the dummy gate structure is removed.
The dummy gate structure comprises a first gate dielectric layer and a polysilicon dummy gate formed on the surface of the channel region 3.
The grooves 5 are defined on two sides of the polycrystalline silicon dummy gate in a self-aligned mode, and the source region and the drain region are defined on two sides of the polycrystalline silicon dummy gate in a self-aligned mode.
Both side surfaces of the groove 5 are in a sigma shape. In other embodiments, the side of the cross-sectional structure of the groove 5 can be of other shapes.
In the embodiment of the invention, when the gradient change of the phosphorus doping concentration and the gradient change of the arsenic doping concentration of the gradient silicon phosphorus arsenic epitaxial layer are realized by adjusting the flow rates of the phosphorus doping source gas and the arsenic doping source gas in the epitaxial growth process, as shown in fig. 2, the flow rates of the phosphorus doping source gas and the arsenic doping source gas in the corresponding manufacturing method of the NMOS transistor in the embodiment of the invention are curves with time; curve 101 corresponds to phosphorus dopant source gas at PH 3 The flow rate profile at time, curve 102 corresponds to arsenic dopingThe source gas is AsH 3 The flow rate change curve can be seen that the curve 101 is a gradually increasing curve, so that the phosphorus doping concentration of the gradient silicon phosphorus arsenic epitaxial layer can be gradually increased; curve 102 is a decreasing curve, so that the arsenic doping concentration of the graded silicon-phosphorus-arsenic epitaxial layer can be gradually decreased.
As shown in fig. 3, a comparative graph of phosphorus and arsenic expansion curves; curve 103 is a phosphorus expansion curve, i.e., a doping concentration profile of phosphorus after being subjected to a thermal process, and curve 104 is an arsenic expansion curve. It is assumed here that the phosphorus doping concentration profile and the arsenic doping concentration profile before the thermal process are identical; after heat treatment, it can be seen that the diffusion depth of curve 103 is greater than the diffusion depth of curve 104 at the bottom edge location where the depth of the epitaxial layer is greater. Therefore, in the embodiment of the invention, the phosphorus doping concentration of the gradient silicon phosphorus arsenic epitaxial layer is gradually increased from low to high, so that the phosphorus doping at the bottom edge of the gradient silicon phosphorus arsenic epitaxial layer can be reduced, the phosphorus expansion can be reduced, and the impurity expansion of the whole gradient silicon phosphorus arsenic epitaxial layer can be reduced.
As shown in FIG. 4, the resistivity curve and the tensile stress curve of the gradient silicon phosphorus arsenic epitaxial layer of the NMOS tube in the embodiment of the invention are shown; the curve 105 is a resistivity curve of the graded silicon phosphorus arsenic epitaxial layer, and it can be seen that the resistivity of the graded silicon phosphorus arsenic epitaxial layer at each depth is substantially unchanged, and is a very smooth structure, because the doping concentration gradients of phosphorus and arsenic in the embodiments of the present invention are changed in reverse, so that the total N-type doping remains unchanged, and the resistivity is substantially unchanged. The curve 106 is a tensile stress curve of the gradient silicon phosphorus arsenic epitaxial layer, and it can be seen that the tensile stress of the gradient silicon phosphorus arsenic epitaxial layer in the embodiment of the invention is gradually increased, so that compared with the prior art that the tensile stress of the embedded epitaxial layer is reduced by phosphorus expansion, the embodiment of the invention realizes the increase of the tensile stress of the embedded epitaxial layer 6.
The embedded epitaxial layer 6 of the NMOS tube is specially arranged, the embedded epitaxial layer 6 comprises at least one gradient type silicon phosphorus arsenic epitaxial layer, and the bottommost gradient type silicon phosphorus arsenic epitaxial layer is contacted with the bottom surface and the side surface of the groove 5, namely, the embedded epitaxial layer 6 can be formed by stacking one gradient type silicon phosphorus arsenic epitaxial layer or stacking other epitaxial layers such as silicon phosphorus epitaxial layers by stacking one gradient type silicon phosphorus arsenic epitaxial layer, but the bottommost gradient type silicon phosphorus arsenic epitaxial layer is contacted with the bottom surface and the side surface of the groove 5, in the embodiment of the invention, the doping gradient in the gradient type silicon phosphorus arsenic epitaxial layer is arranged in such a way that the phosphorus doping concentration of the gradient type silicon phosphorus arsenic epitaxial layer gradually increases and the arsenic doping concentration gradually decreases from the bottom surface of the groove 5 to the inner direction from the side surface; in the gradient doping structure of phosphorus, the closer to the outer side, the lower the phosphorus doping concentration of the gradient silicon phosphorus arsenic epitaxial layer is, the lower the phosphorus doping concentration of the outer side of the gradient silicon phosphorus arsenic epitaxial layer can effectively reduce phosphorus expansion, the tensile stress of the embedded epitaxial layer 6, namely the tensile stress of silicon on the channel region 3, is reduced, the adverse effect on the channel region 3 is reduced, the channel leakage is reduced, and finally the subsequent process window can be increased.
Meanwhile, the embodiment of the invention is also provided with the arsenic gradient doping structure, so that the gradient doping of arsenic and phosphorus can form a complementary effect, the resistivity of each depth of the embedded epitaxial layer 6 is kept unchanged, and a smooth ultra-low resistance epitaxial effect can be provided.
Meanwhile, the gradient doping structure of arsenic and the gradient doping structure of phosphorus in the embodiment of the invention can gradually increase the tensile stress of the gradient silicon phosphorus arsenic epitaxial layer from top to bottom, and can reduce defects such as stacking fault defects.
The manufacturing method of the NMOS tube comprises the following steps:
step one, providing a silicon substrate 1 with a P well 2 formed on the surface, wherein a channel region 3 is composed of the P well 2 in a selected area, forming a pseudo gate structure on the surface of the channel region 3, and forming a channel on the surface of the channel region 3 in an area covered by the pseudo gate structure.
The dummy gate structure comprises a first gate dielectric layer and a polysilicon dummy gate formed on the surface of the channel region 3.
The first step further includes a step of forming a fin body on the silicon substrate 1, wherein the P-well 2 is formed in the fin body, and the dummy gate structure covers the side surface of the fin body or the gate structure 4 covers the side surface and the top surface of the fin body; subsequent grooves 5 are formed in the fin body at both sides of the dummy gate structure.
And step two, etching the silicon in the P well 2 at the two sides of the pseudo gate structure to form a groove 5.
The shape of the groove 5 is sigma-type. In other embodiments can also be: the grooves may have a U-shape or any other suitable shape.
Filling an embedded epitaxial layer 6 in the groove 5, wherein the embedded epitaxial layer 6 comprises at least one gradient silicon phosphorus arsenic epitaxial layer; the bottom-most gradient silicon phosphorus arsenic epitaxial layer is contacted with the bottom surface and the side surface of the groove 5.
In the growth process of the gradient silicon phosphorus arsenic epitaxial layer, the flow of the phosphorus doping source gas is gradually changed from low to high, and the flow of the arsenic doping source gas is gradually changed from high to low, so that the phosphorus doping concentration of the gradient silicon phosphorus arsenic epitaxial layer gradually increases and the arsenic doping concentration gradually decreases from the bottom surface of the groove 5 to the inner side, and the gradient change of the phosphorus and arsenic doping concentration in the gradient silicon phosphorus arsenic epitaxial layer forms a structure for reducing the outward diffusion of phosphorus.
The phosphorus doping source gas is PH 3 The arsenic doping source gas is AsH 3 。
The embedded epitaxial layer 6 is subjected to thermal annealing treatment in the subsequent process, and the total doping concentration of phosphorus and arsenic in the gradient silicon phosphorus arsenic epitaxial layer is more than 1E21cm -3 。
The resistivity of the gradient silicon phosphorus arsenic epitaxial layer at each depth is the same.
And fourthly, performing self-aligned N+ ion implantation in the embedded epitaxial layer 6 at two sides of the pseudo gate structure to form a source region and a drain region.
And fifthly, removing the pseudo gate structure, and forming a gate structure 4 of the NMOS tube in the pseudo gate structure removing area. The gate structure 4 is HKMG.
In the method of the embodiment of the present invention, step one includes a step of forming a fin body on the silicon substrate 1, where the P-well 2 is formed in the fin body, and the dummy gate structure covers a side surface of the fin body or the gate structure 4 covers a side surface and a top surface of the fin body; the grooves 5 are formed in the fin bodies on two sides of the dummy gate structure.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (15)
1. An NMOS transistor, comprising:
forming a channel region composed of a P well on the surface of a silicon substrate;
forming a gate structure on the surface of the channel region, wherein the surface of the channel region covered by the gate structure is used for forming a channel;
forming grooves in the P well at two sides of the grid structure;
the grooves are filled with embedded epitaxial layers, and the embedded epitaxial layers comprise at least one gradient silicon phosphorus arsenic epitaxial layer; the bottom-most layer of the gradient silicon phosphorus arsenic epitaxial layer is contacted with the bottom surface and the side surface of the groove;
and the phosphorus doping concentration of the gradient silicon phosphorus arsenic epitaxial layer gradually increases and the arsenic doping concentration gradually decreases in the directions from the bottom surface of the groove to the top and from the side to the inside, and the gradient change of the phosphorus doping concentration and the arsenic doping concentration in the gradient silicon phosphorus arsenic epitaxial layer forms a structure for reducing the outward diffusion of phosphorus.
2. The NMOS tube of claim 1, wherein: the embedded epitaxial layer is subjected to thermal annealing treatment, and the total doping concentration of phosphorus and arsenic in the gradient silicon phosphorus arsenic epitaxial layer is more than 1E21cm -3 。
3. The NMOS tube of claim 2, wherein: the resistivity of the gradient silicon phosphorus arsenic epitaxial layer at each depth is the same.
4. The NMOS tube of claim 1, wherein: forming a fin body on the silicon substrate, wherein the P well is formed in the fin body, and the grid structure covers the side face of the fin body or covers the side face and the top surface of the fin body; the grooves are formed in the fin bodies on two sides of the gate structure.
5. The NMOS tube of claim 1, wherein: the grid structure is HKMG; and forming a source region and a drain region which are formed by the N+ regions in the embedded epitaxial layer at two sides of the grid structure.
6. The NMOS tube of claim 5, wherein: the gate structure is defined by a dummy gate structure, the dummy gate structure is removed after the source region and the drain region are formed, and the gate structure is formed in a region where the dummy gate structure is removed;
the dummy gate structure comprises a first gate dielectric layer and a polysilicon dummy gate formed on the surface of the channel region.
7. The NMOS tube of claim 6, wherein: the grooves are defined on two sides of the polycrystalline silicon pseudo gate in a self-aligned mode, and the source region and the drain region are defined on two sides of the polycrystalline silicon pseudo gate in a self-aligned mode.
8. The NMOS tube of claim 7, wherein: the shape of the groove comprises a U shape and a sigma shape.
9. The manufacturing method of the NMOS tube is characterized by comprising the following steps:
providing a silicon substrate with a P well formed on the surface, wherein a channel region consists of the P well in a selected region, forming a pseudo gate structure on the surface of the channel region, and forming a channel on the surface of the channel region in a region covered by the pseudo gate structure;
etching silicon in the P well at two sides of the pseudo gate structure to form grooves;
filling an embedded epitaxial layer in the groove, wherein the embedded epitaxial layer comprises at least one gradient silicon phosphorus arsenic epitaxial layer; the bottom-most layer of the gradient silicon phosphorus arsenic epitaxial layer is contacted with the bottom surface and the side surface of the groove;
in the growth process of the gradient silicon phosphorus arsenic epitaxial layer, the flow rate of phosphorus doping source gas is gradually changed from low to high, and the flow rate of arsenic doping source gas is gradually changed from high to low, so that the phosphorus doping concentration of the gradient silicon phosphorus arsenic epitaxial layer gradually increases and the arsenic doping concentration gradually decreases in the direction from the bottom surface of the groove to the side surface, and the gradient change of the phosphorus doping concentration and the arsenic doping concentration in the gradient silicon phosphorus arsenic epitaxial layer forms a structure for reducing the outward diffusion of phosphorus;
step four, performing self-aligned N+ ion implantation in the embedded epitaxial layers at two sides of the pseudo gate structure to form a source region and a drain region;
and fifthly, removing the pseudo gate structure, and forming a gate structure of the NMOS tube in the pseudo gate structure removing area.
10. The method for manufacturing an NMOS transistor according to claim 9, wherein: the embedded epitaxial layer is subjected to thermal annealing treatment, and the total doping concentration of phosphorus and arsenic in the gradient silicon phosphorus arsenic epitaxial layer is more than 1E21cm -3 。
11. The method for manufacturing an NMOS transistor according to claim 10, wherein: the resistivity of the gradient silicon phosphorus arsenic epitaxial layer at each depth is the same.
12. The method for manufacturing an NMOS transistor according to claim 9, wherein: the grid structure is HKMG; the dummy gate structure comprises a first gate dielectric layer and a polysilicon dummy gate formed on the surface of the channel region.
13. The method for manufacturing an NMOS transistor according to claim 9, wherein: the shape of the groove comprises a U shape and a sigma shape.
14. The method for manufacturing an NMOS transistor according to claim 9, wherein: the first step further comprises the step of forming a fin body on the silicon substrate, wherein the P well is formed in the fin body, and the dummy gate structure covers the side surface of the fin body or the gate structure covers the side surface and the top surface of the fin body; the grooves are formed in the fin bodies on two sides of the pseudo gate structure.
15. The method for manufacturing an NMOS transistor according to claim 9, wherein: the phosphorus doping source gas is PH 3 The arsenic doping source gas is AsH 3 。
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