CN108573874A - The manufacturing method of NMOS with HKMG - Google Patents
The manufacturing method of NMOS with HKMG Download PDFInfo
- Publication number
- CN108573874A CN108573874A CN201810330459.6A CN201810330459A CN108573874A CN 108573874 A CN108573874 A CN 108573874A CN 201810330459 A CN201810330459 A CN 201810330459A CN 108573874 A CN108573874 A CN 108573874A
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- Prior art keywords
- nmos
- layer
- hkmg
- manufacturing
- gate structure
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- 230000008569 process Effects 0.000 claims abstract description 18
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 16
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 11
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 8
- 239000002019 doping agent Substances 0.000 claims abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 15
- 230000006872 improvement Effects 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 3
- 238000007689 inspection Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
Abstract
The invention discloses a kind of manufacturing methods of the NMOS with HKMG, including step：Step 1: providing the silicon substrate for the gate structure for being formed with NMOS and forming side wall in the side of gate structure；Step 2: performing etching to form groove to the silicon of the both sides of the gate structure of NMOS；Step 3: forming the buffer layer of embedded epitaxial layer in a groove；Step 4: carrying out the first time ion implanting with angle that implanted dopant is carbon and nitrogen；Step 5: filling the body layer of embedded epitaxial layer in a groove；Step 6: forming the cap layer of embedded epitaxial layer on the surface of body layer；Step 7: carry out second of ion implanting forms source region and drain region in the both sides of the gate structure of NMOS.The present invention can improve the short-channel effect of NMOS in conjunction with the formation process of embedded epitaxial layer, and simple for process, process costs are low, the present invention does not interfere with the characteristic of PMOS.
Description
Technical field
The present invention relates to a kind of manufacturing method of semiconductor integrated circuit, more particularly to a kind of system of the NMOS with HKMG
Make method.
Background technology
HKMG has the gate dielectric layer and metal gate (MG) of high-k (HK), therefore is commonly abbreviated as in this field
HKMG.Using in the MOS transistor of HKMG, the source region of NMOS and drain region often use embedded epitaxial layer, and NMOS's is embedded
The material of epitaxial layer is usually SiP, changes the stress of the channel region of NMOS by embedded epitaxial layer and is formed with conducive to improving
The tensile stress of the mobility of the electronics of the channel region of NMOS, so as to improve NMOS channel region electron mobility, reduce ditch
Road resistance.
With the development of technology, the critical size (CD) of device is smaller and smaller, and the technology node of such as existing HKMG techniques is
CD has reached 28nm hereinafter, this makes the short-channel effect of device increasingly severe, makes the performance of device by serious influence,
In existing method, the threshold voltage of generally use trap injects, and the excellent of short-channel effect is realized in lightly doped drain (LDD) injection etc.
Change.
The manufacturing method of the existing NMOS with HKMG includes the following steps：
Step 1: providing the silicon substrate for the gate structure for being formed with NMOS and forming side in the side of the gate structure
Wall, generally silicon nitride spacer；The channel region of the surface composition NMOS for the silicon substrate that the gate structure is covered.The step
The rapid gate structure is usually that pseudo- grid structure includes polysilicon puppet grid, is needed after continuous source and drain ion implanting in the completed
With the gate structure i.e. HKMG replacements for including metal gate.
Step 2: performing etching to form groove to the silicon of the both sides of the gate structure of the NMOS；The side of groove is usual
In " ∑ " shape.
Step 3: filling SiP epitaxial layers in the groove；SiP material layers so are just embedded into silicon, therefore are known as being embedded in
SiP layers of formula namely the embedded epitaxial layer that material is SiP.
It injects N-type impurity Step 4: carrying out source and drain ion implanting in the both sides of the gate structure of the NMOS and forms institute
State source region and the drain region of NMOS.
It, can if can carry out while improve the short-channel effect of NMOS in conjunction with the formation process of the embedded epitaxial layer of NMOS
Preferable improvement is brought to the performance of NMOS, and at low cost.
Invention content
Technical problem to be solved by the invention is to provide a kind of manufacturing methods of the NMOS with HKMG, can be in conjunction with insertion
The formation process of formula epitaxial layer improves the short-channel effect of NMOS.
In order to solve the above technical problems, the manufacturing method of the NMOS provided by the invention with HKMG includes the following steps：
Step 1: providing the silicon substrate for the gate structure for being formed with NMOS and forming side in the side of the gate structure
Wall；The channel region of the surface composition NMOS for the silicon substrate that the gate structure is covered.
Step 2: performing etching to form groove to the silicon of the both sides of the gate structure of the NMOS.
Step 3: forming the buffer layer of embedded epitaxial layer in the groove.
Step 4: carry out first time ion implanting with angle, the implanted dopant of the first time ion implanting be carbon and
Nitrogen.
Step 5: filling the body layer of the embedded epitaxial layer in the groove for being formed with the buffer layer.
Step 6: forming the cap layer of the embedded epitaxial layer on the surface of the body layer.
It injects N-type impurity Step 7: carrying out second of ion implanting in the both sides of the gate structure of the NMOS and is formed
The source region of the NMOS and drain region.
A further improvement is that the gate structure in step 1 includes the first gate dielectric layer and polysilicon puppet grid, institute
State gate structure step 7 formed the NMOS source region and drain region after remove, later again the gate structure removal
Region forms HKMG.
A further improvement is that side wall described in step 1 is silicon nitride spacer.
A further improvement is that the two sides for etching the groove of formation in step 2 are all in " ∑ " shape.
A further improvement is that CD is surveyed after being developed before the recess etch after silicon nitride spacer formation
Amount.
A further improvement is that CD is measured after being performed etching after the recess etch.
A further improvement is that the material of the buffer layer of the embedded epitaxial layer, body layer and cap layer is all SiP.
A further improvement is that buffer layer, body layer and the cap layer of the embedded epitaxial layer all use selectivity outer
Prolong technique to be formed.
A further improvement is that the P concentration of the buffer layer is less than the P concentration of the body layer, the P of the cap layer is dense
P concentration of the degree less than the body layer.
A further improvement is that also while PMOS is integrated on the silicon substrate of step 1, in step 2 to step 7
Described in PMOS area protected.
A further improvement is that the length of the channel region of the NMOS is 28nm or less.
A further improvement is that cap layer described in step 6 protrudes from the top of the groove and is higher than the silicon substrate
Surface location.
The present invention is by the formation process of embedded epitaxial layer, mainly in the embedded of groove and groove surfaces
After the buffer layer of epitaxial layer is formed, the carbon and nitrogen of a sub-band angle are increased before the body layer filling of embedded epitaxial layer
Ion implanting, that is, first time ion implanting, carbon and nitrogen can be injected into from groove side in channel region by first time ion implanting,
The short-channel effect of NMOS can be improved so as to improve the short-channel effect formed in channel region also, so the present invention can tie
The formation process of embedded epitaxial layer is closed to improve the short-channel effect of NMOS.
The promotion of device performance can be brought by improving the short-channel effect of NMOS, and will improve the work of the short-channel effect of NMOS
Skill is attached to the reduction that cost can be then brought in the formation process of embedded epitaxial layer, and simple for process.
In general, NMOS and PMOS are integrated on same silicon substrate, and when carrying out the formation process of embedded epitaxial layer, PMOS
Region can all be protected, therefore the present invention does not interfere with the characteristic of PMOS.
Description of the drawings
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments：
Fig. 1 is the flow chart of the manufacturing method of NMOS of the embodiment of the present invention with HKMG；
Fig. 2 is the device junction composition in present invention method.
Specific implementation mode
As shown in Figure 1, being the flow chart of the manufacturing method of NMOS of the embodiment of the present invention with HKMG；As shown in Fig. 2, being
The manufacturing method of device junction composition in present invention method, NMOS of the embodiment of the present invention with HKMG includes following step
Suddenly：
Step 1: providing the silicon substrate 1 for the gate structure 2 for being formed with NMOS and being formed in the side of the gate structure 2
Side wall 3；The channel region of the surface composition NMOS for the silicon substrate 1 that the gate structure 2 is covered.
In the embodiment of the present invention, the gate structure 2 includes the first gate dielectric layer and polysilicon puppet grid, the gate structure
2 step 7 formed the NMOS source region and drain region after remove, later again the gate structure 2 remove region formed
HKMG。
The side wall 3 is silicon nitride spacer.
It is gone back on the silicon substrate 1 of step 1 while being integrated with PMOS, the PMOS area described in step 2 to step 7
It is protected.In the embodiment of the present invention, the length of the channel region of the NMOS is 28nm or less.Namely the embodiment of the present invention is corresponding
The process node of HKMG is 28nm or less.
Step 2: performing etching to form groove to the silicon of the both sides of the gate structure 2 of the NMOS.
In the embodiment of the present invention, the two sides for etching the groove of formation are all in " ∑ " shape.
CD measures After Develop after being developed before the recess etch after silicon nitride spacer formation
Inspection, ADI)
CD measures (After Etch Inspection, AEI) after being performed etching after the recess etch.
Step 3: forming the buffer layer (Buffer Layer) 41 of embedded epitaxial layer 4 in the groove.
Step 4: carry out first time ion implanting with angle, the implanted dopant of the first time ion implanting be carbon and
Nitrogen.
Step 5: filling the body layer of the embedded epitaxial layer 4 in the groove for being formed with the buffer layer 41
(Bulk Layer)42。
Step 6: forming the cap layer (Cap Layer) of the embedded epitaxial layer 4 on the surface of the body layer 42
43.Namely the embedded epitaxial layer 4 is formed by the superposition of the buffer layer 41, the body layer 42 and the cap layer 43.
The material of the buffer layer 41 of the embedded epitaxial layer 4, body layer 42 and cap layer 43 is all SiP.
Buffer layer 41, body layer 42 and the cap layer 43 of the embedded epitaxial layer 4 all use selective epitaxial process shape
At.
The P concentration of the buffer layer 41 is less than the P concentration of the body layer 42, and the P concentration of the cap layer 43 is less than institute
State the P concentration of body layer 42.
The cap layer 43 protrudes from the top of the groove and the surface location higher than the silicon substrate 1.
It injects N-type impurity Step 7: carrying out second of ion implanting in the both sides of the gate structure 2 of the NMOS and is formed
The source region of the NMOS and drain region.
The embodiment of the present invention is by the formation process of embedded epitaxial layer 4, mainly in groove and groove surfaces
Embedded epitaxial layer 4 buffer layer 41 formed after, increased before the body layer 42 of embedded epitaxial layer 4 is filled primary
The ion implanting of carbon and nitrogen with angle, that is, first time ion implanting, first time ion implanting can note carbon and nitrogen from groove side
Enter into channel region, can improve the short-channel effect of NMOS so as to improve the short-channel effect formed in channel region also,
So the present invention can improve the short-channel effect of NMOS in conjunction with the formation process of embedded epitaxial layer 4.
The promotion of device performance can be brought by improving the short-channel effect of NMOS, and will improve the work of the short-channel effect of NMOS
Skill is attached to the reduction that cost can be then brought in the formation process of embedded epitaxial layer 4, and simple for process.
In general, NMOS and PMOS are integrated on same silicon substrate 1, when carrying out the formation process of embedded epitaxial layer 4,
The region of PMOS can all be protected, therefore the embodiment of the present invention does not interfere with the characteristic of PMOS.
The present invention has been described in detail through specific embodiments, but these not constitute the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (12)
1. a kind of manufacturing method of the NMOS with HKMG, which is characterized in that include the following steps：
Step 1: providing the silicon substrate for the gate structure for being formed with NMOS and forming side wall in the side of the gate structure；Institute
State the channel region of the surface composition NMOS for the silicon substrate that gate structure is covered；
Step 2: performing etching to form groove to the silicon of the both sides of the gate structure of the NMOS；
Step 3: forming the buffer layer of embedded epitaxial layer in the groove；
Step 4: carrying out first time ion implanting with angle, the implanted dopant of the first time ion implanting is carbon and nitrogen；
Step 5: filling the body layer of the embedded epitaxial layer in the groove for being formed with the buffer layer；
Step 6: forming the cap layer of the embedded epitaxial layer on the surface of the body layer；
It is injected described in N-type impurity and formation in the both sides of the gate structure of the NMOS Step 7: carrying out second of ion implanting
The source region of NMOS and drain region.
2. the manufacturing method of the NMOS with HKMG as described in claim 1, it is characterised in that：The grid in step 1
Structure includes the first gate dielectric layer and polysilicon puppet grid, and the gate structure forms source region and the drain region of the NMOS in step 7
It removes later, forms HKMG in the region of gate structure removal again later.
3. the manufacturing method of the NMOS with HKMG as described in claim 1, it is characterised in that：Side wall described in step 1 is
Silicon nitride spacer.
4. the manufacturing method of the NMOS with HKMG as claimed in claim 3, it is characterised in that：Etching is formed in step 2
The two sides of the groove are all in " ∑ " shape.
5. the manufacturing method of the NMOS with HKMG as claimed in claim 4, it is characterised in that：In the silicon nitride spacer shape
It is measured at CD after being developed before the recess etch later.
6. the manufacturing method of the NMOS with HKMG as claimed in claim 4, it is characterised in that：After the recess etch
Rear CD is performed etching to measure.
7. the manufacturing method of the NMOS with HKMG as described in claim 1, it is characterised in that：The embedded epitaxial layer
The material of buffer layer, body layer and cap layer is all SiP.
8. the manufacturing method of the NMOS as claimed in claim 1 or 7 with HKMG, it is characterised in that：The embedded extension
Buffer layer, body layer and the cap layer of layer are all formed using selective epitaxial process.
9. the manufacturing method of the NMOS with HKMG as claimed in claim 7, it is characterised in that：The P concentration of the buffer layer
Less than the P concentration of the body layer, the P concentration of the cap layer is less than the P concentration of the body layer.
10. the manufacturing method of the NMOS with HKMG as described in claim 1, it is characterised in that：The silicon of step 1 serves as a contrast
It is gone back on bottom while being integrated with PMOS, the PMOS area described in step 2 to step 7 is protected.
11. the manufacturing method of the NMOS with HKMG as described in claim 1, it is characterised in that：The channel region of the NMOS
Length be 28nm or less.
12. the manufacturing method of the NMOS as claimed in claim 1 or 7 with HKMG, it is characterised in that：It is covered described in step 6
Cap layers protrude from the top of the groove and the surface location higher than the silicon substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810330459.6A CN108573874B (en) | 2018-04-13 | 2018-04-13 | Manufacturing method of NMOS with HKMG |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810330459.6A CN108573874B (en) | 2018-04-13 | 2018-04-13 | Manufacturing method of NMOS with HKMG |
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| Publication Number | Publication Date |
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| CN108573874A true CN108573874A (en) | 2018-09-25 |
| CN108573874B CN108573874B (en) | 2020-10-02 |
Family
ID=63574831
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109473469A (en) * | 2018-10-29 | 2019-03-15 | 上海华力集成电路制造有限公司 | NMOS tube and its manufacturing method |
| CN110828300A (en) * | 2019-11-25 | 2020-02-21 | 上海华力集成电路制造有限公司 | Epitaxial process |
| CN111599764A (en) * | 2020-05-29 | 2020-08-28 | 上海华力集成电路制造有限公司 | Method for manufacturing embedded epitaxial layer |
| CN113394159A (en) * | 2021-05-14 | 2021-09-14 | 上海华力集成电路制造有限公司 | MOS transistor manufacturing method and MOS transistor |
| CN113394161A (en) * | 2021-05-31 | 2021-09-14 | 上海华力集成电路制造有限公司 | Manufacturing method of embedded SiP epitaxial layer |
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| CN107634092A (en) * | 2017-09-26 | 2018-01-26 | 上海华力微电子有限公司 | A kind of germanium silicon source drain electrode and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109473469A (en) * | 2018-10-29 | 2019-03-15 | 上海华力集成电路制造有限公司 | NMOS tube and its manufacturing method |
| CN110828300A (en) * | 2019-11-25 | 2020-02-21 | 上海华力集成电路制造有限公司 | Epitaxial process |
| CN110828300B (en) * | 2019-11-25 | 2022-03-18 | 上海华力集成电路制造有限公司 | Epitaxial process |
| CN111599764A (en) * | 2020-05-29 | 2020-08-28 | 上海华力集成电路制造有限公司 | Method for manufacturing embedded epitaxial layer |
| CN113394159A (en) * | 2021-05-14 | 2021-09-14 | 上海华力集成电路制造有限公司 | MOS transistor manufacturing method and MOS transistor |
| CN113394161A (en) * | 2021-05-31 | 2021-09-14 | 上海华力集成电路制造有限公司 | Manufacturing method of embedded SiP epitaxial layer |
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