CN113394159A - MOS transistor manufacturing method and MOS transistor - Google Patents
MOS transistor manufacturing method and MOS transistor Download PDFInfo
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- CN113394159A CN113394159A CN202110526789.4A CN202110526789A CN113394159A CN 113394159 A CN113394159 A CN 113394159A CN 202110526789 A CN202110526789 A CN 202110526789A CN 113394159 A CN113394159 A CN 113394159A
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- Prior art keywords
- mos transistor
- gas
- manufacturing
- layer
- buffer layer
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 18
- 239000007789 gas Substances 0.000 claims description 17
- 239000012159 carrier gas Substances 0.000 claims description 16
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 9
- 239000001257 hydrogen Substances 0.000 claims description 9
- 229910052739 hydrogen Inorganic materials 0.000 claims description 9
- 229910052757 nitrogen Inorganic materials 0.000 claims description 9
- 235000012489 doughnuts Nutrition 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 2
- 229910052986 germanium hydride Inorganic materials 0.000 description 2
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 2
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- QYKABQMBXCBINA-UHFFFAOYSA-N 4-(oxan-2-yloxy)benzaldehyde Chemical compound C1=CC(C=O)=CC=C1OC1OCCCC1 QYKABQMBXCBINA-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- QHGSGZLLHBKSAH-UHFFFAOYSA-N hydridosilicon Chemical compound [SiH] QHGSGZLLHBKSAH-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Abstract
The invention discloses a manufacturing method of an MOS transistor, which comprises the following steps: providing a silicon substrate, forming a structural body on the surface of the silicon substrate, and forming side walls on two sides of the structural body; and step two, etching the structural bodies by a dry method to form grooves. Growing a buffer layer in the groove, wherein the buffer layer is tightly attached to the wall of the groove; growing a first main body layer on the buffer layer; and fifthly, growing and forming a second body layer on the first body layer.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit manufacturing, and more particularly, to a method for manufacturing a MOS transistor and a MOS transistor manufactured by the method.
Background
In the manufacturing of a semiconductor device, an embedded epitaxial layer is often adopted in a source region and a drain region of an MOS transistor, the embedded epitaxial layer is usually made of SiP, the stress of a channel region of the MOS transistor is changed through the embedded epitaxial layer, and tensile stress favorable for improving the mobility of electrons in the channel region of the MOS transistor is formed, so that the electron mobility of the channel region of the MOS transistor can be improved, and the channel resistance is reduced.
With the development of technology, the critical dimension of the device is smaller and smaller, and is already less than 28nm, the existing SiP epitaxial growth process may cause poor uniformity of the wafer, especially the thickness difference between the ring (donut) region and the middle or edge region is larger, or is thin or thick, which directly affects the device performance of the ring (donut) region.
Disclosure of Invention
The invention aims to solve the technical problem of how to improve the thickness uniformity of an embedded epitaxial layer, and provides a manufacturing method of an MOS transistor, which comprises the following steps:
providing a silicon substrate, forming a structural body on the surface of the silicon substrate, and forming side walls on two sides of the structural body;
and step two, etching the structural bodies by a dry method to form grooves.
Growing a buffer layer in the groove, wherein the buffer layer is tightly attached to the wall of the groove;
growing a first main body layer on the buffer layer;
and fifthly, growing and forming a second body layer on the first body layer.
Preferably, the structure is any one of a gate electrode, a source electrode, and a drain electrode.
Preferably, the material of the buffer layer, the first body layer and the second body layer is SiP.
Preferably, the first gas is used as the carrier gas in the fourth step, and the second gas is used as the carrier gas in the fifth step.
Preferably, the first gas is nitrogen and the second gas is hydrogen.
Preferably, the first gas is hydrogen and the second gas is nitrogen.
Preferably, the carrier gas has a gas flow rate between 1slm and 50slm, a gas pressure between 1torr and 100torr, and a process temperature range between 500 and 800 degrees celsius.
The invention also provides a MOS transistor which is manufactured by adopting the manufacturing method.
Compared with the prior art, the method can improve the thickness uniformity of the embedded epitaxial layer, thereby improving the overall thickness uniformity of the wafer and improving the performance of devices.
Drawings
FIGS. 1a to 1c are schematic views of device structures in the prior art manufacturing method.
FIG. 2 is a diagram illustrating a wafer thickness in the prior art.
Fig. 3a to 3d are schematic device structures of the manufacturing method according to the embodiment of the invention.
FIG. 4 is a schematic diagram of a wafer thickness under the manufacturing method of the present invention.
Detailed Description
Before describing the embodiment of the present invention in detail, a method for manufacturing a conventional MOS transistor is described, as shown in fig. 1a to 1c, which are device structure diagrams in each step of the conventional method for manufacturing a MOS transistor; the manufacturing method of the existing MOS tube comprises the following steps:
step one, as shown in fig. 1a, providing a silicon substrate 1, forming a gate structure on the surface of the silicon substrate 1, and forming side walls on two sides of the gate structure.
Step two, as shown in fig. 1a, forming a groove by dry etching.
And step three, as shown in fig. 1b, growing and forming a buffer layer 2 in the groove, wherein the buffer layer 2 is tightly attached to the wall of the groove.
Step four, as shown in fig. 1c, a body layer 3 is grown on the buffer layer 2 to a desired thickness.
The thickness uniformity of the epitaxial layer grown by the growth process in the existing manufacturing method is not good. In particular, the thickness difference between the ring-shaped (donut) region and the middle or edge region is large, or thin or thick. This results in poor uniformity of wafer thickness, which directly affects the device performance in the halo (donut) region. The difference in thickness between the wafer ring-shaped region and the other regions can be seen from fig. 2.
In the structural schematic diagram of the MOS transistor device according to the embodiment of the present invention, as shown in fig. 3a to 3d, the MOS transistor may be an NMOS transistor or a PMOS transistor. This embodiment takes a gate region as an example, and the source region or the drain region can also be applied with this method. The specific manufacturing method of the MOS transistor comprises the following steps:
step one, as shown in fig. 3a, providing a silicon substrate 1, forming a gate structure on the surface of the silicon substrate 1, and forming side walls on two sides of the gate structure.
Step two, as shown in fig. 3a, a groove is formed by dry etching.
And step three, as shown in fig. 3b, growing and forming a buffer layer 2 in the groove, wherein the buffer layer 2 is tightly attached to the wall of the groove. The buffer layer is made of SiP.
Step four, as shown in fig. 3c, a first body layer 31 is grown on the buffer layer 2. The material of the first body layer 31 is SiP. Nitrogen is used as a carrier gas, the process temperature ranges from 500 to 800 degrees celsius, and the pressure ranges from 1torr to 100 torr. The carrier gas flow rate is between 1slm to 50 slm.
Step five, as shown in fig. 3d, a second body layer 32 is grown on the first body layer 31. The material of the second body layer 32 is SiP. Hydrogen is used as a carrier gas, the process temperature ranges from 500 to 800 degrees celsius, and the pressure ranges from 1torr to 100 torr. The carrier gas flow rate is between 1slm to 50 slm. The sum of the thicknesses of the second body layer 32 and the first body layer 31 is the total thickness of the body layers required.
It is also possible to use hydrogen as the carrier gas in step four and then nitrogen as the carrier gas in step five.
When nitrogen is used as carrier gas, the thickness of a ring-shaped (donut) area of the wafer is thinner, and the thickness of the middle area and the edge area are thicker; when hydrogen is used as the carrier gas, the thickness of the ring (donut) region of the wafer is thicker, and the thickness of the middle and edge regions is thinner. So that the SiP silicon wafer with uniform thickness is formed through the growth of two steps.
As can be seen from fig. 4, the thickness difference of the wafer-ring-shaped region and other regions of the first and second body layers grown in two steps, and the difference of the overall thickness can be seen.
It should be noted that the carrier gas is not limited to hydrogen and nitrogen, and SiH can also be used as the gas2Cl2(dichlorosilane) SiH4(silicon tetrahydride), GeH4(germanium hydride), pH3(phosphine), HCL (hydrogen chloride), etc., at a flow rate of 1sccm to 1000sccm in addition to hydrogen and nitrogen. Forming the difference of the thickness of the deposition layer by using different carrier gas growth, and growing twiceAnd forming the silicon wafer with uniform thickness.
The invention also provides a MOS transistor which is manufactured by adopting the manufacturing method.
The present invention has been described in detail with reference to the specific embodiments and examples, but these are not intended to limit the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (8)
1. A MOS transistor manufacturing method is characterized by comprising the following steps:
providing a silicon substrate, forming a structural body on the surface of the silicon substrate, and forming side walls on two sides of the structural body;
and step two, etching the structural bodies by a dry method to form grooves.
Growing a buffer layer in the groove, wherein the buffer layer is tightly attached to the wall of the groove;
growing a first main body layer on the buffer layer;
and fifthly, growing and forming a second body layer on the first body layer.
2. The MOS transistor fabrication method of claim 1, wherein:
the structure body is any one of a gate electrode, a source electrode and a drain electrode.
3. The MOS transistor fabrication method of claim 1, wherein:
the buffer layer, the first main body layer and the second main body layer are made of SiP.
4. The MOS transistor fabrication method of claim 1, wherein:
the fourth step uses the first gas as the carrier gas, and the fifth step uses the second gas as the carrier gas.
5. The method of manufacturing a MOS transistor according to claim 4, wherein:
the first gas is nitrogen and the second gas is hydrogen.
6. The method of manufacturing a MOS transistor according to claim 4, wherein:
the first gas is hydrogen and the second gas is nitrogen.
7. The method of manufacturing a MOS transistor according to claim 4, wherein:
the carrier gas has a gas flow rate of between 1slm and 50slm, a gas pressure of between 1torr and 100torr, and a process temperature range of between 500 and 800 degrees celsius.
8. A MOS transistor, characterized by:
manufactured by the manufacturing method of any of the preceding claims.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110526789.4A CN113394159A (en) | 2021-05-14 | 2021-05-14 | MOS transistor manufacturing method and MOS transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110526789.4A CN113394159A (en) | 2021-05-14 | 2021-05-14 | MOS transistor manufacturing method and MOS transistor |
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| CN113394159A true CN113394159A (en) | 2021-09-14 |
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| CN202110526789.4A Pending CN113394159A (en) | 2021-05-14 | 2021-05-14 | MOS transistor manufacturing method and MOS transistor |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120126296A1 (en) * | 2010-11-18 | 2012-05-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits and fabrication methods thereof |
| CN108573874A (en) * | 2018-04-13 | 2018-09-25 | 上海华力集成电路制造有限公司 | The manufacturing method of NMOS with HKMG |
| CN111599764A (en) * | 2020-05-29 | 2020-08-28 | 上海华力集成电路制造有限公司 | Method for manufacturing embedded epitaxial layer |
| US20210043442A1 (en) * | 2019-08-09 | 2021-02-11 | Zing Semiconductor Corporation | Method for improving flatness of semiconductor thin film |
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2021
- 2021-05-14 CN CN202110526789.4A patent/CN113394159A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120126296A1 (en) * | 2010-11-18 | 2012-05-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits and fabrication methods thereof |
| CN108573874A (en) * | 2018-04-13 | 2018-09-25 | 上海华力集成电路制造有限公司 | The manufacturing method of NMOS with HKMG |
| US20210043442A1 (en) * | 2019-08-09 | 2021-02-11 | Zing Semiconductor Corporation | Method for improving flatness of semiconductor thin film |
| CN111599764A (en) * | 2020-05-29 | 2020-08-28 | 上海华力集成电路制造有限公司 | Method for manufacturing embedded epitaxial layer |
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Application publication date: 20210914 |
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