CN100561692C - The doping method in MOS transistor tagma - Google Patents
The doping method in MOS transistor tagma Download PDFInfo
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- CN100561692C CN100561692C CNB2007101771054A CN200710177105A CN100561692C CN 100561692 C CN100561692 C CN 100561692C CN B2007101771054 A CNB2007101771054 A CN B2007101771054A CN 200710177105 A CN200710177105 A CN 200710177105A CN 100561692 C CN100561692 C CN 100561692C
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- sacrificial dielectric
- tagma
- gate electrode
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Abstract
The invention provides the doping method in a kind of MOS transistor tagma, belong to semiconductor integrated circuit and manufacturing technology field thereof.This method is to form slit in the gate electrode both sides, carries out the ion implantation doping in tagma by this slit.The present invention is because tagma heavy doping is slit by the gate electrode both sides carries out, therefore, realized that heavily doped region is strip in the channel region both sides, this strip heavily doped region can effectively shield an electric leakage influence to raceway groove and source end, makes device have good short-channel properties.And this strip heavily doped region is in the raceway groove both sides, and impurity concentration can be very low in the channel region, makes device have the subthreshold characteristic that high carrier mobility is become reconciled.The present invention can effectively avoid or alleviate the problem that the tagma doping method of present routine is brought.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacturing technology field thereof, relate in particular to the doping method in a kind of MOS transistor tagma.
Background technology
The integrated circuit especially main devices in the very lagre scale integrated circuit (VLSIC) is metal-oxide semiconductor fieldeffect transistor (metal oxide semiconductor field effect transistor is called for short MOSFET).Integrated circuit is since invention, and its progress on performance and function is advanced by leaps and bounds.Obtaining that this is progressive then is to realize by the size and the increase chip area of continuous reduction of device simply.Constantly dwindling of device size caused the continuous improvement of circuit performance and the continuous increase of current densities, and the continuous expansion of chip size impelled circuit function to be on the increase.Therefore the physical dimension of MOSFET is constantly being dwindled always, and its characteristic size has entered nanoscale at present.In this zone, various reality and basic restriction begin to occur, and further dwindling of device size just becomes more and more difficult.Just conventional complementary type Metal-oxide-semicondutor (complementary metal-oxide-semiconductor, be called for short CMOS) integrated circuit technique, along with constantly reducing of MOS device feature size (gate length), for suppressing short-channel effect, the doping content of tagma (channel region) must improve constantly.But improving constantly of doping content can cause carrier mobility reduction, subthreshold characteristic variation and threshold voltage to be difficult to problems such as reduction.Halo (pocket) doping method has to a certain degree been alleviated the problems referred to above, but still exists the source to omit problems such as living resistance, parasitic capacitance and leakage current increase.
Summary of the invention
The object of the present invention is to provide the doping method in a kind of MOS transistor tagma, the problem that the tagma doping method of present routine is brought can effectively be avoided or alleviate to this method.Above-mentioned purpose of the present invention is achieved by the following technical solutions:
The doping method in a kind of MOS transistor tagma, its step comprises:
1) on Semiconductor substrate, defines active area, the growth gate dielectric layer;
2) deposit gate electrode layer and sacrificial dielectric layer one, sacrificial dielectric layer one adopts earth silicon material, and photoetching and etching institute deposited dielectric layers one and gate electrode layer form gate electrode figure;
3) consecutive deposition sacrificial dielectric layer two and sacrificial dielectric layer three, the material of sacrificial dielectric layer two is a silicon nitride, the material of sacrificial dielectric layer three is a silicon dioxide, removes on the gate electrode to be in outermost sacrificial dielectric layer three, and exposes sacrificial dielectric layer two;
4) be mask with sacrificial dielectric layer one and sacrificial dielectric layer three, erode gate electrode sacrificial dielectric layer two on every side, form slit like this in the gate electrode both sides;
5) be that window carries out the ion injection with this slit, mixed in the tagma, form heavily doped region in relevant position, following tagma, gate electrode both sides;
6) deposit one deck sacrificial dielectric layer two is again returned and is carved to fill the slit of gate electrode both sides;
7) after difference erosion removal sacrificial dielectric layer one, sacrificial dielectric layer three and the sacrificial dielectric layer two, carry out conventional source drain extension region and contact zone ion implantation doping, enter the conventional cmos postchannel process at last.
Semiconductor substrate in the described step 1) is body silicon chip or soi wafer.
When Semiconductor substrate is the body silicon chip, the definite employing shallow-trench isolation or the LOCOS method of active area.
When Semiconductor substrate is soi wafer, the definite employing etching or the LOCOS method of active area.
Adopt chemico-mechanical polishing (CMP) technology that smooth processing is carried out on the surface in the described step 3), on gate electrode, be in outermost sacrificial dielectric layer three removals.
The thickness range of described sacrificial dielectric layer one is 20nm～40nm.
The thickness range of described sacrificial dielectric layer two is 10nm～100nm.
The thickness range of described sacrificial dielectric layer three must be greater than the thickness sum of gate electrode layer and dielectric layer one.
Described gate material is polysilicon or metal.
The step 5) intermediate ion is injected to multiple energy and dosage injects, and can form desirable doping impurity in the tagma and distribute by different combinations of injecting energy and dosage.
The present invention has the advantage of the following aspects:
In preparation method of the present invention, tagma heavy doping is to be undertaken by the slit crack of gate electrode both sides, so heavily doped region is strip in the channel region both sides.This strip heavily doped region can effectively shield an electric leakage influence to raceway groove and source end, makes device have good short-channel properties.Secondly, this strip heavily doped region is in the raceway groove both sides, so impurity concentration can be very low in the channel region, makes device have the subthreshold characteristic that high carrier mobility is become reconciled.In addition, this strip heavily doped region makes the n+/p that is isolated between source leakage and substrate tie (for the nMOS pipe) or p+/n (for the pMOS pipe) knot.So living electric capacity is omitted in the source and leakage current can reduce.At last, owing to inject by the slit ion, the doping compensation of source-drain area seldom.Conventional no mask inclination is injected back and is caused source-drain area to have serious impurity compensation effect, and living resistance is omitted in the increase source.
Description of drawings
Below in conjunction with accompanying drawing the present invention is illustrated in further detail:
Fig. 1～Fig. 6 show successively body silicon MOS transistor manufacture method of the present invention the main technique step, wherein:
Fig. 1 has illustrated shallow-trench isolation and the gate medium in the preparation process to grow;
Fig. 2 has illustrated the processing step that gate electrode forms;
Fig. 3 has illustrated the processing step that multilayer dielectricity forms;
Fig. 4 has illustrated the gate electrode both sides to inject the processing step of slit and the formation of tagma strip heavily doped region;
Fig. 5 has illustrated to fill the processing step of gate electrode both sides slit;
Fig. 6 has illustrated the processing step that source-drain area and gate electrode mix;
Fig. 7～Figure 12 show successively SOI MOS transistor manufacture method of the present invention the main technique step, wherein:
Fig. 7 has illustrated the active area in the preparation process to determine and the gate medium growth;
Fig. 8 has illustrated the processing step that gate electrode forms;
Fig. 9 has illustrated the processing step that multilayer dielectricity forms;
Figure 10 has illustrated the gate electrode both sides to inject the processing step of slit and the formation of tagma strip heavily doped region;
Figure 11 has illustrated to fill the processing step of gate electrode both sides slit;
Figure 12 has illustrated the processing step that source-drain area and gate electrode mix.
Embodiment
Below with reference to accompanying drawing of the present invention, more detailed description goes out most preferred embodiment of the present invention.
(1) substrate is the body silicon chip
The concrete example that described manufacture method prepares the one silicon MOS transistor, be may further comprise the steps to shown in Figure 6 by Fig. 1:
1) as shown in Figure 1, the crystal orientation of used monocrystalline substrate is (100), and to n type MOS transistor, tagma 1 is initially p type light dope.To p type MOS transistor, tagma 1 is initially n type light dope.Adopt conventional cmos shallow-trench isolation fabrication techniques active area isolation layer 2.The gate dielectric layer 3 of then growing.Gate dielectric layer 3 is a silicon dioxide, and its thickness is 0.5～3nm.The formation method of gate medium can also be one of following method: conventional thermal oxidation, nitrating thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD).
2) as shown in Figure 2, with LPCVD deposit gate electrode polysilicon layer 4 and sacrificial dielectric layer one (silicon dioxide) 5.The thickness of polysilicon layer 4 is 80～250nm, and the thickness of silicon dioxide layer 5 is 20～40nm.Then adopt the polysilicon layer 4 and the sacrificial dielectric layer 1 of the deposit of photoetching of conventional cmos technology and etching institute, form gate electrode figure.
3) as shown in Figure 3, continuously with sacrificial dielectric layer two (silicon nitride) 6 of LPCVD deposit one deck 10～100nm and the sacrificial dielectric layer three (silicon dioxide) 7 of 100～300nm, then planarization is carried out on the surface with chemico-mechanical polishing (CMP), silicon dioxide layer 7 up to the gate electrode top is removed, and silicon nitride layer 6 exposes.
4) as shown in Figure 4, fall gate electrode silicon nitride 6 on every side, form the wide slit of 10～100nm in the gate electrode both sides with hot phosphoric acid corrosion.With this slit is that passage carries out the ion injection, is mixed in the tagma.Inject to divide and to carry out for three times, to n type device, energy is respectively 20,40,60KeV, and implantation dosage is respectively 2 * 10
14Cm
-2, 1.5 * 10
14Cm
-2With 1 * 10
14Cm
-2Implanted dopant is indium (In).To p type device, energy is respectively 15,25,55KeV, and implantation dosage is respectively 2 * 10
14Cm
-2, 1.5 * 10
14Cm
-2With 1 * 10
14Cm
-2Implanted dopant is arsenic (As), forms heavily doped region 8.
5) as shown in Figure 5, adopting CVD deposit one layer thickness is silicon nitride film and time quarter of 10～100nm, makes the slit of gate electrode both sides be filled.
6) as shown in Figure 6, erode silicon dioxide layer 7 and silicon dioxide layer 5, remove all silicon nitride layers 6 with hot phosphoric acid then with BOE.Then, source-drain area is mixed to form shallow junction,, inject energy 5KeV, implantation dosage 5 * 10 n type device with the low energy ion injection
14Cm
-2, implanted dopant is arsenic (As).To p type device, inject energy 5KeV, implantation dosage 5 * 10
14Cm
-2, implanted dopant is boron fluoride (BF
2).Then with LPCVD grow a layer thickness 50～250nm silicon dioxide and return to carve, form side wall 9 in gate electrode 4 both sides.Afterwards, once more source-drain area is carried out ion implantation doping, to form drain contact district, source.To n type device, inject energy 45KeV, implantation dosage 2 * 10
15Cm
-2, implanted dopant is arsenic (As).To p type device, inject energy 35KeV, implantation dosage 2 * 10
15Cm
-2, implanted dopant is boron fluoride (BF
2).
7) enter the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make the one silicon MOS transistor.
(2) substrate is a soi wafer
It is extremely shown in Figure 12 by Fig. 7 that described manufacture method prepares the transistorized concrete example of a SOIMOS, may further comprise the steps:
1) as shown in Figure 7, the crystal orientation of used monocrystalline substrate is the soi wafer of (100).Described soi wafer is made up of substrate 35, oxygen buried layer 25 and monocrystalline silicon membrane 10.Wherein the thickness of oxygen buried layer 25 is 20nm～400nm, and the thickness of monocrystalline silicon membrane 10 is 50～200nm.To n type MOS transistor, monocrystalline silicon membrane 10 is initially p type light dope.To p type MOS transistor, monocrystalline silicon membrane 10 is initially n type light dope.Adopt conventional cmos photoetching and lithographic technique to be manufactured with the source region.The gate dielectric layer 30 of then growing.Gate dielectric layer 30 is a silicon dioxide, and its thickness is 0.5～3nm.The formation method of gate medium can also be one of following method: conventional thermal oxidation, nitrating thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD).
2) as shown in Figure 8, with LPCVD deposit gate electrode polysilicon layer 40 and sacrificial dielectric layer one (silicon dioxide) 50.The thickness of polysilicon layer 40 is 80～250nm, and the thickness of silicon dioxide layer 50 is 20～40nm.Then adopt the polysilicon layer 40 and the titanium dioxide silicon 50 of the deposit of photoetching of conventional cmos technology and etching institute, form gate electrode figure.
3) as shown in Figure 9, continuously with sacrificial dielectric layer two (silicon nitride) 60 of LPCVD deposit one deck 10～100nm and the sacrificial dielectric layer three (silicon dioxide) 70 of 100～300nm, then planarization is carried out on the surface with chemico-mechanical polishing (CMP), silicon dioxide layer 70 up to the gate electrode top is removed, and silicon nitride layer 60 exposes.
4) as shown in figure 10, fall gate electrode silicon nitride layer 60 on every side, form the wide slit of 10～100nm in the gate electrode both sides with hot phosphoric acid corrosion.With this slit is that passage carries out the ion injection, is mixed in the tagma.Inject to divide and to carry out for three times, to n type device, energy is respectively 20,40,60KeV, and implantation dosage is respectively 2 * 10
14Cm
-2, 1.5 * 10
14Cm
-2With 1 * 10
14Cm
-2Implanted dopant is indium (In).To p type device, energy is respectively 15,25,55KeV, and implantation dosage is respectively 2 * 10
14Cm
-2, 1.5 * 10
14Cm
-2With 1 * 10
14Cm
-2Implanted dopant is arsenic (As), forms heavily doped region 80.
5) as shown in figure 11, adopting CVD deposit one layer thickness is silicon nitride film and time quarter of 10～100nm, makes the slit of gate electrode both sides be filled.
6) as shown in figure 12, erode silicon dioxide layer 70 and silicon dioxide layer 50, remove all silicon nitride layers 60 with hot phosphoric acid then with BOE.Then, source-drain area is mixed to form shallow junction,, inject energy 5KeV, implantation dosage 5 * 10 n type device with the low energy ion injection
14Cm
-2, implanted dopant is arsenic (As).To p type device, inject energy 5KeV, implantation dosage 5 * 10
14Cm
-2, implanted dopant is boron fluoride (BF
2).Then with LPCVD grow a layer thickness 50～250nm silicon dioxide and return to carve, form side wall 90 in gate electrode 40 both sides.Afterwards, once more source-drain area is carried out ion implantation doping, to form drain contact district, source.To n type device, inject energy 45KeV, implantation dosage 2 * 10
15Cm
-2, implanted dopant is arsenic (As).To p type device, inject energy 35KeV, implantation dosage 2 * 10
15Cm
-2, implanted dopant is boron fluoride (BF
2).
7) enter the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make a SOI MOS transistor.
The foregoing description is of the present invention giving an example, although disclose most preferred embodiment of the present invention and accompanying drawing for the purpose of illustration, but it will be appreciated by those skilled in the art that: without departing from the spirit and scope of the invention and the appended claims, various replacements, variation and modification all are possible.Therefore, the present invention should not be limited to most preferred embodiment and the disclosed content of accompanying drawing.
Claims (9)
1, the doping method in a kind of MOS transistor tagma, its step comprises:
1) on Semiconductor substrate, defines active area, the growth gate dielectric layer;
2) deposit gate electrode layer and sacrificial dielectric layer one, sacrificial dielectric layer one adopts earth silicon material, and photoetching and etching institute deposited dielectric layers one and gate electrode layer form gate electrode figure;
3) consecutive deposition sacrificial dielectric layer two and sacrificial dielectric layer three, the material of sacrificial dielectric layer two is a silicon nitride, the material of sacrificial dielectric layer three is a silicon dioxide, removes on the gate electrode to be in outermost sacrificial dielectric layer three, and exposes sacrificial dielectric layer two;
4) be mask with sacrificial dielectric layer one and sacrificial dielectric layer three, erode gate electrode sacrificial dielectric layer two on every side, form slit like this in the gate electrode both sides;
5) be that window carries out the ion injection with this slit, mixed in the tagma, form heavily doped region in relevant position, following tagma, gate electrode both sides;
6) deposit one deck sacrificial dielectric layer two is again returned and is carved to fill the slit of gate electrode both sides;
7) after difference erosion removal sacrificial dielectric layer one, sacrificial dielectric layer three and the sacrificial dielectric layer two, carry out conventional source drain extension region and contact zone ion implantation doping, enter the conventional cmos postchannel process at last.
2, the doping method in MOS transistor as claimed in claim 1 tagma, it is characterized in that: the Semiconductor substrate in the described step 1) is body silicon chip or soi wafer.
3, the doping method in MOS transistor as claimed in claim 2 tagma is characterized in that: when Semiconductor substrate is the body silicon chip, and the definite employing shallow-trench isolation or the LOCOS method of active area.
4, the doping method in MOS transistor as claimed in claim 2 tagma is characterized in that: when Semiconductor substrate is soi wafer, and the definite employing etching or the LOCOS method of active area.
5, the doping method in MOS transistor as claimed in claim 1 tagma is characterized in that: adopt chemico-mechanical polishing CMP technology that smooth processing is carried out on the surface in the described step 3), be in outermost sacrificial dielectric layer three removals on gate electrode.
6, the doping method in MOS transistor as claimed in claim 1 tagma, it is characterized in that: the thickness range of described sacrificial dielectric layer one is 20nm～40nm.
7, the doping method in MOS transistor as claimed in claim 1 tagma, it is characterized in that: the thickness range of described sacrificial dielectric layer two is 10nm～100nm.
8, as the doping method in claim 6 or 7 described MOS transistor tagmas, it is characterized in that: the thickness of described sacrificial dielectric layer three must be greater than the thickness sum of gate electrode layer and dielectric layer one.
9, the doping method in MOS transistor as claimed in claim 1 tagma, it is characterized in that: described gate material is polysilicon or metal.
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| CN111952188A (en) * | 2020-08-21 | 2020-11-17 | 中国科学院上海微系统与信息技术研究所 | Field effect transistor with isolation layer and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1218295A (en) * | 1997-09-30 | 1999-06-02 | 西门子公司 | Reduced parasitic leakage in semiconductor devices |
| US6621114B1 (en) * | 2002-05-20 | 2003-09-16 | Advanced Micro Devices, Inc. | MOS transistors with high-k dielectric gate insulator for reducing remote scattering |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1218295A (en) * | 1997-09-30 | 1999-06-02 | 西门子公司 | Reduced parasitic leakage in semiconductor devices |
| US6621114B1 (en) * | 2002-05-20 | 2003-09-16 | Advanced Micro Devices, Inc. | MOS transistors with high-k dielectric gate insulator for reducing remote scattering |
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