CN111952188A - Field effect transistor with isolation layer and preparation method thereof - Google Patents
Field effect transistor with isolation layer and preparation method thereof Download PDFInfo
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- CN111952188A CN111952188A CN202010850667.6A CN202010850667A CN111952188A CN 111952188 A CN111952188 A CN 111952188A CN 202010850667 A CN202010850667 A CN 202010850667A CN 111952188 A CN111952188 A CN 111952188A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
Abstract
The invention provides a field effect transistor with an isolation layer and a preparation method thereof, wherein the field effect transistor comprises a bottom substrate, an insulation layer and a semiconductor substrate of a top semiconductor layer which are sequentially stacked, and the top semiconductor layer is coated with the isolation layer with a space; the projections of the gate structures in the vertical direction cover the space and form an overlapping region with the isolation layer, and the projections of the source region and the drain region in the vertical direction are completely located in the isolation layer. The source electrode and the drain electrode can be isolated from a carrier transmission channel of the top semiconductor layer below the isolation layer through the isolation layer, a leakage path of the source electrode and the drain electrode is completely isolated, the problem of electric leakage at the bottom of the top semiconductor layer is solved, the total dose irradiation resistance of the device is improved, the heat dissipation rate of a channel is guaranteed through the distance of the isolation layer, the problem of electric leakage at the side edge of the channel can be further solved, the preparation process is completely compatible with the existing CMOS process, the application range is wide, and the method can be used for preparing high-reliability integrated circuits and discrete devices.
Description
Technical Field
The invention belongs to the field of semiconductor design and manufacture, and relates to a field effect transistor with an isolation layer and a preparation method thereof.
Background
Transistors based on SOI substrates (SOI MOSFET) have good single event effect resistance, but in the SOI structure, a buried oxide layer (BOX layer) is easy to generate radiation induced charges when high-energy particles are incident, the charges are easy to cause a parasitic conductive channel in SOI top silicon, so that leakage current is introduced, and the electrical performance of the device is drifted, and the effect is called total dose effect. The total dose effect is a main reason for the failure of the SOI MOSFET device in an irradiation environment, and the SOI MOSFET device has poor capability of resisting the total dose irradiation effect and is easy to cause back gate leakage.
However, for the SOI MOSFET device with embedded cavity, i.e. the SOI MOSFET device manufactured by using a SON substrate (silicon on nothing), it has better total dose irradiation resistance, but all or part of the cavity is under the channel, and the cavity can be a vacuum environment or an environment filled with a certain gas, so the cavity has stronger heat insulation property and poorer heat dissipation property, and thus the heat dissipation property at the channel in the top layer silicon is poor. Since the channel region is the primary heat generation region in a MOSFET, SOI MOSFET devices with cavities are prone to self-heating effects.
Therefore, it is necessary to provide a field effect transistor having an isolation layer and a method for manufacturing the same.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a field effect transistor with an isolation layer and a method for fabricating the same, which are used to solve the problems of the SOI MOSFET device in the prior art such as the total dose exposure resistance effect and the self-heating effect.
To achieve the above and other related objects, the present invention provides a method for fabricating a field effect transistor having an isolation layer, the method comprising the steps of:
forming a semiconductor base, wherein the semiconductor base comprises a bottom substrate, an insulating layer and a top semiconductor layer which are sequentially stacked, an isolating layer is covered in the top semiconductor layer, and the isolating layer has a distance;
etching the top semiconductor layer to form an active region wrapping the isolation layer;
and forming a gate structure, a source region and a drain region, wherein the gate structure is positioned on the active region, the source region and the drain region are positioned in the active region, the projection of the gate structure in the vertical direction covers the interval and forms an overlapping region with the isolation layer, and the projection of the source region and the drain region in the vertical direction is completely positioned in the isolation layer.
Optionally, the isolation layer includes one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a silicon carbide layer.
Optionally, the thickness of the isolation layer ranges from 3nm to 50 nm; the size range of the isolation layer comprises 20 nm-2 mu m.
Optionally, a width of the overlap region is greater than 1/2 of a thickness of the top semiconductor layer over the isolation layer.
Optionally, a width of the spacing is greater than 2 times a thickness of the top semiconductor layer over the isolation layer.
Optionally, the thickness of the top semiconductor layer underlying the isolation layer is greater than 10 nm.
Optionally, the step of forming the semiconductor substrate includes:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate, an insulating layer and a first semiconductor layer which are stacked in sequence;
forming an isolation layer with a space on the surface of the first semiconductor layer;
forming a second semiconductor layer to cover the isolation layer and the first semiconductor layer;
annealing is performed to prepare a semiconductor substrate.
Optionally, the annealing is performed with a hydrogen atmosphere to form the semiconductor substrate with a surface roughness of less than 0.2nm, and the annealing includes:
carrying out first annealing, wherein the temperature range of the first annealing comprises 900-1400 ℃, and the time is less than 100 ms;
and carrying out second annealing, wherein the temperature range of the second annealing is below 1350 ℃ and the time is below 1-10 h.
Optionally, the step of forming the semiconductor substrate includes:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a bottom substrate, an insulating layer and a top semiconductor layer which are sequentially stacked;
forming a patterned mask on the top semiconductor layer;
performing ion implantation and annealing to form an isolation layer with a gap in the top semiconductor layer;
and removing the mask to prepare the semiconductor substrate.
Optionally, the dose range of the ion implantation comprises 1x1015/cm2～2x1017/cm2。
Optionally, the annealing is performed with a hydrogen atmosphere to form the semiconductor substrate with a surface roughness of less than 0.2nm, and the annealing includes:
carrying out first annealing, wherein the temperature range of the first annealing comprises 900-1400 ℃, and the time is less than 100 ms;
and carrying out secondary annealing, wherein the temperature range of the secondary annealing is below 1350 ℃ and the time is below 10 h.
Optionally, the method further includes a step of forming a bias electrode, where the bias electrode is in contact with the top semiconductor layer below the isolation layer, so as to electrically lead out the top semiconductor layer below the isolation layer through the bias electrode.
Optionally, forming one or a combination of an LDD doped region and a halo doped region; the LDD doped region is formed above the isolation layer or above and below the isolation layer; the halo doped region is formed in contact with or wraps the isolation layer.
Optionally, the field effect transistor comprises an NMOS device or a PMOS device.
Optionally, the method further includes a step of forming a heavily doped isolation region at a side of the channel to block a leakage path at the side of the channel through the heavily doped isolation region.
Optionally, the isolation layer extends to a side of the channel to prolong the leakage path.
Optionally, the method further comprises the step of forming a heavily doped isolation region in the isolation layer at the side of the channel.
The present invention also provides a field effect transistor having an isolation layer, the field effect transistor including:
the semiconductor substrate comprises a bottom substrate, an insulating layer and a top semiconductor layer which are sequentially stacked, wherein an isolation layer is coated in the top semiconductor layer, and the isolation layer has a distance;
a gate structure, a source region and a drain region, the gate structure being located on the top semiconductor layer, the source region and the drain region being located within the top semiconductor layer; and the projection of the grid structure in the vertical direction covers the interval and forms an overlapping region with the isolation layer, and the projection of the source electrode region and the drain electrode region in the vertical direction is completely positioned in the isolation layer.
Optionally, the isolation layer includes one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a silicon carbide layer.
Optionally, the thickness of the isolation layer ranges from 3nm to 50 nm; the size range of the isolation layer comprises 20 nm-2 mu m.
Optionally, a width of the overlap region is greater than 1/2 of a thickness of the top semiconductor layer over the isolation layer.
Optionally, a width of the spacing is greater than 2 times a thickness of the top semiconductor layer over the isolation layer.
Optionally, the thickness of the top semiconductor layer underlying the isolation layer is greater than 10 nm.
Optionally, the surface roughness of the semiconductor substrate is less than 0.2 nm.
Optionally, a bias electrode is further included, the bias electrode contacting the top semiconductor layer under the isolation layer.
Optionally, one or a combination of an LDD doped region and a halo doped region is further included; the LDD doped region is formed above the isolation layer or above and below the isolation layer; the halo doped region is formed in contact with or wraps the isolation layer.
Optionally, the channel side further includes a heavily doped isolation region to block a leakage path of the channel side through the heavily doped isolation region.
Optionally, the isolation layer extends to a side of the channel to prolong the leakage path.
Optionally, a heavily doped isolation region is further included in the isolation layer at the side of the channel.
Optionally, the field effect transistor comprises an NMOS device or a PMOS device.
As described above, according to the field effect transistor with the isolation layer and the method for manufacturing the same of the present invention, the source and drain electrodes can be isolated from the carrier transport channel of the top semiconductor layer located below the isolation layer by the isolation layer, thereby completely isolating the source and drain electrodes from the leakage path formed by the defective charges in the isolation layer, so as to fundamentally solve the problem of the leakage current at the bottom of the top semiconductor layer, improve the total dose irradiation resistance of the device, and ensure the heat dissipation rate at the channel by the distance between the isolation layers, and further, the leakage path at the side of the channel can be effectively isolated by the heavily doped isolation region at the side of the channel or the isolation layer extending to the side of the channel, and the heavily doped isolation region in the isolation layer at the side of the channel, thereby solving the. The field effect transistor with the isolation layer and the preparation method thereof ensure the excellent radiation resistance of the field effect transistor and ensure the heat dissipation rate at the channel, and the preparation process is completely compatible with the existing CMOS process, has wider application range, and can be used for preparing high-reliability integrated circuits and discrete devices.
Drawings
Fig. 1 is a schematic process flow diagram of the present invention for fabricating a field effect transistor with an isolation layer.
Fig. 2 to 7 are schematic structural views showing steps of preparing a semiconductor substrate according to the present invention.
FIGS. 8-12 are schematic structural views showing steps of another semiconductor substrate manufacturing method according to the present invention.
FIGS. 13a to 13c are schematic diagrams showing top views and cross-sectional structures along AA 'and BB' of the semiconductor substrate of the present invention.
Fig. 14a to 14c are schematic sectional views along AA 'and BB' of the top view after forming the active region according to the present invention.
Fig. 15a to 15c are schematic sectional views along AA 'and BB' of the top view after forming the gate metal layer according to the present invention.
Fig. 16a to 16c are schematic diagrams showing a top view and cross-sectional structures along AA 'and BB' after forming a gate electrode in the present invention.
Fig. 17a to 17c are schematic diagrams showing a top view and cross-sectional structures along AA 'and BB' of the gate sidewall formed in the present invention.
Fig. 18a to 18c are enlarged schematic views of the region a in fig. 17.
Fig. 19 is a schematic view showing a structure after forming a bias electrode in the present invention.
Fig. 20 a-20 b are schematic structural views illustrating the formation of heavily doped isolation regions at the sides of the channel in the present invention.
FIGS. 21a to 21c are schematic views showing structures of spacers extending to the side of the trench in the present invention.
Description of the element reference numerals
101. 201 bottom lining
102. 202 insulating layer
103. 203 top semiconductor layer
1031 first semiconductor layer
1032. 1033 second semiconductor layer
104. 204 isolation layer
1041. 2041 pitch
205 mask
105 gate dielectric layer
106 gate metal layer
107 grid side wall
108 LDD doped region
109 source drain region
110 halo doped region
111 bias electrode
112. 113 heavily doped isolation region
A. Region B
C channel side region
a width of the overlapping area
b thickness of
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, in this embodiment, a method for manufacturing a field effect transistor with an isolation layer is provided, in which a source electrode and a drain electrode are isolated from a carrier transmission channel of a top semiconductor layer located below the isolation layer by the isolation layer, so that the source electrode and the drain electrode are completely isolated from a leakage path formed by defect charges in the isolation layer, thereby fundamentally solving a problem of leakage at the bottom of the top semiconductor layer and improving a total dose irradiation resistance of a device. The field effect transistor with the isolation layer and the preparation method thereof ensure the excellent radiation resistance of the field effect transistor and ensure the heat dissipation rate at the channel, and the preparation process is completely compatible with the existing CMOS process, has wider application range, and can be used for preparing high-reliability integrated circuits and discrete devices.
Referring to fig. 2 to 21c, the structure of the steps in forming the field effect transistor with the isolation layer is shown schematically.
First, referring to fig. 2 to 12, a semiconductor substrate is formed, the semiconductor substrate includes a bottom substrate, an insulating layer, and a top semiconductor layer stacked in sequence, the top semiconductor layer is covered with an isolation layer, and the isolation layer has a gap.
Referring to fig. 2 to 7, as an example, the step of forming the semiconductor substrate includes:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a base substrate 101, an insulating layer 102 and a first semiconductor layer 1031 which are stacked in sequence;
forming an isolation layer 104 with a spacing 1041 on the surface of the first semiconductor layer 1031;
forming second semiconductor layers 1032 and 1033 to cover the isolation layer 104 and the first semiconductor layer 1031;
and annealing to prepare the semiconductor substrate.
First, referring to fig. 2, the semiconductor substrate is provided, and the base substrate 101 may be Si, Ge, GaN, SiC, GaAs, AlGaN, Ga2O3The InP material layer may be a combination of two or more of the above material layers. Of course, other crystalline semiconductors are also possible, and are not limited thereto. The insulating layer 102 may be silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium aluminum oxide, zirconium oxide, hafnium zirconium oxide, lanthanum lutetium oxide, or other insulating dielectrics, or may be a combination of two or more of the above material layers, or may be other insulating dielectric layers, which is not limited thereto. The first semiconductor layer 1031 may be Si, Ge, GaN, SiC, GaAs, AlGaN, Ga2O3The InP material layer may be a combination of two or more of the above material layers. Of course, other crystalline semiconductors are also possible, and are not limited thereto. In this embodiment, the semiconductor substrate is an SOI substrate, but is not limited thereto.
Next, referring to fig. 3 and fig. 4, the isolation layer 104 with the pitch 1041 is formed on the surface of the first semiconductor layer 1031.
The method for forming the isolation layer 104 includes selecting high temperature dry oxygen oxidation and high temperature nitridation processes to prepare high quality silicon oxide film and silicon nitride film, or using N2O, NO, preparing the silicon oxynitride film at high temperature by using the nitrogen-oxygen mixed gas, so that the isolation layer 104 comprises one of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer.
After the isolation layer 104 covering the first semiconductor layer 1031 is formed, the isolation layer 104 is patterned by using an etching method, so as to form the isolation layer 104 with the distance 1041 on the surface of the first semiconductor layer 1031. Preferably, a high selectivity etching process is used to avoid damaging the surface of the first semiconductor layer 1031.
Referring to fig. 5, the second semiconductor layer 1033 covering the isolation layer 104 and the second semiconductor layer 1032 covering the first semiconductor layer 1031 are formed.
Specifically, since the isolation layer 104 cannot provide the original single crystal orientation, when the second semiconductor layer is grown, a growth rate above the isolation layer 104 is slow or no growth occurs, so that a layer of polysilicon (not shown) may be deposited in advance before the second semiconductor layer is formed, and the thickness of the polysilicon is preferably 5nm, so that the growth of the second semiconductor layer is performed after the polysilicon is recrystallized by high-temperature annealing.
In this embodiment, the second semiconductor layer is directly grown on the first semiconductor layer 1031, so as to reduce the process complexity. Wherein the second semiconductor layer 1033 deposited on the surface of the isolation layer 104 is in a polycrystalline state, and the second semiconductor layer 1032 deposited on the surface of the first semiconductor layer 1031 is in a single crystalline state that is consistent with the crystal orientation of the first semiconductor layer 1031. Referring to fig. 6, a schematic diagram of a partially enlarged structure of a region a in fig. 5 is shown, wherein a grain boundary exists between the second semiconductor layer 1033 in a polycrystalline state located above the isolation layer 104 and the second semiconductor layer 1032 in a single crystalline state located above the first semiconductor layer 1031.
Further, since the isolation layer 104 cannot provide the original single crystal orientation, when the second semiconductor layer is grown, a situation that the growth speed is slow or no growth occurs above the isolation layer 104, and therefore, when the size area of the isolation layer 104 is small, the second semiconductor layer 1033 in a single crystal state can be formed on the surface of the isolation layer 104 by the lateral epitaxy of the second semiconductor layer 1033 on the surface of the first semiconductor layer 1031, which is not limited herein.
Referring to fig. 7, after annealing, the semiconductor substrate may be prepared.
As an example, the annealing is performed with a hydrogen atmosphere to form the top semiconductor layer 103 having a surface roughness of less than 0.2nm, and the annealing includes:
carrying out first annealing, wherein the temperature range of the first annealing comprises 900-1400 ℃, and the time is less than 100 ms;
and carrying out second annealing, wherein the temperature range of the second annealing is below 1350 ℃ and the time is below 1-10 h.
Specifically, the first annealing may be ultra-fast high-temperature annealing, such as an ultra-fast laser annealing process. The first annealing atmosphere is preferably hydrogen or a gas containing hydrogen ions, and when the annealing time is less than 100ms, the first annealing temperature is higher than 900 ℃ and can be raised to 1400 ℃. After the ultrafast high temperature annealing, the method further includes performing the second annealing at 1350 ℃ or below to perform a supplementary annealing, where the second annealing duration is preferably 3 hours, and may be specifically adjusted according to the thickness of the first semiconductor layer 1031, the thickness of the isolation layer 104, and the thicknesses of the second semiconductor layers 1032 and 1033. Wherein, the second annealing atmosphere is preferably hydrogen or a gas containing hydrogen ions, the second semiconductor layer 1033 above the isolation layer 104 can obtain higher mobility under the assistance of hydrogen ions, thereby facilitating recrystallization of the material layer above the isolation layer 104 and surface planarization of the entire top semiconductor layer 103, and the surface roughness of the top semiconductor layer 103 is preferably less than 0.2nm, such as 0.15nm, 0.1nm, and the like, so as to improve the performance of a subsequently manufactured device. Of course, in another embodiment, the ultrafast high temperature annealing process may not be adopted, and the annealing temperature should be higher than 900 ℃ and lower than 1350 ℃, and the rest annealing conditions may not be changed, which will not be described herein. When the second semiconductor layer is formed to be thick, it is difficult to completely flatten the surface of the top semiconductor layer 103 only by using the annealing process, and at this time, a process of first CMP thinning and polishing and then annealing or a process of first annealing and then CMP thinning and polishing may be used to obtain a flattened surface of the top semiconductor layer 103.
Illustratively, the thickness of the isolation layer 104 may range from 3nm to 50 nm.
Specifically, in the present embodiment, the thickness of the isolation layer 104 is preferably 5nm, so that the isolation layer 104 has a relatively thin thickness, and thus the defect charges generated in the isolation layer 104 are relatively small and easily disappear by itself under the action of an external electric field. In addition, since the upper and lower interfaces of the isolation layer 104 are wrapped by the top semiconductor layer 103 communicated with each other by the distance 1041, the electric field intensity of the upper and lower interfaces of the isolation layer 104 is small, and it is not easy to introduce defect charges into the isolation layer 104, but the thickness of the isolation layer 104 is not limited thereto, and may be 3nm, 6nm, 8nm, or the like, and may be selected as needed.
By way of example, the size range of the isolation layer 104 includes 20nm to 2 μm.
Specifically, after the photolithography, if the remaining planar size of the isolation layer 104 is too large, the difficulty of converting the polycrystalline material layer above the isolation layer 104 into the single-crystalline material layer is large, and the surface of the second semiconductor layer 1033 above the isolation layer 104 is finally higher than the surface of the second semiconductor layer 1032 above the first semiconductor layer 1031, so that it is difficult to obtain a flat surface only by annealing, and a planarization process such as CMP is additionally performed. The size and the morphology of the isolation layer 104 need to correspond to those of a source and drain region formed subsequently, so that the projection of the source region and the drain region in the vertical direction can be completely located in the isolation layer 104, the source and drain electrodes can be completely isolated from the first semiconductor layer 1031 below the isolation layer 104 by the isolation layer 104, and a leakage path formed by the source and drain electrodes and the defect charges in the insulating layer 102 is completely isolated, so that the problem of leakage at the bottom of the top semiconductor layer 103 is fundamentally solved, and the total dose irradiation resistance of the device is improved. In this embodiment, the size of the isolation layer 104 is preferably 20nm to 2 μm, and the profile of the isolation layer 104 is preferably square, that is, the size of the isolation layer 104 is 20nm × 20nm to 2 μm × 2 μm, but the invention is not limited thereto, the size of the isolation layer 104 may be 100nm, 500nm, 1 μm, 1.5 μm, etc., and the profile of the isolation layer 104 may be other polygons such as rectangle, circle, triangle, etc., which is not limited herein.
Referring to fig. 8 to 12, the present embodiment further provides another method for manufacturing a semiconductor substrate, wherein the step of forming the semiconductor substrate includes:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a bottom substrate 201, an insulating layer 202 and a top semiconductor layer 203 which are sequentially stacked;
forming a patterned mask 205 on the top semiconductor layer 203;
performing ion implantation and annealing to form an isolation layer 204 with a spacing 2041 in the top semiconductor layer 203;
the mask 205 is removed to prepare the semiconductor substrate.
Specifically, the material of the semiconductor substrate is selected, and is not described herein again. Wherein the thickness of the top semiconductor layer 103 is preferably greater than 10nm, but not limited thereto, the thickness of the top semiconductor layer 103 may also be, for example, 15nm, 20nm, 25nm, etc. The mask 205 may be prepared by a dry method, a wet oxidation process, a nitridation process, or by a CVD or PVD deposition, and the thickness of the mask 205 needs to be larger than the depth of the implanted ions, so that the formed isolation layer 204 is embedded in the top semiconductor layer 203. When the mask 205 is etched, a high selectivity etching process is preferred to avoid damaging the surface of the top semiconductor layer 203, the size of the etching window of the mask 205 defines the size of the isolation layer 204, and details regarding the size and the morphology of the isolation layer 204 are omitted here.
As an example, the ion implantation includes implanting one or a mixture of oxygen ions, nitrogen gas, and carbon ions; the implantation dose comprises 1x1015/cm2～2x1017/cm2(ii) a The isolation layer 204 includes one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a silicon carbide layer.
Specifically, the distribution of the implanted ions in the top semiconductor layer 203 is close to gaussian distribution, and the depth position of the peak value of the bulk concentration of the implanted ions is the depth position of the isolation layer 204. The ion implantation will be to the top semiconductorThe layer 203 is damaged, causing a large number of defects in said top semiconductor layer 203, which are bombarded by implanted ions, even turning into an amorphous state, which will react with said top semiconductor layer 203 to form, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, etc., as said isolation layer 204. Wherein, the implantation dose can be 5x1015/cm2、1x1016/cm2、5x1016/cm2、1x1017/cm2And the like, to form the isolation layer 204 with a predetermined thickness and depth, wherein the depth of the isolation layer 204 may range from 5nm to 20nm, such as a depth of 10nm, 15nm, and the like, and the thickness of the isolation layer 204 may range from 5nm to 20nm, such as a thickness of 10nm, 15nm, and the like.
As an example, the annealing is performed using a hydrogen atmosphere to form the top semiconductor layer 203 having a surface roughness of less than 0.2nm, and the annealing includes:
carrying out first annealing, wherein the temperature range of the first annealing comprises 900-1400 ℃, and the time is less than 100 ms;
performing a second annealing at a temperature below 1350 ℃ for a time below 10h
Specifically, the annealing step will promote further reaction of the implanted ions with the top semiconductor layer 203 while re-crystallizing the damaged top semiconductor layer 203 to return to a single crystalline state. The first annealing may be ultra-fast high temperature annealing, such as ultra-fast laser annealing. The first annealing atmosphere is preferably hydrogen or a gas containing hydrogen ions, and when the annealing time is less than 100ms, the first annealing temperature is higher than 900 ℃ and can be raised to 1400 ℃. After the ultrafast high temperature annealing, performing the second annealing at 1350 ℃ or below to perform a supplementary annealing, wherein the duration of the second annealing is preferably 10 hours, and the second annealing can be specifically adjusted according to the thickness of the top semiconductor layer 203 and the dosage of implanted ions. The second annealing atmosphere is preferably hydrogen or a gas containing hydrogen ions, the top semiconductor layer 203 above the isolation layer 204 may obtain a higher mobility with the assistance of hydrogen ions, thereby facilitating recrystallization of the top semiconductor layer 203 above the isolation layer 204 and surface planarization of the entire top semiconductor layer 203, and the surface roughness of the top semiconductor layer 203 is preferably less than 0.2nm, such as 0.15nm, 0.1nm, and the like. Of course, in another embodiment, the ultrafast high temperature annealing process may not be adopted, so that the annealing temperature should be higher than 900 ℃ and lower than 1350 ℃, and the rest annealing conditions are not changed, which will not be described herein.
When the dose of the implanted ions is large, that is, the thickness of the isolation layer 204 is large, it is difficult to completely flatten the surface of the top semiconductor layer 203 only by using the annealing process, or when the window of the implanted ions is too large, it is difficult to completely flatten the surface of the top semiconductor layer 203 only by using the annealing process, so that in this case, a process of first performing CMP thinning and polishing and then performing annealing, or a process of first performing annealing and then performing CMP thinning and polishing can be used to obtain a flat surface of the top semiconductor layer 203.
Referring to fig. 13a to 13c, in the present embodiment, the semiconductor substrate has the bottom substrate 101, the insulating layer 102 and the top semiconductor layer 103, and the isolation layer 104 with the distance 1041 is covered in the top semiconductor layer 103, which is taken as an example and not limited thereto.
The semiconductor substrate may have well doping and threshold voltage adjusting doping, the well doping region may cover the isolation layer 104, and the threshold voltage adjusting doping is located above the isolation layer 104, and the preparation of the well doping and the threshold voltage adjusting doping is not described herein.
By way of example, the field effect transistor includes an NMOS device or a PMOS device, and is not intended to be unduly limited herein.
Referring to fig. 14a to 14c, the top semiconductor layer 103 is etched to form an active region covering the isolation layer 103, and the source electrode and the drain electrode formed subsequently are completely isolated by the isolation layer 104 in the vertical direction by etching, so that only the top semiconductor layer 103 below the channel is remained, and the top semiconductor layer 103 located at the upper and lower interfaces of the isolation layer 104 is communicated with each other through the space 1041.
As an example, after etching the top semiconductor layer 103 to form the active region, a step of preparing an STI isolation structure (not shown) may be further included.
Specifically, after the top semiconductor layer 103 is etched to form the active region, an insulating dielectric layer may be deposited on the surface of the top semiconductor layer 103, and then the insulating dielectric layer on the surface of the active region is removed by a CMP process, so as to form the STI isolation structure on the side of the active region. The choice of material for the STI isolation structures is not overly limited herein.
Next, referring to fig. 15a to 18c, a gate structure, a source region and a drain region are formed, wherein the gate structure is located on the active region, and the source region and the drain region are located in the active region; in the vertical direction, the projections of the gate structures cover the space 1041 and form an overlapping region with the isolation layer 104, and the projections of the source region and the drain region are completely located in the isolation layer 104.
In this embodiment, a Gate-First process is used to describe a preparation method of a device, and the device may be prepared by a Gate-last process through adjustment of simple process steps, where the structure of the device is close to that of the Gate-First process, and details regarding preparation of the Gate-last process are not described here.
Referring to fig. 15a to 15c, a gate dielectric layer 105 is formed, a gate conductive layer is formed on the gate dielectric layer 105, and then, referring to fig. 16a to 16c, etching is performed to form the gate structure.
Specifically, the gate dielectric layer 105 may be prepared by thermal oxidation, atomic layer deposition, or the like, and the gate dielectric layer 105 may be made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium aluminum oxide, zirconium oxide, hafnium zirconium oxide, lanthanum lutetium oxide, or other dielectric materials with good insulation properties. The gate conductive layer may be made of polysilicon, Ti, Cu, Al, W, Ni, Cr, Ta, Mo, TiN, TaN, or other conductive materials or alloy materials. In this embodiment, the gate dielectric layer 105 is a gate oxide layer, and the gate conductive layer is a gate metal layer 106, but is not limited thereto.
Illustratively, the width a of the overlap region is greater than 1/2 of the thickness b of the top semiconductor layer above the isolation layer 104 to isolate the source-drain doped region from the top semiconductor layer 103 below the isolation layer 104 to avoid creating a conductive channel in the spacing 1041 of the isolation layer 104. Wherein a thickness b of the top semiconductor layer 103 over the isolation layer 104 ranges from 10nm to 200nm, such as 20nm, 50nm, 100nm, or any other range of points.
As an example, the width of the spacing 1041 is greater than 2 times the thickness b of the top semiconductor layer 103 above the isolation layer 104 to reduce the influence of the interface charges of the isolation layer 104 on the channel, so that the channel can be completely turned off by the gate electrode.
As an example, the thickness of the top semiconductor layer 103 below the isolation layer 104 is larger than 10nm, preferably 20nm to 50nm, such as a value in any range of 30nm, 40nm, etc., so that the back leakage channel does not communicate with the conductive channel of the top semiconductor layer 103 above the isolation layer 104.
Further, referring to fig. 16b, after the gate metal layer 106 is formed by etching and before the source/drain region 109 is formed, the method further includes forming an LDD doped region 108 by using the gate metal layer 106 as a mask, and may further include forming a gate sidewall structure 107 and forming a halo doped region 110, as shown in fig. 17a to 18 c.
In particular, referring to fig. 18 a-18 c, the LDD doped regions 108 and the halo doped regions 110 are of opposite doping ion types. Taking NMOS as an example, the ion type of the LDD doped region 108 is N type, and the ion type of the halo doped region 110 is P type, but not limited thereto, and the device may also be PMOS, which is not limited herein. Through the gate sidewall structure 107, the mechanical performance of the gate structure can be improved, and the insulation between the gate structure and a subsequently formed source/drain electrode is ensured. The halo doped region 110 may be formed before or after the gate sidewall structure 107 is formed, which is not limited herein.
Further, a step of forming a buffer protection layer (not shown) may be further included when the dopant implantation is performed, and the buffer protection layer may be removed after the dopant implantation is completed and the annealing activation. The buffer protection layer can be made of silicon nitride, silicon oxide or other insulating films, and surface damage caused by ion bombardment in the ion implantation process can be effectively avoided through the buffer protection layer.
As an example, the LDD doped regions 108 may be formed above the isolation layer 104 or above and below the isolation layer 104; the halo doped region 110 is formed in contact with the isolation layer 104 or wraps around the isolation layer 104.
Specifically, referring to fig. 18a to 18c, a partial enlarged view of the region B in fig. 17B is shown. When the isolation layer 104 is wrapped by the halo doping region 110, a large potential barrier exists between the doping region and the channel, so that the generation of body leakage can be further avoided.
Finally, the processes of preparing source, drain and gate contact electrodes, device passivation layers, metal interconnection lines and the like are also included, and are the same as the general processes, and are not described in detail herein. For example, a passivation layer may be formed by using a low pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, or the like, and a material of the passivation layer includes, but is not limited to, silicon oxide, and then an opening is formed above the source and drain regions 109 by an etching process, and finally the source, drain, and gate contact electrodes are formed in the opening.
As an example, a step of forming a bias electrode 111 may be further included, the bias electrode 111 being in contact with the top semiconductor layer 103 under the isolation layer 104 to electrically extract the top semiconductor layer 103 under the isolation layer 104 through the bias electrode 111.
Specifically, referring to fig. 19, the bias electrode 111 can adjust the potential of the lower interface of the isolation layer 104 to further reduce the probability of generating defect charges in the isolation layer, so that the defect charges in the isolation layer 104 can hardly introduce a leakage path in the device.
As an example, a step of forming a heavily doped isolation region 112 at a side of the channel may be further included to block a leakage path at the side of the channel through the heavily doped isolation region 112.
Specifically, referring to fig. 20a and 20b, the isolation layer 104 is located below the halo doped region 110, the LDD doped region 108, and the source/drain region 109, and the heavily doped isolation region 112 may be overlapped with or not overlapped with the isolation layer 104. In this embodiment, an NMOS is taken as an example, and therefore, the heavily doped isolation region 112 is a P-type heavily doped region, but is not limited thereto, and the device may also be a PMOS.
As an example, the isolation layer 104 extends to the side of the channel to prolong the leakage path.
Specifically, referring to fig. 21a to 21b, the isolation layer 104 extends to the side of the channel to extend the leakage path, as shown in fig. 21b, the leakage path can be effectively extended through the region C extending from the side of the channel, so that the leakage resistance can be increased, and the leakage current can be reduced.
Further, referring to fig. 21C, in the region C, a step of forming a heavily doped isolation region 113 may be further included to further effectively prevent the problem of side leakage of the channel through the heavily doped isolation region 113. Of course, when the extension path of the region C is long enough, the heavily doped isolation region 113 may not be prepared, and is not limited herein.
The present embodiment also provides a field effect transistor having an isolation layer, where the field effect transistor is preferably prepared by the above preparation method, and of course, may also be prepared by other methods. Wherein the field effect crystal comprises:
the semiconductor device comprises a semiconductor base, a first substrate and a second substrate, wherein the semiconductor base comprises a bottom substrate 101, an insulating layer 102 and a top semiconductor layer 103 which are sequentially stacked, an isolation layer 104 is coated in the top semiconductor layer 103, and the isolation layer 104 has a distance 1041;
a gate structure located on the top semiconductor layer 103, source and drain regions located within the top semiconductor layer 103; in the vertical direction, the projections of the gate structures cover the space 1041 and form an overlapping region with the isolation layer 104, and the projections of the source region and the drain region are completely located in the isolation layer 104.
By way of example, the isolation layer 104 includes one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a silicon carbide layer.
By way of example, the thickness of the isolation layer 104 may range from 3nm to 50 nm; the size range of the isolation layer 104 includes 20nm to 2 μm.
As an example, the width a of the overlap region is larger than 1/2 of the thickness b of the top semiconductor layer 103 located above the isolation layer 104.
As an example, the width of the spacing 1041 is greater than 2 times the thickness b of the top semiconductor layer 103 above the isolation layer 104.
As an example, the thickness of the top semiconductor layer 103 under the isolation layer 104 is greater than 10 nm. As an example, the surface roughness of the semiconductor substrate is less than 0.2 nm.
As an example, a bias electrode 111 is further included, the bias electrode 111 being in contact with the top semiconductor layer 103 under the isolation layer 104.
As an example, one or a combination of LDD doped regions 108 and halo doped regions 109 are also included; the LDD doped regions 108 are located above the isolation layer 104 or above and below the isolation layer 104; the halo doped region 109 is in contact with the isolation layer 104 or wraps around the isolation layer 104.
As an example, the channel side further includes a heavily doped isolation region 112 to block a leakage path of the channel side through the heavily doped isolation region 112.
As an example, the isolation layer 104 extends to the side of the channel to prolong the leakage path.
Illustratively, a heavily doped isolation region 113 is also included in the isolation layer 104 on the sides of the channel.
By way of example, the field effect transistor comprises an NMOS device or a PMOS device.
In summary, according to the field effect transistor with the isolation layer and the method for manufacturing the field effect transistor with the isolation layer of the present invention, the source electrode and the drain electrode can be isolated from the carrier transport channel of the top semiconductor layer located below the isolation layer through the isolation layer, so that the source electrode and the drain electrode are completely isolated from the leakage path formed by the defect charges in the isolation layer, the problem of leakage at the bottom of the top semiconductor layer is fundamentally solved, the total dose irradiation resistance of the device is improved, the heat dissipation rate at the channel is ensured by the distance between the isolation layers, and further, the leakage path at the side of the channel can be effectively isolated through the heavily doped isolation region at the side of the channel or the isolation layer extending to the side of the channel, and the leakage problem at the side of the channel is. The field effect transistor with the isolation layer and the preparation method thereof ensure the excellent radiation resistance of the field effect transistor and ensure the heat dissipation rate at the channel, and the preparation process is completely compatible with the existing CMOS process, has wider application range, and can be used for preparing high-reliability integrated circuits and discrete devices.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (18)
1. A method of fabricating a field effect transistor having an isolation layer, the method comprising the steps of:
forming a semiconductor base, wherein the semiconductor base comprises a bottom substrate, an insulating layer and a top semiconductor layer which are sequentially stacked, an isolating layer is covered in the top semiconductor layer, and the isolating layer has a distance;
etching the top semiconductor layer to form an active region wrapping the isolation layer;
and forming a gate structure, a source region and a drain region, wherein the gate structure is positioned on the active region, the source region and the drain region are positioned in the active region, the projection of the gate structure in the vertical direction covers the interval and forms an overlapping region with the isolation layer, and the projection of the source region and the drain region in the vertical direction is completely positioned in the isolation layer.
2. The method of claim 1, wherein: the isolation layer comprises one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and a silicon carbide layer; the thickness range of the isolation layer comprises 3 nm-50 nm; the size range of the isolation layer comprises 20 nm-2 mu m.
3. The method of claim 1, wherein: the width of the overlap region is greater than 1/2 a thickness of the top semiconductor layer over the isolation layer.
4. The method of claim 1, wherein: the width of the spacing is greater than 2 times the thickness of the top semiconductor layer over the isolation layer.
5. The method of claim 1, wherein: the thickness of the top semiconductor layer below the isolation layer is greater than 10 nm.
6. The method according to claim 1, wherein the step of forming the semiconductor substrate includes:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate, an insulating layer and a first semiconductor layer which are stacked in sequence;
forming an isolation layer with a space on the surface of the first semiconductor layer;
forming a second semiconductor layer to cover the isolation layer and the first semiconductor layer;
annealing to prepare a semiconductor substrate with a surface roughness of less than 0.2 nm; the annealing is carried out in a hydrogen atmosphere, the annealing comprises a first annealing and a second annealing, the temperature range of the first annealing comprises 900-1400 ℃, the time is less than 100ms, and the temperature range of the second annealing comprises 1350 ℃ and less than 1 h-10 h.
7. The method according to claim 1, wherein the step of forming the semiconductor substrate includes:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a bottom substrate, an insulating layer and a top semiconductor layer which are sequentially stacked;
forming a patterned mask on the top semiconductor layer;
performing ion implantation and annealing to form an isolation layer with a gap in the top semiconductor layer; wherein the dose range of the ion implantation comprises 1x1015/cm2～2x1017/cm2(ii) a The annealing is carried out by adopting a hydrogen atmosphere, and the annealing comprises a first annealing and a second annealing, wherein the temperature range of the first annealing comprises 900-1400 ℃, the time is less than 100ms, and the temperature range of the second annealing comprises 1350 ℃ or less, and the time is less than 10 h;
and removing the mask to prepare the semiconductor substrate with the surface roughness less than 0.2 nm.
8. The method of claim 1, wherein: the method further comprises the step of forming a bias electrode, wherein the bias electrode is in contact with the top semiconductor layer below the isolation layer so as to lead out the top semiconductor layer below the isolation layer electrically through the bias electrode; forming one or a combination of an LDD doped region and a halo doped region, wherein the LDD doped region is formed above the isolation layer or above and below the isolation layer, and the halo doped region is formed to be in contact with or wrap the isolation layer; the method also comprises the step of forming a heavily doped isolation region at the side edge of the channel so as to cut off a leakage current path at the side edge of the channel through the heavily doped isolation region.
9. The method of claim 1, wherein: the isolation layer extends to the side edge of the channel to prolong the leakage path; further comprising the step of forming a heavily doped isolation region in the isolation layer lateral to the channel.
10. A field effect transistor having an isolation layer, the field effect transistor comprising:
the semiconductor substrate comprises a bottom substrate, an insulating layer and a top semiconductor layer which are sequentially stacked, wherein an isolation layer is coated in the top semiconductor layer, and the isolation layer has a distance;
a gate structure, a source region and a drain region, the gate structure being located on the top semiconductor layer, the source region and the drain region being located within the top semiconductor layer; and the projection of the grid structure in the vertical direction covers the interval and forms an overlapping region with the isolation layer, and the projection of the source electrode region and the drain electrode region in the vertical direction is completely positioned in the isolation layer.
11. The field effect transistor of claim 10, wherein: the isolation layer comprises one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and a silicon carbide layer; the thickness range of the isolation layer comprises 3 nm-50 nm; the size range of the isolation layer comprises 20 nm-2 mu m.
12. The field effect transistor of claim 10, wherein: the width of the overlap region is greater than 1/2 a thickness of the top semiconductor layer over the isolation layer.
13. The field effect transistor of claim 10, wherein: the width of the spacing is greater than 2 times the thickness of the top semiconductor layer over the isolation layer.
14. The field effect transistor of claim 10, wherein: the thickness of the top semiconductor layer below the isolation layer is greater than 10 nm.
15. The field effect transistor of claim 10, wherein: the surface roughness of the semiconductor substrate is less than 0.2 nm.
16. The field effect transistor of claim 10, wherein: further comprising a bias electrode in contact with the top semiconductor layer below the isolation layer; the LDD doped region is formed above the isolation layer or above and below the isolation layer, and the formed halo doped region is in contact with the isolation layer or wraps the isolation layer; the side edge of the channel also comprises a heavily doped isolation region so as to cut off a leakage current path of the side edge of the channel through the heavily doped isolation region.
17. The field effect transistor of claim 10, wherein: the isolation layer extends to the side edge of the channel to prolong the leakage path; heavily doped isolation regions are also included in the isolation layer lateral to the channel.
18. The field effect transistor of claim 10, wherein: the field effect transistor comprises an NMOS device or a PMOS device.
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