CN108447824A - A kind of semiconductor devices and its manufacturing method - Google Patents
A kind of semiconductor devices and its manufacturing method Download PDFInfo
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- CN108447824A CN108447824A CN201710094875.6A CN201710094875A CN108447824A CN 108447824 A CN108447824 A CN 108447824A CN 201710094875 A CN201710094875 A CN 201710094875A CN 108447824 A CN108447824 A CN 108447824A
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- stressor layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A kind of semiconductor devices of present invention offer and its manufacturing method, including：Semiconductor substrate is provided, the semiconductor substrate includes the areas PMOS, and the first fin structure is formed on the substrate in the areas PMOS；The first stressor layers are formed in the source/drain region of first fin structure；Form the first cap layer for covering first stressor layers；Form the interlayer dielectric layer for covering first cap layer；Etching is executed, to form the first contact hole opening in the interlayer dielectric layer and the first cap layer, the first contact hole opening exposes first stressor layers；The metal silicide contacted with first stressor layers is formed in first contact hole opening；Conductive layer is filled in first contact hole opening.The manufacturing method of semiconductor devices provided by the invention can reduce the contact resistance between metal silicide and source-drain area in the areas PMOS, improve the performance of semiconductor devices.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its manufacturing method.
Background technology
With the continuous development of semiconductor technology, the raising of performance of integrated circuits is mainly by constantly reducing integrated circuit
The size of device is realized with improving its speed.Currently, due in pursuing high device density, high-performance and low cost half
Conductor industry has advanced to that nanotechnology process node, the preparation of semiconductor devices are limited by various physics limits.
With the continuous diminution of cmos device size, the challenge from manufacture and design aspect has promoted three dimensional design such as fin
The development of gate fin-fet (FinFET).Relative to existing planar transistor, FinFET is to be used for 20nm and following work
The advanced semiconductor device of skill node, can effectively control device it is scaled caused by be difficult to the short channel overcome effect
It answers, the density of transistor array formed on a substrate can also be effectively improved, meanwhile, the grid in FinFET is set around fin
It sets, therefore electrostatic can be controlled from three faces, the performance in terms of Electrostatic Control is also more prominent.
With the continuous diminution of transistor feature size and the continuous increase of integrated circuit level, the outside of transistor is posted
Raw resistance (parasitic external resistance, abbreviation Rext) becomes limit transistor and performance of integrated circuits
Principal element.In the resistance components of composition Rext, the contact resistance (Rc) of regions and source/drain is due to metal/semiconductor
The diminution of contact area and increase so that contact resistance becomes the chief component of ectoparasitism resistance.In 14nm and its
When with lower node, Rext can significantly reduce the performance of semiconductor devices, except non-source, the ohmic contact resistance in the region (S/D) that drains
(Specific Contact Resistivity, ρ c) reduces.
Therefore, to solve the above-mentioned problems, it is necessary to propose a kind of new semiconductor devices and its manufacturing method.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention provides a kind of manufacturing method of semiconductor devices, the method includes：
Semiconductor substrate is provided, the semiconductor substrate includes the areas PMOS, and first is formed on the substrate in the areas PMOS
Fin structure；
The first stressor layers are formed in the source/drain region of first fin structure；
Form the first cap layer for covering first stressor layers；
Form the interlayer dielectric layer for covering first cap layer；
Etching is executed, is open with forming the first contact hole in the interlayer dielectric layer and the first cap layer, described first
Contact hole opening exposes first stressor layers；
The metal silicide contacted with first stressor layers is formed in first contact hole opening；
Conductive layer is filled in first contact hole opening.
Illustratively, first stressor layers are SiGe layer.
Illustratively, the content of Ge is 5%-50% in first stressor layers.
Illustratively, first stressor layers are also doped with B ions.
Illustratively, the doping concentration of the B in first stressor layers is less than 1E22cm-3。
Illustratively, doped with B ions in first cap layer.
Illustratively, the doping concentration of the B is not less than 1E21cm-3。
Illustratively, also doped with Ge ions in first cap layer.
Illustratively, the semiconductor substrate further includes NMOS area, and the second fin is formed on the substrate of the NMOS area
Structure, the manufacturing method further include：The second stressor layers are formed in the source/drain region of second fin structure；
The second cap layer for covering second stressor layers is formed, the interlayer dielectric layer covers second cap layer；
Etching is executed, is open with forming the second contact hole in the interlayer dielectric layer and the second cap layer, described second
Contact hole opening exposes second stressor layers；
The metal silicide contacted with second stressor layers is formed in second contact hole opening；
Conductive layer is filled in second contact hole opening.
Illustratively, second stressor layers are SiP layers.
The present invention also provides a kind of semiconductor devices, including：
Semiconductor substrate, the semiconductor substrate include the areas PMOS, and the first fin is formed on the substrate in the areas PMOS
Structure；
It is formed in the first stressor layers of the source/drain region of first fin structure；
Cover the first cap layer of first stressor layers；
Cover the interlayer dielectric layer of first cap layer；
The the first contact hole opening being formed in the interlayer dielectric layer and the first cap layer, the first contact hole opening
Exposure first stressor layers；
It is formed in the metal silicide contacted in the first contact hole opening and with first stressor layers；
Fill the conductive layer of the first contact hole opening.
Illustratively, first stressor layers are SiGe layer.
Illustratively, the content of Ge is 5%-50% in first stressor layers.
Illustratively, first stressor layers are also doped with B ions.
Illustratively, the doping concentration of the B in first stressor layers is less than 1E22cm-3。
Illustratively, doped with B ions in first cap layer.
Illustratively, the content of the B element is not less than 1E21cm-3。
Illustratively, also doped with Ge ions in first cap layer.
Illustratively, the semiconductor substrate further includes NMOS area, and the second fin is formed on the substrate of the NMOS area
Structure；The source/drain region of second fin structure is formed with the second stressor layers；Second is covered in second stressor layers to answer
Second cap layer of power layer；It is covered with interlayer dielectric layer in second cap layer；The interlayer dielectric layer and second lid
The second contact hole opening of exposure second stressor layers is formed in cap layers；Second contact hole is formed in being open and institute
State the metal silicide of the second stressor layers contact；It is also filled with filling conductive layer in the second contact hole opening.
The manufacturing method of semiconductor devices provided by the invention, since the etching of the first contact hole opening opens the first lid
Cap layers, and stop in the first stressor layers, so that metal silicide is contacted with the first stressor layers, therefore advantageously reduce Schottky gesture
It builds, to reduce the contact resistance in the areas PMOS between metal silicide and source-drain area, improves the performance of semiconductor devices.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 shows the process flow chart of the manufacturing method of semiconductor devices provided by one embodiment of the present invention.
Fig. 2A -2P show for the device that is obtained respectively the step of implementation successively according to the method for one embodiment of the invention
Meaning property sectional view.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the areas Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention further includes making
With the different orientation with the device in operation.For example, if the device in attached drawing is overturn, then, it is described as " under other elements
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related Listed Items and institute
There is combination.
It describes to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the variation of shown shape.Therefore,
The embodiment of the present invention should not necessarily be limited to the specific shape in area shown here, but include due to for example manufacturing caused shape
Shape deviation.For example, be shown as the injection region of rectangle its edge usually there is circle or bending features and/or implantation concentration ladder
Degree, rather than the binary from injection region to non-injection regions changes.Equally, the disposal area can be led to by injecting the disposal area formed
Some injections in area between the surface passed through when injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed structure will be proposed in following description, to illustrate proposition of the present invention
Technical solution.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can be with
With other embodiment.
With the continuous diminution of transistor feature size and the continuous increase of integrated circuit level, the outside of transistor is posted
Raw resistance (parasitic external resistance, abbreviation Rext) becomes limit transistor and performance of integrated circuits
Principal element.In the resistance components of composition Rext, the contact resistance (Rc) of regions and source/drain is due to metal/semiconductor
The diminution of contact area and increase so that contact resistance becomes the chief component of ectoparasitism resistance.In 14nm and its
When with lower node, Rext can significantly reduce the performance of semiconductor devices, except non-source, the ohmic contact resistance in the region (S/D) that drains
(Specific Contact Resistivity, ρ c) reduces.
Ohmic contact resistance can be defined by following equations：
Wherein, ρcIndicate contact resistivity (the silicide/Si contact of metal silicide/Si
Resisitivity), φBnIndicate schottky barrier height (the Schottky barrier height), NDIndicate that N-shaped is miscellaneous
Matter doping concentration (n-type doping concentration), εrIndicate relative dielectric constant (the relative
Permittivity), m* indicates electron effective mass (effective mass of electrons),Indicate reduced Planck
Constant (Planck ' s constant), q indicate electron charge (elctronic charge).It is dropped it can be seen from above-mentioned formula
Low Schottky barrier height is one of the effective ways for reducing contact resistance.
In addition, most metals material can cause fermi level pinning (FLP) effect at the intermediate forbidden band close to silicon,
So that schottky barrier height is very big, to ρcIt adversely affects, due to fermi level pinning (FLP) effect, makes into one
Step reduces schottky barrier height φ Bn and becomes more difficult.
In view of the above-mentioned problems, the present invention provides a kind of manufacturing method of semiconductor devices, including：Semiconductor substrate is provided,
The semiconductor substrate includes the areas PMOS, and the first fin structure is formed on the substrate in the areas PMOS；In first fin
The source/drain region of structure forms the first stressor layers；Form the first cap layer for covering first stressor layers；Described in deposition covering
The interlayer dielectric layer of first cap layer；Etching is executed, to form the first contact hole opening, first contact in the areas PMOS
Hole opening exposes first stressor layers；The metal contacted with first stressor layers is formed in first contact hole opening
Silicide；Conductive layer is filled in first contact hole opening.
First stressor layers are SiGe layer.The content of Ge is 5%-50% in first stressor layers.Described first answers
Power layer is also doped with B ions.The doping concentration of B in first stressor layers is less than 1E22cm-3。
Doped with B ions in first cap layer.The doping concentration of the B is not less than 1E21cm-3.First block
Also doped with Ge ions in layer.
The semiconductor substrate further includes NMOS area, and the second fin structure is formed on the substrate of the NMOS area, described
Manufacturing method further includes：The second stressor layers are formed in the source/drain region of second fin structure；Form covering described second
Second cap layer of stressor layers, the interlayer dielectric layer cover second cap layer；Etching is executed, in the interlayer dielectric
The second contact hole opening is formed in layer and second cap layer, the second contact hole opening exposes second stressor layers；
The metal silicide contacted with second stressor layers is formed in second contact hole opening；It is opened in second contact hole
Conductive layer is filled in mouthful.Second stressor layers are SiP layers.
The manufacturing method of semiconductor devices provided by the invention, since the etching of the first contact hole opening opens the first lid
Cap layers, and stop in the first stressor layers, so that metal silicide is contacted with the first stressor layers, therefore advantageously reduce Schottky gesture
It builds, to reduce the contact resistance in the areas PMOS between metal silicide and source-drain area, improves the performance of semiconductor devices.
In order to thoroughly understand the present invention, detailed structure and/or step will be proposed in following description, to illustrate this
Invent the technical solution proposed.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this hair
It is bright to have other embodiment.
[exemplary embodiment one]
Below with reference to Fig. 1 and Fig. 2A~Fig. 2 P, to the manufacturing method of the semiconductor devices of an embodiment of the present invention
It is described in detail.
First, it executes step 101 and provides semiconductor substrate 200 as shown in Figure 2 A, the semiconductor substrate includes PMOS
Area 201 is formed with the first fin structure 203a on the substrate in the areas PMOS 201.
Specifically, the semiconductor substrate 200 can be following at least one of the material being previously mentioned：Silicon, insulator
Silicon (SSOI), stacking SiGe (S-SiGeOI), germanium on insulator SiClx on insulator are laminated on upper silicon (SOI), insulator
(SiGeOI) and germanium on insulator (GeOI) etc..
In the present embodiment, the semiconductor substrate 200 includes the areas PMOS 201 and NMOS area 202, in the areas PMOS
201 and the NMOS area 202 in be respectively formed with the first fin structure 203a and the second fin structure 203b.Fin structure it
Between be also formed with isolation structure 204, the top surface of the isolation structure 204 is less than the top surface of described fin structure 203a, 203b, institute
It is its effective height to state the height that the first fin structure 203a and the second fin structure 203b is exposed to other than isolation structure 204.
Further, various well regions are formed in the semiconductor substrate 200, for example, being formed with P in NMOS area 202
Type well region (PW) is formed with N-type well region (NW) in the areas PMOS 201, wherein can be formed by the method for ion implanting each
Well region, the ionic species and method for implanting of injection can be method commonly used in the art, not repeat one by one herein.
Specifically, the forming method of the first fin structure 203a and the second fin structure 203b are not limited to a certain
Kind, a kind of illustrative forming method is given below：Hard mask layer is formed on semiconductor substrate 200, forms the hard mask
The various suitable techniques that those skilled in the art are familiar with, such as chemical vapor deposition method may be used in layer, described to cover firmly
Film layer can be the oxide skin(coating) and silicon nitride layer that are laminated from bottom to top, and in the present embodiment, hard mask layer is preferably silicon nitride
Layer；It patterns the hard mask layer, is formed for etch semiconductor substrates and multiple to be isolated from each other be formed on fin
Mask, in one embodiment, using patterning process described in self-aligned double patterning case (SADP) process implementing；Etching semiconductor serves as a contrast
Bottom 200 is to be formed on the first fin structure 203a and the second fin structure 203b.
Then, depositing isolation material layer, to be filled up completely between the first fin structure 203a and the second fin structure 203b
Gap.The spacer material layer can be any insulating materials with buffer action, such as silica, silicon oxynitride
(SiON) etc..Any deposition method well known to those skilled in the art may be used and form the spacer material layer, including is but unlimited
In chemical vapour deposition technique, physical vaporous deposition or atomic layer deposition method etc..In the present embodiment, preferably using has and can flow
It is deposited described in chemical vapor deposition (FCVD) process implementing of dynamic property.
Then, the surface of spacer material layer is planarized, which is, for example, chemical mechanical grinding (CMP) work
Skill.Then, it is etched back to the spacer material layer, to expose the fin of object height, to form final isolation structure 204,
The top surface of the isolation structure 204 is less than the top surface of the first fin structure 203a and the second fin structure 203b.Described time quarter
Etching method can select dry etching or wet etching, it is not limited to a certain.
Then, the gate structure for being developed across the first fin structure 203a and the second fin structure 203b (is not schemed
Show).
Specifically, the gate structure includes gate dielectric and gate electrode from bottom to top.Gate dielectric can be with
Including traditional dielectric substance such as with electric medium constant from the oxidation of the silicon of about 4 to about 20 (true aerial surveties)
Object, nitride and nitrogen oxides.Alternatively, gate dielectric may include with electric medium constant from about 20 at least about
100 it is usual compared with high dielectric constant dielectric substance.It is this compared with high dielectric constant electrolyte to may include but unlimited
In：Hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate and lead zirconate titanate.The material of suitable gate dielectric composition of layer may be used
Any type of several methods forms gate dielectric.It is included but unrestricted have heat or plasma oxidation or nitridation side
Method, process for chemical vapor deposition of materials and physical vapor deposition methods.In general, gate dielectric includes having thickness from about 5 to big
About 70 angstroms of thermal oxidation silicon dielectric substance.
The material of gate electrode including but not limited to：Certain metals, metal alloy, metal nitride and metal silicide,
And its laminate and its compound.Gate electrode can also include doping polysilicon and polysilicon-Ge alloy material and
Polycide material etc..Similarly, any one formation previous materials of several methods can also be used.It is unrestricted
Property example includes self-aligned metal silicate method, process for chemical vapor deposition of materials and physical vapor deposition methods, such as but unlimited
In：Method of evaporating and sputtering method.In general, gate electrode include have from about 50 to about 2000 angstroms of thickness doping it is more
Crystal silicon material.
In one example, the step of formation gate structure includes：The grid of covering semiconductor substrate is sequentially formed first
Dielectric layer and grid electrode layer are formed on the surface of the semiconductor substrate by photoetching process and etching extend simultaneously cross later
Across the gate structure of the first fin structure 203a and the second fin structure 203b.
Later, also optionally, offset side wall (not shown) is formed on the side wall of gate structure.Specifically, described
Offset side wall can be a kind of in silica, silicon nitride, silicon oxynitride or they combine and constitute.In the one of the present embodiment
Embodiment, the offset side wall is silica, silicon nitride collectively constitutes, and concrete technology is：Is formed on a semiconductor substrate
Then one silica layer, the first silicon nitride layer and the second silicon oxide layer use lithographic method to form offset side wall.It can also be
The top surface of dummy gate structure and side wall are respectively formed on spacer material layer, in the steps afterwards by the method for planarization, such as
Chemical mechanical grinding removes the spacer material layer on top surface, forms the offset side wall being located only on side wall.
Then, to the first fin structure 203a and the second fin structure 203b carry out respectively LDD ion implantings and
Halo ion implantings.Later, it is made annealing treatment accordingly, the two of the gate structure of the first fin 203a and the second fin 203b
Side is respectively formed LDD ion implanted regions and Halo ion implanted regions.Wherein, LDD ion implantings are lightly doped with being formed in source/drain region
(LDD) structure is leaked, electric field can be reduced, and thermoelectronic effect can be significantly improved；Halo ion implantings can prevent source and drain phase
Logical and shortening channel length.
Then, the first gap wall layer 205 for covering the areas PMOS 201 and the NMOS area 202 is formed.
Specifically, the first gap wall layer 205 be formed on the surface of the isolation structure 204 of exposing, the gate structure
On top surface and side wall and on the side wall and top surface of the first fin structure 203a and the second fin structure 203b.First clearance wall
Layer 205 can be a kind of in silica, silicon nitride, silicon oxynitride or they combine and constitute.A kind of reality as the present embodiment
Mode is applied, first gap wall layer 205 includes the first clearance wall silicon oxide layer 205a and the first clearance wall nitrogen sequentially formed
SiClx layer 205b.
Then, step 102 is executed, the first stressor layers are formed in the source/drain region of first fin structure.
First, as shown in Figure 2 B, patterned first photoresist layer 206 is formed, to cover the NMOS area 202, is exposed
The areas PMOS 201.
Specifically, to form this using photoetching process (including coating the processes such as photoresist and exposure imaging) patterned
First photoresist layer 206, patterned first photoresist layer 206 expose the first gap wall layer 205 in the areas PMOS 202.
Then, it is mask with patterned first photoresist layer 206, gate structure two is reduced at the top of the first fin structure 203a
The height of first fin structure 203a of side is to preset height.In the present embodiment, the first fin of part is removed using dry etching
Structure 203a and the first gap wall layer 205, the height of the second fin structure 203b and the first gap wall layer 205 are reduced to pre-
If height.Later, the methods of ashing can be used to remove first photoresist layer 206.
Then, as shown in Figure 2 C, it is located in the source/drain region of gate structure both sides in the first fin structure 203a and grows
First stressor layers 207.
Form the stressor layers with compression in PMOS, the performance of cmos device can by by action of compressive stress in
PMOS is improved.Wherein, the cross sectional shape of the first stressor layers 207 is preferably " ∑ " shape.Selective epitaxial growth can be used
Method on the surface of the second fin structure 203b of exposing one stressor layers 207 of growth regulation, selective epitaxial growth can adopt
It is heavy with low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultrahigh vacuum chemical vapor
One kind in product (UHVCVD), rapid thermal CVD (RTCVD) and molecular beam epitaxy (MBE).
In the present embodiment, the material of the first stressor layers 207 is preferably SiGe.Illustratively, in first in source/drain region
Epitaxial growth SiGe seed layers.The lattice constant of the lower SiGe seed layers of Ge contents closer to silicon in substrate lattice constant,
The alternatively buffer layer during the higher SiGe epitaxial layers of property epitaxial growth Ge contents, is conducive to the SiGe for obtaining high quality
Epitaxial layer.Then, epitaxial growth SiGe body layers on the seed layer, the concentration containing Ge in SiGe body layers are higher than seed layer.Compared with
Goodly, also doped with B element in the body layer.In the body layer, Ge constituent contents are gradually increased to 50%, then by
It is gradually reduced to 5%, B element content is gradually increased to 1E22cm-3。
Specifically, chemical vapor deposition method or gas source molecular beam epitaxy method growth SiGe can be used, use silane
Or disilane is as silicon source, while a certain amount of germane is added, to form SiGe epitaxial layers.Ion implantation technology may be used
Boron is adulterated in sige, that is, after being epitaxially-formed SiGe layer, ion implanting is carried out to SiGe layer and forms boron doped SiGe layer,
But the method for forming boron doped SiGe layer is not limited to this, and can also be carried out using boron while epitaxial growth SiGe layer
Doping in situ forms boron doped SiGe layer according to doping in situ, then can also include gas B in process gas2H6Or
BH3.For example, selecting GeH4And SiH2Cl2As reaction gas, and select H2As carrier gas, and gas B is added2H6Or BH3It carries out
Reaction, the wherein flow-rate ratio of reaction gas and carrier gas are 0.01-0.1, and the temperature of deposition is 300-1000 DEG C, preferably 650-
750 DEG C, gas pressure 1-50Torr, preferably 20-40Torr.
Then, step 103 is executed, the first cap layer for covering first stressor layers is formed.
As shown in Figure 2 D, the first cap layer 208 is formed in first stressor layers 207.In the present embodiment, described
Ge constituent contents are relatively low in one cap layer 208, and B element content is higher.Doping B element dissolving in Si can reduce source, drain electrode
The resistance in region.Specifically, one layer of Si cap layer of epitaxial growth (Si cap) in first stressor layers 207, wherein first
The material of cap layer 208 includes but not limited to SiB, SiGe, SiGeB, SiC, SiCB etc..Illustratively, first cap layer
B element content is 1E21cm in 208-3, Ge constituent contents are less than 5%.
In the present embodiment, further include forming the second stressor layers in NMOS area 202.
First, as shown in Figure 2 E, the second spacer material layer 209 is deposited, to cover the areas PMOS 201.Second gap
The wall material bed of material 209 can use material identical with the first spacer material layer 205 above-mentioned, for example, silica, silicon nitride,
A kind of or their combinations are constituted in silicon oxynitride.As an embodiment of the present embodiment, the second spacer material layer 209
For silicon nitride.It can use and include but not limited to：The method of chemical vapor deposition method and physical gas-phase deposite method forms the
Two spacer material layers 209.Specifically, in the areas PMOS 201, the second spacer material layer 209 covers first cap layer
208 surface, and be respectively formed on the surface of isolation structure 204 on the side wall of the first fin structure 203a in the areas PMOS 201
Second spacer material layer 209.
Then, as shown in Figure 2 F, patterned second photoresist layer 210 is formed, to cover the areas PMOS 201, exposure
The NMOS area 202.Specifically, the figure is formed using photoetching process (including coating photoresist and exposure imaging etc. processes)
Second photoresist layer 210 of case, patterned second photoresist layer 210 expose the NMOS area.
Then, it is mask with patterned second photoresist layer 210, etching removes at the top of the second fin structure 203b
And the first spacer material layer on the isolation structure in NMOS area 202, with the second fin structure 203b's
Clearance wall is formed on side wall.The method of etching can use any suitable dry etching well known to those skilled in the art or
The methods of wet etching, preferably, using the method for dry etching.
Then, it is mask with patterned second photoresist layer 210, to exposed the second fin structure 203b's
Source/drain region is etched back, to remove part the second fin structure 203b.It is described to be etched back to that art technology is used
Any suitable dry etching or the methods of wet etching or combination thereof known to personnel.Preferably, using each to different
The dry etching method of property, dry etch process include but not limited to：Reactive ion etching (RIE), ion beam etching, plasma
Body etches or laser cutting.Dry etching is carried out preferably by one or more RIE step.Illustratively, described time quarter
The depth bounds of erosion are 20~40nm, namely the depth bounds being etched back to downwards since the top surface of the second fin structure 203b are
20~40nm, the depth bounds are only used as example.
Later, patterned second photoresist layer 210 is removed.The method removal figure of ashing can be used
Second photoresist layer 210 of case.
Then, as shown in Figure 2 G, two stress of growth regulation on the second fin structure 203b exposed in the groove
Layer 211.Can use selective epitaxial growth method on the surface of the second fin structure 203b of exposing growth regulation two answer
Power layer 211, it is heavy that low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor may be used in selective epitaxial growth
Product (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecular beam epitaxy
(MBE) one kind in.
In NMOS device, the second stressor layers 211 should have tensile stress.The material of second stressor layers 211 can be SiP,
SiC or other the suitable material of tensile stress can be provided.In the present embodiment, preferably select SiP as the second stressor layers 211,
Wherein P content is 1E22cm-3.Specifically, chemical vapor deposition method or the growth of gas source molecular beam epitaxy method can be used
SiP uses silane or disilane as silicon source, and phosphine is as phosphorus source.The table that also optionally the second stressor layers 211 are exposed
Face carries out oxidation processes, to form oxide skin(coating).
Then, as illustrated in figure 2h, the second cap layer 212 is formed in second stressor layers 211.In the present embodiment,
Ge constituent contents are higher in second cap layer 212.Specifically, one layer of Si of epitaxial growth in second stressor layers 211
Cap layer (Si cap).Illustratively, P element content is 1E21cm in second cap layer 212-3。
Then, as shown in figure 2i, the second gap wall layer 209 is removed.It can use well known to those skilled in the art any
The methods of suitable dry etching or wet etching remove second gap wall layer 209.
Then, step 104 is executed, the interlayer dielectric layer for covering first cap layer is formed.
Specifically, first, as shown in fig. 2j, contact hole etching stop-layer 213 is formed, to cover first cap layer
208 and second cap layer 212.The contact hole etching stop-layer 213 also covers the first fin structure 203a and the second fin knot
Structure 203b and isolation structure 204.Conformal deposition process may be used and form contact hole etching stop-layer 213, so that is formed connects
Contact hole etching stop layer 213 has good step coverage characteristics, the preferred silicon nitride of material of contact hole etching stop-layer 213.
Then, it interlevel dielectric deposition 214 and planarizes, to fill the gap between each fin structure.The interlayer
Dielectric layer 214 can select dielectric material commonly used in the art, such as various oxides etc., in the present embodiment interlayer dielectric
Layer can select SiO2, thickness is not limited to a certain numerical value.
Then, step 105 is executed, etching is executed, is connect with forming first in the interlayer dielectric layer and the first cap layer
Contact hole is open, and the first contact hole opening exposes first stressor layers.In the present embodiment, as shown in figure 2k, quarter is executed
Erosion, to form the contact hole opening 215a for exposing first stressor layers 207 in the areas PMOS 201, and in the NMOS area
202 form the contact hole opening 215b for exposing second stressor layers 211.
Specifically, the method for formation the first contact hole opening 215a and second contact hole opening 215b include：
Patterned photoresist layer is formed on interlayer dielectric layer 214 first, which defines the first contact hole of predetermined formation
Be open 215a and second contact hole opening 215b positions and dimensions etc., then using the patterned photoresist as mask successively
Interlayer dielectric layer 214, etching stop layer 213 and the first cap layer 208, the second cap layer 211 are etched, stops at described the respectively
In one stressor layers 207 and the second stressor layers 211, to form the first contact hole opening 215a and the second contact hole opening 215b.With
Afterwards, patterned photoresist layer is removed, such as the photoresist layer is removed using the method for ashing.
Then, n-type doping ion implanting is executed to second stressor layers 211.
In one example, as shown in figure 2l, it is initially formed patterned photoresist layer 216, to cover the areas PMOS
201.It is mask with the patterned photoresist layer 216, to described the exposed in 215b that be open from second contact hole
Two stressor layers 211 execute n-type doping ion implanting, and to form injection region in second stressor layers 211, injection ion can
Think any suitable n-type doping ion, including but not limited to phosphorus (P) ion, arsenic (As) ion.Specifically, the first ion is noted
The energy and dopant dose entered can need to reasonably select according to actual process, be not specifically limited herein.Oxygen can be passed through later
The common process such as gas plasma ashing remove the photoresist layer 216.Source and drain ion implanting is carried out to the second stressor layers 211,
Source and drain ion can be made to be on the non-proxy position in 211 lattice of the first stressor layers, in subsequent anneal processing procedure, the source and drain from
Son is activated, and occupies the lattice of the second stressor layers 211.Because of the contact resistance of the second stressor layers 211 and incorporation source and drain ion
Dosage is inversely proportional, so the larger source and drain ion of implantation dosage in the second stressor layers, can further decrease the second stressor layers
211 contact resistance.
Then, the injection of p-type Doped ions is executed to first stressor layers 207.
In one example, as shown in figure 2m, it is initially formed patterned photoresist layer 217, to cover the NMOS area
202.It is mask with the patterned photoresist layer 217, to described the exposed in 215a that be open from first contact hole
One stressor layers 207 execute the injection of p-type Doped ions, and to form injection region in first stressor layers 207, injection ion can
Think any suitable p-type Doped ions, including but not limited to boron (B) ion, indium (In) ion.The p-type ion implanting
Energy and dopant dose can need to reasonably select according to actual process, be not specifically limited herein.Oxygen etc. can be passed through later
The common process such as ion ashing remove the photoresist layer 217.Source and drain ion implanting is carried out to the first stressor layers 207, it can be with
Source and drain ion is set to be on the non-proxy position in 211 lattice of the first stressor layers, in subsequent anneal processing procedure, the source and drain ion quilt
Activation, occupies the lattice of the first stressor layers 207.Because of the dosage of the contact resistance of the first stressor layers 207 and incorporation source and drain ion
It is inversely proportional, so the larger source and drain ion of implantation dosage in the first stressor layers, can further decrease the first stressor layers 207
Contact resistance.
It is noted that for above-mentioned steps, can also p-type ion implanting be carried out to the areas PMOS first, then to NMOS
Device carries out N-type ion implanting, similarly can realize the present invention.
Then, as shown in figure 2n, annealing process is executed, to activate the n-type doping ion and p-type Doped ions.This is moved back
Fire processing can be peak value anneal (spike anneal) technique, the annealing region that the peak value annealing process uses for
500~1050 DEG C, annealing time is 10s~60min, specifically can suitably be adjusted according to actual process.The annealing steps
Usually the substrate is placed under the protection of high vacuum or high-purity gas, is heated to certain temperature and carries out, annealing steps are high
Temperature carrys out the p-type Doped ions and n-type doping ion adulterated in Activation Activation source region and drain region.
Annealing process step in the present invention can also select one kind in following methods：Furnace anneal, pulse
Laser short annealing, pulsed electron beam short annealing, ion beam short annealing, continuous wave laser short annealing and incoherent width
Band light source (such as halogen lamp, arc lamp, graphite heating) short annealing, but it is not limited to examples cited.
Then, step 106 is executed, the metal contacted with first stressor layers is formed in first contact hole opening
Silicide.
In the present embodiment, as shown in Figure 2 O, in first contact hole opening 215a, second contact hole opening
Metal silicide 218 is formed in 215b.
Specifically, first, in the bottom and side of first contact hole opening 215a, second contact hole opening 215b
Metal layer is formed on wall.The material of the metal layer can use titanium (Ti), nickeliferous (nickel), cobalt (cobalt) and platinum
(platinum) or combinations thereof material.It can deposit to form institute using any suitable method well known to those skilled in the art
State metal layer, including but not limited to chemical vapor deposition method or physical gas-phase deposite method etc..
Then, coating (not shown) is formed on the metal layer.Physics can be selected in the preparation method of the coating
Be vapor-deposited (PVD), coating can between -40 DEG C~400 DEG C temperature with about between 0.1 millitorr (mTorr)~100 millitorr
(mTorr) it is formed under pressure.Covering layer material is material such as tantalum, tantalum nitride, titanium, the nitridation of metal or metal compound layer
Titanium, zirconium nitride, titanium nitride zirconium, tungsten, tungsten nitride, its alloy or its constituent.In addition, diffusion impervious layer also may include multiple films
Layer, in the present embodiment, the coating includes TiN layer.
Then, annealing steps are carried out.The annealing steps can use any suitable method for annealing, such as furnace anneal,
Laser short annealing, pulsed electron beam short annealing, ion beam short annealing, continuous wave laser short annealing and incoherent width
Band light source (such as halogen lamp, arc lamp, graphite heating) short annealing.In the present embodiment, preferably, annealing uses laser annealing
(laser anneal).Wherein, the temperature range of annealing can be 800~1100 DEG C, preferably, the temperature of annealing is 900 DEG C.
Annealing time can be any suitable time, for example, annealing time may range from the 400 μ s of μ s~800, the annealing time
Use the residence time (Dwell time) when laser annealing.In the annealing process of this step, make contact hole open bottom
The metal layer and be in contact with it first stressor layers 207, the first cap layer 208 or the second stressor layers 211, second lid
The reaction of cap layers 212 generates metal silicide layer 218 (for example, TiSi).
In the areas PMOS 201, since the etching of the first contact hole opening 215a opens the first cap layer 208, and stop at
In first stressor layers 207, metal silicide 218 is set to be contacted with the first stressor layers 207, therefore advantageously reduce Schottky barrier,
To reduce the contact resistance in the areas PMOS 201 between metal silicide 218 and source-drain area.
In a particular embodiment, when the first stressor layers 207 are SiGe, band gap ratio Si is small, realizes metal silicide 218
Schottky barrier is reduced in the case of being contacted with the first stressor layers 207.In addition, when the B content of the first cap layer 208 is higher,
This advantageously reduces resistance, mitigates current-crowding effect, is equally beneficial for reducing contact resistance.
Later, step 107 is executed, conductive layer is filled in first contact hole opening.
As shown in figure 2p, the conductive layer for filling the first contact hole opening 215a, the second contact hole opening 215b is formed
219.Specifically, conductive layer can be deposited to fill the first contact hole opening 215a, the second contact hole opening 215b, and carried out
Planarization, to be respectively formed the first contact hole, the second contact hole.
Wherein, conductive layer 219 can be any suitable conductive material well known to those skilled in the art, including but unlimited
Metal material.Preferably, conductive layer is tungsten material.In another embodiment, conductive layer can be cobalt (Co), molybdenum (Mo), titanium nitride
(TiN) and the conductive material or combinations thereof containing tungsten.
Can have by low-pressure chemical vapor deposition (LPCVD), plasma auxiliary chemical vapor deposition (PECVD), metal
Chemical machine vapor deposition (MOCVD) and atomic layer deposition (ALD) or other advanced deposition techniques form conductive layer.
The non-limiting examples of the planarization process include mechanical planarization method and chemically mechanical polishing planarization side
Method.The planarization stops on the surface of the interlayer dielectric layer 214.
So far, the introduction of the correlation step of the manufacturing method of the semiconductor devices of the embodiment of the present invention is completed.It can manage
Solution, the present embodiment method, semi-conductor device manufacturing method not only include above-mentioned steps, before above-mentioned steps, among or later also
It may include other desired step, be included in the range of this implementation manufacturing method.
The manufacturing method of semiconductor devices provided by the invention, since the etching of the first contact hole opening opens the first lid
Cap layers, and stop in the first stressor layers, so that metal silicide is contacted with the first stressor layers, therefore advantageously reduce Schottky gesture
It builds, to reduce the contact resistance in the areas PMOS between metal silicide and source-drain area, improves the performance of semiconductor devices.
[exemplary embodiment two]
The present invention also provides a kind of semiconductor devices.As shown in figure 2p, the semiconductor devices includes semiconductor substrate
200, the semiconductor substrate includes the areas PMOS 201, and the first fin structure 203a is formed on the substrate in the areas PMOS 201.
Specifically, the semiconductor substrate 200 can be following at least one of the material being previously mentioned：Silicon, insulator
Silicon (SSOI), stacking SiGe (S-SiGeOI), germanium on insulator SiClx on insulator are laminated on upper silicon (SOI), insulator
(SiGeOI) and germanium on insulator (GeOI) etc..
In the present embodiment, the semiconductor substrate 200 includes the areas PMOS 201 and NMOS area 202, in the areas PMOS
201 and the NMOS area 202 in be respectively formed with the first fin structure 203a and the second fin structure 203b.Fin structure it
Between be also formed with isolation structure 204, the top surface of the isolation structure 204 is less than the top surface of described fin structure 203a, 203b, institute
It is its effective height to state the height that the first fin structure 203a and the second fin structure 203b is exposed to other than isolation structure 204.
Further, various well regions are formed in the semiconductor substrate 200, for example, being formed with P in NMOS area 202
Type well region (PW) is formed with N-type well region (NW) in the areas PMOS 201, wherein can be formed by the method for ion implanting each
Well region, the ionic species and method for implanting of injection can be method commonly used in the art, not repeat one by one herein.
The semiconductor devices further includes the grid across the first fin structure 203a and the second fin structure 203b
Structure (not shown).Specifically, the gate structure includes gate dielectric and gate electrode from bottom to top.Gate dielectric
May include the oxygen of the silicon of traditional dielectric substance such as with electric medium constant from about 4 to about 20 (true aerial surveties)
Compound, nitride and nitrogen oxides.Alternatively, gate dielectric may include with electric medium constant from about 20 at least about
100 it is usual compared with high dielectric constant dielectric substance.It is this compared with high dielectric constant electrolyte to may include but unlimited
In：Hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate and lead zirconate titanate.The material of suitable gate dielectric composition of layer may be used
Any type of several methods forms gate dielectric.It is included but unrestricted have heat or plasma oxidation or nitridation side
Method, process for chemical vapor deposition of materials and physical vapor deposition methods.In general, gate dielectric includes having thickness from about 5 to big
About 70 angstroms of thermal oxidation silicon dielectric substance.
The material of gate electrode including but not limited to：Certain metals, metal alloy, metal nitride and metal silicide,
And its laminate and its compound.Gate electrode can also include doping polysilicon and polysilicon-Ge alloy material and
Polycide material etc..Similarly, any one formation previous materials of several methods can also be used.It is unrestricted
Property example includes self-aligned metal silicate method, process for chemical vapor deposition of materials and physical vapor deposition methods, such as but unlimited
In：Method of evaporating and sputtering method.In general, gate electrode include have from about 50 to about 2000 angstroms of thickness doping it is more
Crystal silicon material.
Illustratively, offset side wall (not shown) is formed on the side wall of gate structure.Specifically, the offset side wall
Can be a kind of in silica, silicon nitride, silicon oxynitride or their combination compositions.First fin 203a and the second fin 203b
The both sides of gate structure be also respectively formed with LDD ion implanted regions and Halo ion implanted regions.
The semiconductor devices further includes the first gap wall layer for covering the areas PMOS 201 and the NMOS area 202
205.Specifically, the first gap wall layer 205 be formed on the surface of the isolation structure 204 of exposing, the top surface of the gate structure
With on side wall and on the side wall and top surface of the first fin structure 203a and the second fin structure 203b.First gap wall layer 205
Can be a kind of in silica, silicon nitride, silicon oxynitride or their combination compositions.A kind of embodiment party as the present embodiment
Formula, first gap wall layer 205 include the first clearance wall silicon oxide layer 205a and the first clearance wall silicon nitride layer 205b.
The first stressor layers 207 are formed in the source/drain region of first fin structure.Wherein, the first stressor layers 207
Cross sectional shape be preferably " ∑ " shape.In the present embodiment, the material of the first stressor layers 207 is preferably SiGe.Illustratively,
In the SiGe layer, Ge constituent contents are gradually increased to 50% from the bottom to top, are then gradually decrease to 5%, B element content is gradual
Increase to 1E22cm-3。
The first cap layer 208 is formed in first stressor layers 207.In the present embodiment, first cap layer 208
Middle Ge constituent contents are relatively low, and B element content is higher.Doping B element dissolves in the resistance that can reduce source, drain region in Si.
Wherein, the material of the first cap layer 208 includes but not limited to SiB, SiGe, SiGeB, SiC, SiCB etc..Illustratively, described
B element content is 1E21cm in one cap layer 208-3, Ge constituent contents are less than 5%.
In the present embodiment, the semiconductor devices further includes the second stressor layers 211 for being formed in NMOS area 202.
In NMOS device, the second stressor layers 211 should have tensile stress.The material of second stressor layers 211 can be SiP, SiC or other can
The suitable material of tensile stress is provided.In the present embodiment, preferably select SiP as the second stressor layers 211, wherein P content is
1E22cm-3.The second cap layer 212 is formed in second stressor layers 211.In the present embodiment, second cap layer
Ge constituent contents are higher in 212.Illustratively, P element content is 1E21cm in the cap layer 208-3。
It is covered with interlayer dielectric layer in first cap layer.In the present embodiment, first cap layer 208 and
It is covered with contact hole etching stop-layer 213 in two cap layers 212.The contact hole etching stop-layer 213 also covers the first fin
The side wall and isolation structure 204 of structure 203a and the second fin structure 203b.The preferred nitrogen of material of contact hole etching stop-layer 213
SiClx.It is formed with interlayer dielectric layer 214 on the contact hole etching stop-layer 213.The interlayer dielectric layer 214 also fills up respectively
Gap between a fin structure.The interlayer dielectric layer 214 can select dielectric material commonly used in the art, such as various
Oxide etc., in the present embodiment interlayer dielectric layer can select SiO2, thickness is not limited to a certain numerical value.
The first contact hole opening, the first contact hole opening exposure first stressor layers are formed in the areas PMOS
207.In the present embodiment, the contact hole opening of exposed second stressor layers 211 is formed in the NMOS area 202.
It is formed with metal silicide 218 in first contact hole opening.In the present embodiment, in first contact hole
Forming metal layer in opening, the bottom and side wall of second contact hole opening has metal silicide layer 218 (for example, TiSi).
In the areas PMOS 201 Schottky is advantageously reduced since metal silicide 218 is contacted with the first stressor layers 207
Potential barrier, to reduce the contact resistance in the areas PMOS 201 between metal silicide 218 and source-drain area.
It is filled with conductive layer 219 in the first contact hole opening 215a, the second contact hole opening 215b.Conductive layer 219
Can be any suitable conductive material well known to those skilled in the art, including but unlimited metal material.Preferably, conductive layer
For tungsten material.In another embodiment, conductive layer can be cobalt (Co), molybdenum (Mo), titanium nitride (TiN) and the conduction material containing tungsten
Material or combinations thereof.
Semiconductor devices provided by the invention is advantageously reduced since metal silicide is contacted with the first stressor layers
Schottky barrier improves semiconductor devices to reduce the contact resistance in the areas PMOS between metal silicide and source-drain area
Performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (19)
1. a kind of manufacturing method of semiconductor devices, which is characterized in that the method includes：
Semiconductor substrate is provided, the semiconductor substrate includes the areas PMOS, and the first fin is formed on the substrate in the areas PMOS
Structure；
The first stressor layers are formed in the source/drain region of first fin structure；
Form the first cap layer for covering first stressor layers；
Form the interlayer dielectric layer for covering first cap layer；
Etching is executed, to form the first contact hole opening, first contact in the interlayer dielectric layer and the first cap layer
Hole opening exposes first stressor layers；
The metal silicide contacted with first stressor layers is formed in first contact hole opening；
Conductive layer is filled in first contact hole opening.
2. manufacturing method according to claim 1, which is characterized in that first stressor layers are SiGe layer.
3. manufacturing method according to claim 2, which is characterized in that the content of Ge is 5%- in first stressor layers
50%.
4. manufacturing method according to claim 2, which is characterized in that first stressor layers are also doped with B ions.
5. manufacturing method according to claim 4, which is characterized in that the doping concentration of the B in first stressor layers is small
In 1E22cm-3。
6. manufacturing method according to claim 1, which is characterized in that doped with B ions in first cap layer.
7. manufacturing method according to claim 6, which is characterized in that the doping concentration of the B is not less than 1E21cm-3。
8. manufacturing method according to claim 6, which is characterized in that also doped with Ge ions in first cap layer.
9. manufacturing method according to claim 1, which is characterized in that the semiconductor substrate further includes NMOS area, described
The second fin structure is formed on the substrate of NMOS area, the manufacturing method further includes：
The second stressor layers are formed in the source/drain region of second fin structure；
The second cap layer for covering second stressor layers is formed, the interlayer dielectric layer covers second cap layer；
Etching is executed, to form the second contact hole opening, second contact in the interlayer dielectric layer and the second cap layer
Hole opening exposes second stressor layers；
The metal silicide contacted with second stressor layers is formed in second contact hole opening；
Conductive layer is filled in second contact hole opening.
10. manufacturing method according to claim 9, which is characterized in that second stressor layers are SiP layers.
11. a kind of semiconductor devices, which is characterized in that including：
Semiconductor substrate, the semiconductor substrate include the areas PMOS, and the first fin structure is formed on the substrate in the areas PMOS；
It is formed in the first stressor layers of the source/drain region of first fin structure；
Cover the first cap layer of first stressor layers；
Cover the interlayer dielectric layer of first cap layer；
The the first contact hole opening being formed in the interlayer dielectric layer and the first cap layer, the first contact hole opening exposure
First stressor layers；
It is formed in the metal silicide contacted in the first contact hole opening and with first stressor layers；
Fill the conductive layer of the first contact hole opening.
12. semiconductor devices according to claim 11, which is characterized in that first stressor layers are SiGe layer.
13. semiconductor devices according to claim 12, which is characterized in that the content of Ge is in first stressor layers
5%-50%.
14. semiconductor devices according to claim 12, which is characterized in that first stressor layers are also doped with B ions.
15. semiconductor devices according to claim 14, which is characterized in that the doping of the B in first stressor layers is dense
Degree is less than 1E22cm-3。
16. semiconductor devices according to claim 11, which is characterized in that doped with B ions in first cap layer.
17. semiconductor devices according to claim 16, which is characterized in that the content of the B element is not less than 1E21cm-3。
18. semiconductor devices according to claim 16, which is characterized in that in first cap layer also doped with Ge from
Son.
19. semiconductor devices according to claim 11, which is characterized in that the semiconductor substrate further includes NMOS area,
The second fin structure is formed on the substrate of the NMOS area；The source/drain region of second fin structure is formed with second and answers
Power layer；The second cap layer of the second stressor layers is covered in second stressor layers；It is covered with interlayer in second cap layer
Dielectric layer；The second contact hole that exposure second stressor layers are formed in the interlayer dielectric layer and second cap layer is opened
Mouthful；It is formed with the metal silicide contacted with second stressor layers in the second contact hole opening；Second contact hole
Filling conductive layer is also filled in opening.
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