CN113140462B - Manufacturing method of embedded epitaxial layer - Google Patents
Manufacturing method of embedded epitaxial layer Download PDFInfo
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- CN113140462B CN113140462B CN202110330203.7A CN202110330203A CN113140462B CN 113140462 B CN113140462 B CN 113140462B CN 202110330203 A CN202110330203 A CN 202110330203A CN 113140462 B CN113140462 B CN 113140462B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 49
- 239000010703 silicon Substances 0.000 claims abstract description 49
- 238000000034 method Methods 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 11
- 230000007547 defect Effects 0.000 claims abstract description 9
- 238000010030 laminating Methods 0.000 claims abstract 2
- 239000007789 gas Substances 0.000 claims description 53
- 229910052732 germanium Inorganic materials 0.000 claims description 32
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 32
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 20
- 239000011574 phosphorus Substances 0.000 claims description 20
- 229910052698 phosphorus Inorganic materials 0.000 claims description 20
- 239000012159 carrier gas Substances 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 8
- 229910003818 SiH2Cl2 Inorganic materials 0.000 claims description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 6
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 claims description 6
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 claims description 4
- 230000001105 regulatory effect Effects 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052986 germanium hydride Inorganic materials 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention discloses a manufacturing method of an embedded epitaxial layer, which comprises the following steps: etching a silicon substrate to form a groove; filling an embedded epitaxial layer in the groove, wherein the embedded epitaxial layer comprises the following steps: step 21, forming a buffer layer; step 22, forming a main body layer on the surface of the buffer layer; the main body layer is doped in silicon to provide stress for the silicon substrates at two sides of the groove, and the doping concentration of the main body layer is graded doping in the epitaxial growth process so as to eliminate the fault defect and further prevent the main body layer from collapsing; step 23, forming a cap layer, and forming an embedded epitaxial layer by laminating a buffer layer, a main body layer and a cap layer; the material of the buffer layer, the main body layer and the cap layer is the same, and the doping concentration of the buffer layer and the cap layer is less than or equal to the lowest doping concentration of the main body layer. The invention can prevent the main body layer of the embedded epitaxial layer from collapsing, thereby improving the performance and yield of the product.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing an embedded epitaxial layer.
Background
With the development of technology, the Critical Dimension (CD) of the device is smaller and smaller, and when the process node of the device is below 28nm, an embedded epitaxial layer is often required to be adopted in the source-drain region to change the stress of the channel region, so that the mobility of carriers is improved and the performance of the device is improved. For PMOS devices, the embedded epitaxial layer typically employs a silicon germanium epitaxial layer (SiGe); for NMOS devices, a phosphorus silicon epitaxial layer (SiP) is typically used for the embedded epitaxial layer.
Typically, after the gate structure of the device is formed, a recess is first self-aligned on both sides of the gate structure; and then, forming an embedded epitaxial layer in the groove by adopting an epitaxial process in a self-alignment mode.
In the prior art, for a source (source) region and a drain (drain) region of a 14nm PMOS, a U-shaped groove is formed by Dry etching, then an embedded boron-doped germanium-silicon epitaxial layer (SiGeB) is grown in the groove, the SiGeB is divided into three layers, one layer which is closely attached to the inner side surface of the groove is a first layer (L1), and L1 is a buffer layer. After growth as a buffer layer, a bulk layer is grown, followed by a cap layer.
Taking PMOS as an example, in the growth process of the main body layer, the concentration of germanium is a fixed value, and defects are easily generated during growth, so that collapse (DVC defect) occurs in the grown main body layer, the volume of the main body layer after collapse can be reduced, and the stress on the channel region of the device can be reduced, so that the efficiency of the device can be directly affected.
Similarly, the same problems exist for source and drain regions of 14nm NMOS.
The prior art method is described in further detail below with reference to the accompanying drawings:
as shown in fig. 1A to 1D, the structure of the device in each step of the conventional manufacturing method of the embedded epitaxial layer is schematically shown; the existing manufacturing method of the embedded epitaxial layer comprises the following steps:
step one, as shown in fig. 1A, a groove 105 is formed in a silicon substrate 101 by adopting a dry etching process, and the cross section of the groove 105 is in a U-shaped structure.
A gate structure is formed on the silicon substrate 101, and the grooves 105 are formed in the grooves 105 on both sides of the gate structure in a self-aligned manner.
The gate structure includes a gate dielectric layer and a polysilicon gate 102 stacked in sequence.
A top hard mask layer 103 is covered on the top of the polysilicon gate 102, and a side wall 104 is formed on the side surface of the polysilicon gate 102.
Typically, the material of the top hard mask layer 103 comprises silicon oxide or silicon nitride.
The material of the side wall 104 includes silicon oxide or silicon nitride.
And step two, filling an embedded epitaxial layer in the groove 105. Typically, the epitaxial growth process of the embedded epitaxial layer is a selective epitaxial growth process.
The filling process of the embedded epitaxial layer includes three substeps, taking the embedded germanium-silicon epitaxial layer 106 for forming a PMOS as an example, the three substeps are sequentially:
as shown in fig. 1B, the sige buffer layer 106a is formed.
As shown in fig. 1C, the bulk germanium-silicon layer 106b is formed. The germanium concentration of the sige body layer 106b is a fixed value, and defects are easily generated during growth, so that the grown sige body layer 106b collapses as indicated by a broken line circle 107. The volume of the collapsed sige body layer 106b is reduced, so that the stress on the silicon substrate 101 at both sides of the recess 105 is also reduced, and the carrier mobility of the channel region is reduced, thereby reducing the performance of the device.
As shown in fig. 1C, the sige cap layer 106C is formed, and the embedded sige epitaxial layer 106 is formed by stacking the sige buffer layer 106a, the body layer 106b and the sige cap layer 106C.
As shown in fig. 2, the germanium concentration profile of the embedded epitaxial layer formed by the conventional method for manufacturing the embedded epitaxial layer; the abscissa L1 in fig. 2 represents the buffer layer 106a, L2 represents the bulk germanium layer 106b, L3 represents the capping germanium layer 106c. The Ge% on the ordinate represents the germanium concentration, and as shown in the graph 201, the germanium concentration of the L2 layer is a fixed value.
As shown in fig. 3, a TEM photograph of an embedded epitaxial layer formed by a conventional method for manufacturing an embedded epitaxial layer; the embedded sige epitaxial layer 106 on the left side is collapsed, and the collapsed region is shown by the circle corresponding to the mark 107 a.
Disclosure of Invention
The invention aims to provide a manufacturing method of an embedded epitaxial layer, which can prevent a main body layer of the embedded epitaxial layer from collapsing, thereby improving the performance and yield of products.
In order to solve the technical problems, the manufacturing method of the embedded epitaxial layer provided by the invention comprises the following steps:
and step one, etching the silicon substrate to form a groove.
Filling an embedded epitaxial layer in the groove, wherein the embedded epitaxial layer comprises the following sub-steps:
and step 21, performing selective epitaxial growth to form a buffer layer on the silicon on the inner side surface of the groove.
And step 22, performing selective epitaxial growth to form a main body layer on the surface of the buffer layer.
The main body layer is doped in silicon to provide stress for the silicon substrate at two sides of the groove, the doping concentration of the main body layer is graded doping in the epitaxial growth process of the main body layer, and the graded doping is used for eliminating the fault defect in the epitaxial growth of fixed doping, so that the main body layer is prevented from collapsing.
And 23, performing selective epitaxial growth to form a cap layer on the surface of the main body layer, and stacking the buffer layer, the main body layer and the cap layer to form the embedded epitaxial layer.
The material of the buffer layer, the material of the main body layer and the material of the cap layer are the same, the doping concentration of the buffer layer is smaller than or equal to the lowest doping concentration of the main body layer, and the doping concentration of the cap layer is smaller than or equal to the lowest doping concentration of the main body layer.
A further improvement is that in step 22 the graded doping of the bulk layer is such that the doping concentration is gradually increased and gradually decreased after increasing to the highest doping concentration, under conditions where the total doping amount in the bulk layer is guaranteed to provide the required stress to the silicon substrate on both sides of the recess.
The doping concentration of the bottom surface of the main body layer is larger than or equal to the doping concentration of the top surface of the buffer layer.
The doping concentration of the top surface of the main body layer is larger than or equal to the doping concentration of the bottom surface of the cap layer.
A further improvement is that PMOS or NMOS is integrated on the silicon substrate at the same time.
In a further improvement, the embedded epitaxial layer is an embedded germanium-silicon epitaxial layer in the formation region of the PMOS.
A further improvement is that the embedded germanium-silicon epitaxial layer is also doped with boron impurities.
In the second step, the selective epitaxial growth of the step 21, the step 22 and the step 23 is continuously performed, and the process conditions of the selective epitaxial growth of the step 21, the step 22 and the step 23 comprise: the temperature is 500-800 ℃, and the cavity pressure is 1-100 torr; the process gas comprises: silicon source gas, germanium source gas, HCl and carrier gas.
And adjusting the germanium doping concentration in the buffer layer, the main body layer and the cap layer by adjusting the flow rate of the germanium source gas, wherein the larger the flow rate of the germanium source gas is, the larger the germanium doping concentration is.
A further improvement is that the silicon source gas comprises SiH2Cl2 or SiH4, the germanium source gas comprises GeH4, and the carrier gas comprises H2 and N2;
the flow rate of the carrier gas is 1 slm-50 slm, the flow rate of the silicon source gas is 1 sccm-1000 sccm, the flow rate of the germanium source gas is 1 sccm-1000 sccm, and the flow rate of the HCl is 1 sccm-1000 sccm.
In a further improvement, in the forming area of the NMOS, the embedded epitaxial layer is an embedded phosphorus silicon epitaxial layer.
In the second step, the selective epitaxial growth of the step 21, the step 22 and the step 23 is continuously performed, and the process conditions of the selective epitaxial growth of the step 21, the step 22 and the step 23 comprise: the temperature is 500-800 ℃, and the cavity pressure is 1-100 torr; the process gas comprises: silicon source gas, phosphorus source gas, HCl and carrier gas;
and regulating the phosphorus doping concentration in the buffer layer, the main body layer and the cap layer by regulating the flow of the phosphorus source gas, wherein the phosphorus doping concentration is larger as the flow of the phosphorus source gas is larger.
A further improvement is that the silicon source gas comprises SiH2Cl2 or SiH4, the phosphorus source gas comprises PH3, and the carrier gas comprises H2 and N2;
the flow rate of the carrier gas is 1 slm-50 slm, the flow rate of the silicon source gas is 1 sccm-1000 sccm, the flow rate of the phosphorus source gas is 1 sccm-1000 sccm, and the flow rate of the HCl is 1 sccm-1000 sccm.
In the first step, a grid structure is formed on the silicon substrate, and the grooves are formed on two sides of the grid structure in a self-aligned mode;
the gate structure comprises a gate dielectric layer and a polysilicon gate which are sequentially overlapped;
and a top hard mask layer is covered on the top of the polysilicon gate, and a side wall is formed on the side surface of the polysilicon gate.
A further improvement is that the material of the top hard mask layer comprises silicon oxide or silicon nitride;
the material of the side wall comprises silicon oxide or silicon nitride.
In the first step, the etching process for forming the grooves is dry etching or dry etching humidifying etching; the cross section of the groove is of a U-shaped structure or of a sigma-shaped structure.
The further improvement is that the technical nodes of the PMOS tube and the NMOS tube comprise 40nm, 28nm and below 14 nm.
Compared with the prior art that the main body layer grows according to the fixed doping concentration, the method improves the doping concentration of the main body layer into graded doping, so that under the condition that the total doping concentration in the main body layer can ensure that the required stress is provided for the silicon substrates at two sides of the groove, the stacking fault defect is eliminated in the growth process of the main body layer, and further, collapse caused by stacking fault accumulation in the epitaxial growth process of the main body layer or after the growth is finished can be prevented, and the method can prevent the main body layer of the embedded epitaxial layer from collapsing, thereby improving the performance and the yield of products.
In addition, the invention can be realized by only adjusting the doping concentration of the main body layer, and the doping concentration of the main body layer can be realized by only setting the flow of the doping source without other improvements, so the invention also has the characteristics of simple process and low cost.
The invention is particularly suitable for manufacturing PMOS or NMOS with smaller technical nodes such as 40nm, 28nm and below 14nm, and is beneficial to the continuous downsizing of semiconductor devices in the manufacture of integrated circuits.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIGS. 1A-1D are schematic views of a device structure at various steps in a conventional method for fabricating an embedded epitaxial layer;
FIG. 2 is a graph showing the germanium concentration profile of an embedded epitaxial layer formed by a conventional method of fabricating an embedded epitaxial layer;
FIG. 3 is a TEM photograph of an embedded epitaxial layer formed by a conventional method of manufacturing an embedded epitaxial layer;
FIG. 4 is a flow chart of a method of fabricating an embedded epitaxial layer according to an embodiment of the present invention;
FIGS. 5A-5D are schematic views of a device structure at various steps in a method for fabricating an embedded epitaxial layer according to an embodiment of the present invention;
FIG. 6 is a graph showing the germanium concentration profile of an embedded epitaxial layer formed by a method of fabricating an embedded epitaxial layer according to an embodiment of the present invention;
fig. 7 is a TEM photograph of an embedded epitaxial layer formed by the method for manufacturing an embedded epitaxial layer according to the embodiment of the present invention.
Detailed Description
As shown in fig. 4, a flowchart of a method for manufacturing the embedded epitaxial layer 6 according to an embodiment of the present invention is shown; as shown in fig. 5A to 5D, the device structure of the manufacturing method of the embedded epitaxial layer 6 according to the embodiment of the present invention is shown in schematic views; the manufacturing method of the embedded epitaxial layer 6 comprises the following steps:
step one, as shown in fig. 5A, etching is performed on the silicon substrate 1to form a recess 5.
A gate structure is formed on the silicon substrate 1, and the grooves 5 are formed on two sides of the gate structure in a self-aligned manner.
The gate structure comprises a gate dielectric layer and a polysilicon gate 2 which are sequentially overlapped.
The top of the polysilicon gate 2 is covered with a top hard mask layer 3, and a side wall 4 is formed on the side surface of the polysilicon gate 2.
The material of the top hard mask layer 3 comprises silicon oxide or silicon nitride.
The material of the side wall 4 comprises silicon oxide or silicon nitride.
In the embodiment of the present invention, the etching process for forming the groove 5 is dry etching, and the cross section of the groove 5 has a U-shaped structure. In other embodiments can also be: the etching process for forming the groove 5 is dry etching and humidifying etching; the cross section of the groove 5 is in a U-shaped structure or in a sigma-shaped structure.
The silicon substrate 1 is integrated with PMOS or NMOS at the same time.
Typically, an embedded epitaxial layer is required to be formed on the PMOS; as technology nodes decrease, the NMOS also needs to form an embedded epitaxial layer. At this time, the recess 5 needs to be formed in both the PMOS formation region and the NMOS formation region. If the structures of the recesses 5 of the PMOS and NMOS forming regions are the same as the shape and volume, the recesses 5 of the PMOS and NMOS forming regions can be formed simultaneously. If the structures of the grooves 5 of the PMOS forming region and the NMOS forming region are different, such as different shapes or volumes, the grooves 5 of the PMOS forming region and the NMOS forming region are separately formed, and then the grooves are defined by adopting a photolithography process.
The technology nodes of the semiconductor device comprise 40nm, 28nm and below 14 nm.
In a technology node below 14nm, the semiconductor device is a fin field effect transistor. A fin body patterned by the silicon substrate 1 is formed on the silicon substrate 1, and the groove 5 is formed in the fin body.
Filling an embedded epitaxial layer 6 in the groove 5, wherein the method comprises the following substeps:
in step 21, as shown in fig. 5B, a buffer layer 6a is formed on the silicon on the inner side surface of the recess 5 by selective epitaxial growth.
In step 22, as shown in fig. 5C, selective epitaxial growth is performed to form a body layer 6b on the surface of the buffer layer 6a.
The body layer 6b is doped in silicon to provide stress to the silicon substrate 1 at two sides of the groove 5, the doping concentration of the body layer 6b is gradually changed in the epitaxial growth process of the body layer 6b, and the defect of stacking faults in the epitaxial growth process of fixed doping is eliminated through the gradually changed doping, so that the body layer 6b is prevented from collapsing.
In step 23, as shown in fig. 5D, a cap layer 6c is formed on the surface of the body layer 6b by selective epitaxial growth, and the embedded epitaxial layer 6 is formed by stacking the buffer layer 6a, the body layer 6b and the cap layer 6c.
The materials of the buffer layer 6a, the body layer 6b and the cap layer 6c are the same, the doping concentration of the buffer layer 6a is less than or equal to the lowest doping concentration of the body layer 6b, and the doping concentration of the cap layer 6c is less than or equal to the lowest doping concentration of the body layer 6b.
As shown in fig. 6, the germanium concentration profile of the embedded epitaxial layer formed by the method for manufacturing the embedded epitaxial layer according to the embodiment of the present invention; the abscissa L1 in fig. 6 represents the buffer layer 6a, L2 represents the body layer 6b, L3 represents the cap layer 106c. The Ge% on the ordinate represents the germanium concentration, and it is known from the graph 202 that in step 22 the total doping amount in the bulk layer 6b is such that the graded doping of the doping concentration of the bulk layer 6b is such that the doping concentration is gradually increased and that the doping concentration is gradually decreased after the increase to the highest doping concentration, under the condition that the silicon substrate 1 on both sides of the recess 5 is provided with the required stress.
The doping concentration of the bottom surface of the body layer 6b is equal to the doping concentration of the top surface of the buffer layer 6a. In other embodiments, it can also be: the doping concentration of the bottom surface of the body layer 6b is greater than the doping concentration of the top surface of the buffer layer 6a.
The doping concentration of the top surface of the body layer 6b is equal to the doping concentration of the bottom surface of the cap layer 6c. In other embodiments, it can also be: the doping concentration of the top surface of the body layer 6b is greater than the doping concentration of the bottom surface of the cap layer 6c.
In fig. 6, the doping concentration of the buffer layer 6a is a fixed value, and in other embodiments, the buffer layer 6a can also be gradually changed. In step 22, the buffer layer 6a serves as a seed layer during epitaxial growth of the bulk layer 6b.
As shown in fig. 7, a TEM photograph of the embedded epitaxial layer formed by the method for manufacturing the embedded epitaxial layer according to the embodiment of the present invention shows that no collapse of the embedded epitaxial layer 6 occurs.
In the second step, the embedded epitaxial layer in the NMOS formation region and the embedded epitaxial layer in the PMOS formation region are formed separately. The definition of the formation region is performed by photolithography, the formation region where the embedded epitaxial layer is required to be formed is opened and the formation region where the embedded epitaxial layer is not required to be formed is covered.
In the second step, in the forming region of the PMOS, the embedded epitaxial layer 6 is an embedded sige epitaxial layer. In some embodiments, the embedded silicon germanium epitaxial layer is also doped with boron impurities.
The selective epitaxial growth of step 21, step 22 and step 23 is continuously performed, and the process conditions of the selective epitaxial growth of step 21, step 22 and step 23 include: the temperature is 500-800 ℃, and the cavity pressure is 1-100 torr; the process gas comprises: silicon source gas, germanium source gas, HCl and carrier gas.
The germanium doping concentration in the buffer layer 6a, the body layer 6b, and the cap layer 6c is adjusted by adjusting the flow rate of the germanium source gas, the larger the flow rate of the germanium source gas is, the larger the germanium doping concentration is.
The silicon source gas comprises SiH2Cl2 or SiH4, the germanium source gas comprises GeH4, and the carrier gas comprises H2 and N2;
the flow rate of the carrier gas is 1 slm-50 slm, the flow rate of the silicon source gas is 1 sccm-1000 sccm, the flow rate of the germanium source gas is 1 sccm-1000 sccm, and the flow rate of the HCl is 1 sccm-1000 sccm.
In the second step, in the NMOS formation region, the embedded epi layer 6 is an embedded phosphorus silicon epi layer. The selective epitaxial growth of step 21, step 22 and step 23 is continuously performed, and the process conditions of the selective epitaxial growth of step 21, step 22 and step 23 include: the temperature is 500-800 ℃, and the cavity pressure is 1-100 torr; the process gas comprises: silicon source gas, phosphorus source gas, HCl and carrier gas;
the phosphorus doping concentration in the buffer layer 6a, the body layer 6b, and the cap layer 6c is adjusted by adjusting the flow rate of the phosphorus source gas, the larger the phosphorus doping concentration.
The silicon source gas comprises SiH2Cl2 or SiH4, the phosphorus source gas comprises PH3, and the carrier gas comprises H2 and N2;
the flow rate of the carrier gas is 1 slm-50 slm, the flow rate of the silicon source gas is 1 sccm-1000 sccm, the flow rate of the phosphorus source gas is 1 sccm-1000 sccm, and the flow rate of the HCl is 1 sccm-1000 sccm.
After the second step, the method further comprises the step of performing source-drain injection to form a source region and a drain region in the embedded epitaxial layer, wherein the source region and the drain region of the PMOS tube are both P+ doped; and the source region and the drain region of the NMOS tube are both doped with N+.
The gate structure in the first step is a final gate structure. Or the final gate structure is a metal gate, and the subsequent step further comprises the step of replacing the polysilicon gate 2 with the metal gate; the gate dielectric layer material comprises silicon dioxide or a high dielectric constant material.
Unlike the prior art in which the body layer grows according to a fixed doping concentration, the embodiment of the invention improves the doping concentration of the body layer 6b to graded doping, so that the defect of stacking faults can be eliminated in the growth process of the body layer 6b and further collapse caused by accumulation of stacking faults in the epitaxial growth process or after the growth of the body layer 6b can be prevented under the condition that the total doping concentration in the body layer 6b can ensure to provide required stress for the silicon substrate 1 at both sides of the groove 5, and the embodiment of the invention can prevent the body layer 6b of the embedded epitaxial layer 6 from collapsing, thereby improving the performance and yield of products.
In addition, the embodiment of the invention can be realized by only adjusting the doping concentration of the main body layer 6b, and the doping concentration of the main body layer 6b can be realized by only setting the flow of the doping source without other improvement, so the embodiment of the invention has the characteristics of simple process and low cost.
The embodiment of the invention is particularly suitable for manufacturing PMOS or NMOS with smaller technical nodes such as 40nm, 28nm and below 14nm, and is beneficial to the continuous downsizing of semiconductor devices in the manufacture of integrated circuits.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (14)
1. The manufacturing method of the embedded epitaxial layer is characterized by comprising the following steps of:
etching a silicon substrate to form a groove;
filling an embedded epitaxial layer in the groove, wherein the embedded epitaxial layer comprises the following sub-steps:
step 21, performing selective epitaxial growth to form a buffer layer on the silicon on the inner side surface of the groove;
step 22, performing selective epitaxial growth to form a main body layer on the surface of the buffer layer;
the main body layer is doped in silicon to provide stress for the silicon substrate at two sides of the groove, the doping concentration of the main body layer is graded doping in the epitaxial growth process of the main body layer, and the graded doping is used for eliminating the fault defect in the epitaxial growth of fixed doping, so that the main body layer is prevented from collapsing;
in step 22, under the condition that the total doping amount in the main body layer ensures that the required stress is provided for the silicon substrate at the two sides of the groove, the doping concentration of the main body layer is gradually increased, and the doping concentration is gradually reduced after the main body layer is increased to the highest doping concentration;
step 23, performing selective epitaxial growth to form a cap layer on the surface of the main body layer, and forming the embedded epitaxial layer by laminating the buffer layer, the main body layer and the cap layer;
the material of the buffer layer, the material of the main body layer and the material of the cap layer are the same, the doping concentration of the buffer layer is smaller than or equal to the lowest doping concentration of the main body layer, and the doping concentration of the cap layer is smaller than or equal to the lowest doping concentration of the main body layer.
2. The method of manufacturing an embedded epitaxial layer of claim 1, wherein: the doping concentration of the bottom surface of the main body layer is larger than or equal to the doping concentration of the top surface of the buffer layer.
3. The method of manufacturing an embedded epitaxial layer of claim 1, wherein: the doping concentration of the top surface of the body layer is greater than or equal to the doping concentration of the bottom surface of the cap layer.
4. The method of manufacturing an embedded epitaxial layer of claim 1, wherein: and PMOS or NMOS is integrated on the silicon substrate at the same time.
5. The method of manufacturing an embedded epitaxial layer of claim 4, wherein: and in the PMOS forming region, the embedded epitaxial layer is an embedded germanium-silicon epitaxial layer.
6. The method of manufacturing an embedded epitaxial layer of claim 5, wherein: the embedded germanium-silicon epitaxial layer is also doped with boron impurities.
7. The method of manufacturing an embedded epitaxial layer of claim 5, wherein: in the second step, the selective epitaxial growth of step 21, step 22 and step 23 is continuously performed, and the process conditions of the selective epitaxial growth of step 21, step 22 and step 23 include: the temperature is 500-800 ℃, and the cavity pressure is 1-100 torr; the process gas comprises: silicon source gas, germanium source gas, HCl and carrier gas;
and adjusting the germanium doping concentration in the buffer layer, the main body layer and the cap layer by adjusting the flow rate of the germanium source gas, wherein the larger the flow rate of the germanium source gas is, the larger the germanium doping concentration is.
8. The method of manufacturing an embedded epitaxial layer of claim 7, wherein: the silicon source gas comprises SiH2Cl2 or SiH4, the germanium source gas comprises GeH4, and the carrier gas comprises H2 and N2;
the flow rate of the carrier gas is 1 slm-50 slm, the flow rate of the silicon source gas is 1 sccm-1000 sccm, the flow rate of the germanium source gas is 1 sccm-1000 sccm, and the flow rate of the HCl is 1 sccm-1000 sccm.
9. The method of manufacturing an embedded epitaxial layer of claim 4, wherein: in the NMOS forming region, the embedded epitaxial layer is an embedded phosphorus silicon epitaxial layer.
10. The method of manufacturing an embedded epitaxial layer of claim 9, wherein: in the second step, the selective epitaxial growth of step 21, step 22 and step 23 is continuously performed, and the process conditions of the selective epitaxial growth of step 21, step 22 and step 23 include: the temperature is 500-800 ℃, and the cavity pressure is 1-100 torr; the process gas comprises: silicon source gas, phosphorus source gas, HCl and carrier gas;
and regulating the phosphorus doping concentration in the buffer layer, the main body layer and the cap layer by regulating the flow of the phosphorus source gas, wherein the phosphorus doping concentration is larger as the flow of the phosphorus source gas is larger.
11. The method of manufacturing an embedded epitaxial layer of claim 10, wherein: the silicon source gas comprises SiH2Cl2 or SiH4, the phosphorus source gas comprises PH3, and the carrier gas comprises H2 and N2;
the flow rate of the carrier gas is 1 slm-50 slm, the flow rate of the silicon source gas is 1 sccm-1000 sccm, the flow rate of the phosphorus source gas is 1 sccm-1000 sccm, and the flow rate of the HCl is 1 sccm-1000 sccm.
12. The method of manufacturing an embedded epitaxial layer of claim 1, wherein: in the first step, a grid structure is formed on the silicon substrate, and the grooves are formed on two sides of the grid structure in a self-aligned mode;
the gate structure comprises a gate dielectric layer and a polysilicon gate which are sequentially overlapped;
and a top hard mask layer is covered on the top of the polysilicon gate, and a side wall is formed on the side surface of the polysilicon gate.
13. The method of manufacturing an embedded epitaxial layer of claim 1, wherein: in the first step, the etching process for forming the groove is dry etching or dry etching humidifying etching; the cross section of the groove is of a U-shaped structure or of a sigma-shaped structure.
14. The method of manufacturing an embedded epitaxial layer of claim 4, wherein: the technical nodes of the PMOS tube and the NMOS tube comprise 40nm, 28nm and below 14 nm.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102931058A (en) * | 2011-08-08 | 2013-02-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure and method for forming P-channel metal oxide semiconductor (PMOS) transistor |
| CN104538448A (en) * | 2014-12-24 | 2015-04-22 | 上海集成电路研发中心有限公司 | PMOS structure with SiGe source and drain area and manufacturing method thereof |
| CN111599764A (en) * | 2020-05-29 | 2020-08-28 | 上海华力集成电路制造有限公司 | Method for manufacturing embedded epitaxial layer |
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| US7772676B2 (en) * | 2006-06-23 | 2010-08-10 | Infineon Technologies Ag | Strained semiconductor device and method of making same |
| US8835982B2 (en) * | 2011-02-14 | 2014-09-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing strained source/drain structures |
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| CN104538448A (en) * | 2014-12-24 | 2015-04-22 | 上海集成电路研发中心有限公司 | PMOS structure with SiGe source and drain area and manufacturing method thereof |
| CN111599764A (en) * | 2020-05-29 | 2020-08-28 | 上海华力集成电路制造有限公司 | Method for manufacturing embedded epitaxial layer |
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