CN116682821A

CN116682821A - Semiconductor device, semiconductor structure and forming method thereof

Info

Publication number: CN116682821A
Application number: CN202310520746.4A
Authority: CN
Inventors: 王志庆; 谢文兴
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-05-10
Filing date: 2023-05-10
Publication date: 2023-09-01

Abstract

Embodiments of the present invention describe semiconductor devices having asymmetric source/drain (S/D) designs. The semiconductor device includes a plurality of semiconductor layers on a substrate, a gate structure surrounding the plurality of semiconductor layers, an internal spacer structure between the plurality of semiconductor layers and in contact with a first side of the gate structure, and an epitaxial layer in contact with a second side of the gate structure. The second side is opposite to the first side. Embodiments of the present invention also provide semiconductor structures and methods of forming semiconductor structures.

Description

Semiconductor device, semiconductor structure and forming method thereof

Technical Field

Embodiments of the present invention relate to semiconductor devices, semiconductor structures, and methods of forming the same.

Background

With advances in semiconductor technology, there is an increasing demand for higher storage capacity, faster processing systems, higher performance, and lower cost. To meet these needs, the semiconductor industry is continually scaling down semiconductor device dimensions, such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), including planar MOSFETs and fin field effect transistors (finfets). This scaling increases the complexity of the semiconductor manufacturing process and increases the difficulty of defect control in the semiconductor device.

Disclosure of Invention

Some embodiments of the present invention provide a semiconductor structure comprising: a plurality of semiconductor layers on the substrate; a gate structure surrounding the plurality of semiconductor layers; an internal spacer structure located between the plurality of semiconductor layers and in contact with the first side of the gate structure; and an epitaxial layer in contact with a second side of the gate structure, wherein the second side is opposite to the first side.

Further embodiments of the present invention provide a semiconductor device including: a plurality of channel structures located on the substrate; a gate structure surrounding the plurality of channel structures; an internal spacer structure in contact with the gate structure and adjacent to the first ends of the plurality of channel structures; a gate spacer on sidewalls of the gate structure and over the plurality of channel structures; and an epitaxial layer in contact with the gate structure and a second end of the plurality of channel structures, wherein the second end is opposite the first end.

Still further embodiments of the present invention provide a method of forming a semiconductor structure, the method comprising: forming a plurality of semiconductor layers on a substrate, wherein the plurality of semiconductor layers includes a first group of semiconductor layers and a second group of semiconductor layers stacked in an alternating configuration; replacing a portion of the first set of semiconductor layers with an internal spacer structure at a first end of the plurality of semiconductor layers; forming an epitaxial layer in contact with the substrate and a second end of the plurality of semiconductor layers, wherein the second end is opposite the first end; and forming a first source/drain structure in contact with the internal spacer structure and forming a second source/drain structure on the epitaxial layer.

Drawings

Aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawing figures.

Fig. 1 illustrates an isometric view of a semiconductor device having an asymmetric source/drain (S/D) design, in accordance with some embodiments.

Fig. 2 illustrates a cross-sectional view of a semiconductor device having an asymmetric S/D design in accordance with some embodiments.

Fig. 3 is a flow chart of a method of fabricating a semiconductor device having an asymmetric S/D design, in accordance with some embodiments.

Fig. 4-17 illustrate cross-sectional views of semiconductor devices having asymmetric S/D designs, in accordance with some embodiments.

Fig. 18-22 illustrate cross-sectional views of semiconductor devices having another asymmetric S/D design, in accordance with some embodiments.

Fig. 23-27 illustrate cross-sectional views of semiconductor devices having yet another asymmetric S/D design, in accordance with some embodiments.

The illustrated embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements.

Detailed Description

The following disclosure provides many different embodiments, or examples, for different components of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. As used herein, forming a first component on a second component means that the first component is formed in direct contact with the second component. Furthermore, the present invention may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms such as "under …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It should be noted that references in the specification to "one embodiment," "an example," etc., indicate that the embodiment described may include a particular component, structure, or characteristic, but every embodiment may not necessarily include the particular component, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular component, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such component, structure, or characteristic in connection with other embodiments whether or not explicitly described.

It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings herein.

In some embodiments, the terms "about" and "substantially" may refer to a given amount of a value that varies within 20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±20%) of the value. These values are merely examples and are not limiting. The terms "about" and "substantially" may refer to percentages of values that are interpreted by those of ordinary skill in the relevant art in light of the teachings herein.

As semiconductor technology advances, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing Short Channel Effects (SCE). One such multi-gate device is a nanostructured transistor that includes a full-gate field effect transistor (GAA FET), a nanoplatelet transistor, a nanowire transistor, a multi-bridge channel transistor, a nanoribbon transistor, and other similarly structured transistors. The nanostructured transistor provides a channel in a stacked nanoplatelet/nanowire configuration. The name of GAA FET devices derives from the fact that the gate structure may extend around the channel and may provide gate control of the channel on multiple sides of the channel. Nanostructured transistor devices are compatible with MOSFET fabrication processes and their structure allows them to scale while maintaining gate control and reducing SCE.

As the demand for lower power consumption, higher performance, and smaller area (collectively referred to as "PPA") for semiconductor devices continues to increase, nanostructured transistor devices may have their challenges. For example, a nanostructured transistor device may have an internal spacer structure between the gate structure and the source/drain (S/D) structure to reduce parasitic capacitance. In p-type nanostructured transistor devices, an embedded silicon germanium (SiGe) stressor (e.g., S/D structure) may be used to increase device current and improve device performance. However, dislocation defects may be formed in the S/D structure of the nanostructured transistor device with an internal spacer structure. The S/D defects may relax the strain applied to the channel, reducing the device current and compromising the device performance of the nanostructured transistor device. Meanwhile, without the internal spacer structure, dislocation defects in the S/D structure can be reduced while parasitic capacitance between the S/D structure and the gate structure increases. The increase in parasitic capacitance may degrade device performance.

Various embodiments of the present invention provide exemplary methods of forming asymmetric source/drain (S/D) designs for nanostructured transistor devices (e.g., GAA FETs) and/or other semiconductor devices in Integrated Circuits (ICs). The nanostructured transistor device may have a plurality of nanostructured channels and a gate structure surrounding the nanostructured channels. The internal spacer structure may be in contact with the first side of the gate structure, and the internal spacer structure may be disposed between the gate structure and the first S/D structure. The epitaxial layer may be in contact with the second side of the gate structure, and the epitaxial layer may be disposed between the gate structure and the second S/D structure. The second side may be opposite the first side. In some embodiments, the first side may be a drain side of the nanostructured transistor device and the second side may be a source side of the nanostructured transistor device.

With the epitaxial layer on the source side, dislocation defects in the second S/D structure can be reduced by about 50% to about 80%, the resistance of the second S/D structure can be significantly reduced, the proximity between the second S/D structure and the gate structure can be reduced, the strain applied to the nanostructure channel can be improved, and the device current can be increased. The internal spacer structure on the drain side may reduce parasitic capacitance between the gate structure and the first S/D structure. Since the channel current of the nanostructured transistor device is dominated by the resistance of the second S/D structure on the source side, an asymmetric design of the nanostructured transistor device may improve device performance, for example, by about 5% to about 20% for a p-type nanostructured transistor device and by about 0.5% to about 5% for an n-type nanostructured transistor device.

Fig. 1 illustrates an isometric view of a semiconductor device 100 having an asymmetric S/D design, in accordance with some embodiments. Fig. 2 illustrates a cross-sectional view of the semiconductor device 100 along line A-A shown in fig. 1, in accordance with some embodiments. Semiconductor device 100 may include nanostructure transistor 102-1 and nanostructure transistor 102-2. Referring to fig. 1 and 2, a semiconductor device 100 having a nanostructure transistor 102-1 and a nanostructure transistor 102-2 may be formed on a substrate 104 and may be isolated by Shallow Trench Isolation (STI) regions 106. Each of the nanostructure transistors 102-1 and 102-2 may include a nanostructure 108, a gate structure 110, a gate spacer 120, an internal spacer structure 111, an epitaxial layer 112A and 112B (collectively, "epitaxial layer 112"), S/D structures 114A and 114B (collectively, "S/D structures 114"), an Etch Stop Layer (ESL) 126, an interlayer dielectric (ILD) layer 136, and S/D contact structures 128.

In some embodiments, nanostructure transistor 102-1 and nanostructure transistor 102-2 may each be an n-type nanostructure transistor (NFET). In some embodiments, the nanostructure transistor 102-1 may be an NFET and have an n-type S/D structure 114. The nanostructure transistor 102-2 may be a p-type nanostructure transistor (PFET) and have a p-type S/D structure 114. In some embodiments, the nanostructure transistor 102-1 and the nanostructure transistor 102-2 may both be PFETs. Although two nanostructure transistors are shown in fig. 1, semiconductor device 100 may have any number of nanostructure transistors. In addition, the semiconductor device 100 may be incorporated into an IC through the use of other structural components, such as through conductive vias, wires, dielectric layers, passivation layers, and interconnects, which are not shown for simplicity. Unless otherwise indicated, discussion of elements of nanostructure transistor 102-1 and nanostructure transistor 102-2 having the same designation applies to each other. And like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements.

Referring to fig. 1 and 2, the substrate 104 may comprise a semiconductor material, such as silicon. In some embodiments, the substrate 104 comprises a crystalline silicon substrate (e.g., a wafer). In some embodiments, the substrate 104 comprises (i) an elemental semiconductor, such as germanium; (ii) A compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; (iii) Alloy semiconductors including silicon germanium carbide, silicon germanium, gallium arsenic phosphide, and/or aluminum gallium arsenide; (iv) combinations thereof. Further, the substrate 104 may be doped depending on design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, the substrate 104 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

STI regions 106 may provide electrical isolation between nanostructure transistors 102-1 and nanostructure transistor 102-2 from each other, and between nanostructure transistor 102-1 and nanostructure transistor 102-2 and adjacent nanostructure transistors (not shown) on substrate 104, and/or between adjacent active and passive elements (not shown) deposited on or integrated with substrate 104. STI regions 106 may be made of a dielectric material. In some embodiments, STI regions 106 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine doped silicate glass (FSG), low-k dielectric material, and/or other suitable insulating material. In some embodiments, STI regions 106 may include a multi-layer structure.

Referring to fig. 1 and 2, nanostructures 108 may be formed on a patterned portion of the substrate 104. Embodiments of the nanostructures disclosed herein may be patterned by any suitable method. For example, the nanostructures may be patterned using one or more photolithographic processes, including double patterning or multiple patterning processes. The double pattern process or the multiple pattern process may combine lithography and self-aligned processes to form a pattern having a smaller pitch than that obtainable using, for example, a single direct lithography process. For example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the nanostructures.

As shown in fig. 2, the nanostructures 108 may extend along the X-axis and through the nanostructure transistor 102-1 and the nanostructure transistor 102-2. In some embodiments, the nanostructures 108 may be disposed on the substrate 104 and may include a stack of semiconductor layers 108-1, 108-2, and 108-3 (also collectively referred to as "semiconductor layers 108"), which may be in the form of nanostructures, such as nanoplatelets, nanowires, and nanoribbons. Each nanostructure 108 may form a channel region under the gate structure 110 of the nanostructure transistor 102-1 and the nanostructure transistor 102-2. In some embodiments, the nanostructures 108 may comprise a semiconductor material similar to or different from the substrate 104. In some embodiments, each nanostructure 108 may comprise silicon. In some embodiments, each nanostructure 108 may comprise silicon germanium. The semiconductor material of the nanostructures 108 may be undoped or may be doped in situ during their epitaxial growth. Each nanostructure 108 may have a thickness 108t along the Z-axis in the range of about 5nm to about 15 nm. As shown in fig. 1 and 2, the nanostructures 108 under the gate structure 110 may form a channel region of the semiconductor device 100 and represent a current carrying structure of the semiconductor device 100. Although three layers of nanostructures 108 are shown in fig. 2, the nanostructure transistors 102-1 and 102-2 may have any number of nanostructures 108.

Referring to fig. 1 and 2, the gate structure 110 may be a multi-layered structure and may surround a middle portion of the nanostructure 108. In some embodiments, each nanostructure 108 may be surrounded by one or more layers of the gate structure 110, where the gate structure 110 may be referred to as a "full-ring Gate (GAA) structure" and the nanostructure transistor 102-1 and nanostructure transistor 102-2 may also be referred to as "GAA FET102-1 and GAA FET 102-2".

As shown in fig. 2, the gate structure 110 may include a gate dielectric layer 122 and a metal gate structure 124. In some embodiments, gate dielectric layer 122 may include an interfacial layer and a high-k dielectric layer. In some embodiments, gate dielectric layer 122 may comprise a high-k dielectric layer. The term "high k" may refer to a high dielectric constant. In the field of semiconductor device structures and fabrication processes, high k may refer to a dielectric constant greater than SiO ₂ For example, greater than about 3.9). In some embodiments, the interfacial layer may include silicon oxide formed by a deposition process or an oxidation process. In some embodiments, the high-k dielectric layer may include hafnium oxide (HfO ₂ ) Zirconium oxide (ZrO) ₂ ) And other suitable high-k dielectric materials. As shown in fig. 2, a gate dielectric layer 122 may surround each nanostructure 108 and thus electrically isolate the nanostructures 108 from each other, and electrically isolate the nanostructures 108 from the conductive metal gate structure 124, to prevent shorting between the gate structures 110 and the nanostructures 108 during operation of the nanostructure transistors 102-1 and 102-2. In some embodiments, the gate dielectric layer 122 may have a thickness along the Z-axis of about To about->A thickness in the range.

In some embodiments, the metal gate structure 124 may include a work function layer and a gate electrode. The work function layer may surround the nanostructures 108 and may include a work function metal to adjust the threshold voltages (Vt) of the nanostructure transistor 102-1 and the nanostructure transistor 102-2. In some embodiments, the work function layer may include titanium nitride, ruthenium, titanium aluminum carbon, tantalum aluminum carbon, or other suitable work function metal. In some embodiments, the work function layer may comprise a single metal layer or a stack of metal layers. The stack of metal layers may include work function metals having work function values equal to or different from each other. The gate electrode may include titanium, tantalum, aluminum, cobalt, tungsten, nickel, ruthenium, and other suitable conductive materials. Depending on the spacing between adjacent nanostructures 108 and the thickness of the layers of the gate structure 110, the nanostructures 108 may be surrounded by one or more layers of the gate structure 110, thereby filling the spacing between adjacent nanostructures 108.

Referring to fig. 1 and 2, a gate spacer 120 may be disposed on sidewalls of the gate structure 110 and in contact with a gate dielectric layer 122. According to some embodiments, an internal spacer structure 111 may be disposed adjacent to one end portion of the nanostructure 108 and between the S/D structure 114A and the gate structure 110. The gate spacers 120 and the inner spacer structures 111 may comprise insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, low-k materials, and combinations thereof. In some embodiments, the gate spacer 120 and the inner spacer structure 111 may comprise the same insulating material. In some embodiments, the gate spacer 120 and the inner spacer structure 111 may comprise different insulating materials. The gate spacer 120 and the internal spacer structure 111 may include a single layer or a stack of insulating layers. In some embodiments, the gate spacer 120 and the inner spacer structure 111 may have a low-k material with a dielectric constant less than about 3.9 (e.g., about 3.5, about 3.0, or about 2.8). In some embodiments, the inner spacer structure 111 may have a thickness along the Z-axis in the range of about 4nm to about 8 nm.

The S/D structure 114 may be disposed on the substrate 104 and on opposite sides of the nanostructures 108. In some embodiments, the semiconductor device 100 may have a first S/D structure 114A on a first side (e.g., drain side) of the nanostructure transistor 102-1 or nanostructure transistor 102-2 and a second S/D structure 114B on a second side (e.g., source side) of the nanostructure transistor 102-1 or nanostructure transistor 102-2. The S/D structure 114 may function as an S/D region for the nanostructure transistor 102-1 or the nanostructure transistor 102-2. In some embodiments, the S/D structure 114 may have any geometric shape, such as polygonal, elliptical, and circular. In some embodiments, the S/D structure 114 may comprise an epitaxially grown semiconductor material, such as silicon, the same material as the substrate 104. In some embodiments, the epitaxially grown semiconductor material may include an epitaxially grown semiconductor material, such as silicon germanium, that is different from the material of the substrate 104, and the epitaxially grown semiconductor material imparts strain to the channel region under the gate structure 110. Since the lattice constant of such epitaxially grown semiconductor material is different from the material of substrate 104, the channel region is strained to increase carrier mobility in the channel region of semiconductor device 100. The epitaxially grown semiconductor material may include: (i) semiconductor materials such as germanium and silicon; (ii) Compound semiconductor materials such as gallium arsenide and aluminum gallium arsenide; or (iii) semiconductor alloys such as silicon germanium and gallium arsenide phosphorous.

In some embodiments, the S/D structure 114 may comprise silicon, and the S/D structure 114 may be doped in situ during the epitaxial growth process using n-type dopants (such as phosphorus and arsenic). In some embodiments, the S/D structure 114 may include silicon, silicon germanium, or III-V material (e.g., indium antimonide, gallium antimonide, or indium gallium antimonide), and the S/D structure 114 may be doped in-situ during the epitaxial growth process using p-type dopants such as boron, indium, and gallium. In some embodiments, the S/D structure 114 may include one or more epitaxial layers, where each epitaxial layer may have a different composition.

As shown in fig. 2, the S/D structure 114 may include a first S/D epitaxial layer 116A and a first S/D epitaxial layer 116B (collectively, "first S/D epitaxial layer 116") and a second S/D epitaxial layer 118A and a second S/D epitaxial layer 118B (collectively, "second S/D epitaxial layer 118"). In some embodiments, the n-type S/D structure 114 may include an arsenide or phosphideAnd (3) doped silicon. For example, the first S/D epitaxial layer 116 may include a silicon nitride layer of about 1 x 10 ¹⁹ Atoms/cm ³ Up to about 1X 10 ²¹ Atoms/cm ³ Is doped with arsenide or phosphide. The second S/D epitaxial layer 118 may include a silicon nitride layer of about 1 x 10 ²¹ Atoms/cm ³ Up to about 1X 10 ²² Atoms/cm ³ Is doped with phosphide. In some embodiments, the p-type S/D structure 114 may comprise boron doped silicon germanium. In some embodiments, the first S/D epitaxial layer 116 may have a lower Ge concentration than the second S/D epitaxial layer 118 to prevent lattice mismatch and dislocation defects. For example, the first S/D epitaxial layer 116 may include silicon germanium having a germanium concentration of about 0 to about 30% and doped with a concentration of about 1 x 10 ²⁰ Atoms/cm ³ Up to about 1X 10 ²¹ Atoms/cm ³ Is a boron of (a). The second S/D epitaxial layer 118 may comprise silicon germanium having a germanium concentration of about 20% to about 100% and doped with a concentration of about 1 x 10 ²¹ Atoms/cm ³ Up to about 2X 10 ²¹ Atoms/cm ³ Is a boron of (a).

In some embodiments, the first S/D epitaxial layer 116 may have a thickness 116t ranging from about 2nm to about 10 nm. If the thickness 116t is less than about 2nm, the first epitaxial layer 116 may not grow. If the thickness 116t is greater than about 10nm, the proximity between the S/D structure 114 and the gate structure 110 may increase and the device on-current of the nanostructure transistor 102-1 and the nanostructure transistor 102-2 may decrease. In some embodiments, the sidewalls of the first S/D epitaxial layer 116A and the inner spacer structure 111 may be aligned. In some embodiments, the sidewalls of the first S/D epitaxial layer 116A and the inner spacer structure 111 may not be aligned.

As shown in fig. 2, an epitaxial layer 112 may be disposed between the nanostructures 108 and the S/D structures 114. In some embodiments, the internal spacer structure 111 may be in contact with the gate structure 110 at a first side (e.g., drain side) of the nanostructure transistor 102-1 and nanostructure transistor 102-2, and the epitaxial layer 112B may be in contact with the gate structure 110 at a second side (e.g., source side) of the nanostructure transistor 102-1 and nanostructure transistor 102-2. In some embodiments, the epitaxial layer 112A may be uniformly disposed on the semiconductor layer 108-1, the semiconductor layer 108-2, and end portions of the semiconductor layer 108-3 at the first side, and the substrate 104. In some embodiments, as shown in fig. 2, epitaxial layer 112A may include a vertical portion in contact with nanostructure 108 and a horizontal portion in contact with substrate 104. In some embodiments, the epitaxial layer 112B may be uniformly disposed on the gate structure 110, the nanostructures 108, and the substrate 104 at the second side. The second side may be opposite the first side. In some embodiments, as shown in fig. 2, epitaxial layer 112B may include a vertical portion in contact with gate structure 110 and nanostructure 108 and a horizontal portion in contact with substrate 104. In some embodiments, as shown in fig. 2, an epitaxial layer 112A and an epitaxial layer 112B may be formed on both ends of the nanostructure 108 and on one side (e.g., source side) of the gate structure 110. In some embodiments, the epitaxial layer 112A and the epitaxial layer 112B are not formed on the other side (e.g., drain side) of the gate structure 110. Since the semiconductor device 100 has a structure on the source side that is different from that on the drain side, for example, the internal spacer structure 111 is in contact with the gate structure 110 on the drain side, and the epitaxial layer 112B is in contact with the gate structure 110 on the source side, such an S/D design of the semiconductor device 100 may be referred to as an "asymmetric S/D design".

In some embodiments, epitaxial layer 112 may comprise an epitaxially grown semiconductor material, such as silicon. Epitaxial layer 112 may be undoped or doped. In some embodiments, epitaxial layer 112 may comprise undoped silicon. In some embodiments, the epitaxial layer 112 may include silicon, and the epitaxial layer 112 may be doped in situ during the epitaxial growth process with n-type dopants (such as phosphorus and arsenic). The n-type dopant may have about 1 x 10 ¹⁹ Atoms/cm ³ Up to about 1X 10 ²¹ Atoms/cm ³ Is a concentration of (3). In some embodiments, the epitaxial layer 112 may include silicon, and the epitaxial layer 112 may be doped in situ during the epitaxial growth process with a p-type dopant (such as boron). The p-type dopant may have about 1 x 10 ¹⁹ Atoms/cm ³ Up to about 1X 10 ²¹ Atoms/cm ³ Is a concentration of (3). If the concentration of n-type dopant or p-type dopantA degree of greater than about 1 x 10 ²¹ Atoms/cm ³ Hot carrier leakage currents of the nanostructure transistor 102-1 and the nanostructure transistor 102-2 may increase. If the concentration of the n-type dopant or the p-type dopant is less than about 1 x 10 ¹⁹ Atoms/cm ³ The device on-current of the nanostructure transistor 102-1 and the nanostructure transistor 102-2 may decrease.

In some embodiments, the epitaxial layer 112 may serve as an etch stop layer to protect the S/D structure 114 during formation of the gate structure 110. In some embodiments, epitaxial layer 112 may reduce dislocation defects in S/D structure 114B by about 50% to about 80%, reduce the resistance of S/D structure 114B, reduce the proximity between S/D structure 114B and gate structure 110, increase the strain applied to nanostructure 108, and increase the device on-current of nanostructure transistor 102-1 and nanostructure transistor 102-2.

In some embodiments, epitaxial layer 112 may have a thickness 112t in a range from about 1nm to about 10 nm. The ratio of thickness 112t to thickness 108t may be in the range of about 0.1 to about 2. If the thickness 112t is less than about 1nm or the ratio is less than about 0.1, the epitaxial layer 112 may not grow and the S/D structure 114B may be damaged during formation of the gate structure 110. If the thickness 112t is greater than about 10nm or the ratio is greater than about 2, the proximity between the S/D structure 114B and the gate structure 110 may increase and the device on-current of the nanostructure transistor 102-1 and the nanostructure transistor 102-2 may decrease.

In some embodiments, epitaxial layer 112 may improve device performance of p-type nanostructured transistor devices by about 5% to about 20%. In some embodiments, epitaxial layer 112 may improve the device performance of n-type nanostructured transistor devices by about 0.5% to about 5%.

Referring to fig. 1 and 2, esl 126 may be disposed on sidewalls of STI regions 106, S/D structures 114, and gate spacers 120. The ESL 126 may be configured to protect the STI region 106, the S/D structure 114, and the gate structure 110 during formation of the S/D contact structure on the S/D structure 114. In some embodiments, ESL 126 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, silicon carbon boron nitride, or combinations thereof.

ILD layer 136 may be disposed on ESL126 over S/D structure 114 and STI region 106. ILD layer 136 may comprise a dielectric material deposited using a deposition method suitable for flowable dielectric materials. Flowable silicon oxide can be deposited using Flowable Chemical Vapor Deposition (FCVD), for example. In some embodiments, the dielectric material may include silicon oxide.

The S/D contact structure 128 may be disposed on the S/D structure 114 and may be configured to electrically connect the S/D regions of the nanostructure transistor 102-1 and nanostructure transistor 102-2 (e.g., S/D structure 114) to other elements of the semiconductor device 100 and/or other semiconductor devices in the IC of the semiconductor device 100. S/D contact structure 128 may be formed within ILD layer 136. According to some embodiments, the S/D contact structure 128 may include a metal silicide layer 130 and a metal contact 132 disposed on the metal silicide layer 130. Examples of metals for forming the metal silicide layer 130 may include cobalt, titanium, and nickel. In some embodiments, the metal contacts 132 may include, for example, tungsten, cobalt, aluminum, copper, titanium, tantalum, silver, ruthenium, metal alloys, or combinations thereof.

Fig. 3 is a flow chart of a method 300 of fabricating a semiconductor device 100 having an asymmetric S/D design, in accordance with some embodiments. The method 300 may not be limited to nanostructured transistor devices and may be adapted to other devices that would benefit from asymmetric S/D designs. Additional fabrication operations may be performed between the various operations of method 300 and may be omitted merely for clarity and ease of description. Additional processes may be provided before, during, and/or after method 300; one or more of these additional processes are briefly described herein. Moreover, not all operations may be required to perform the disclosure provided herein. In addition, some operations may be performed simultaneously or in a different order than shown in fig. 3. In some embodiments, one or more other operations may be performed in addition to or in place of the presently described operations.

For the purpose of illustration, the operation shown in fig. 3 will be described with reference to an example manufacturing process of manufacturing the semiconductor device 100 shown in fig. 4 to 27. Fig. 4-27 illustrate cross-sectional views of a semiconductor device 100 having an asymmetric S/D design at various stages of its fabrication, in accordance with some embodiments. In some embodiments, fig. 4-17 illustrate cross-sectional views of a semiconductor device 100 having a first asymmetric S/D design. In some embodiments, fig. 18-22 illustrate cross-sectional views of a semiconductor device 100 having a second asymmetric S/D design. In some embodiments, fig. 23-27 illustrate cross-sectional views of a semiconductor device 100 having a third asymmetric S/D design. Elements in fig. 4 to 27 having the same reference numerals as those in fig. 1 and 2 are described above.

Referring to fig. 3, a method 300 begins with operation 310 and a process of forming a plurality of semiconductor layers on a substrate, the plurality of semiconductor layers having a first set of semiconductor layers and a second set of semiconductor layers stacked in an alternating configuration. For example, as shown in fig. 4, a first set of semiconductor layers 438-1, 438-2, and 438-3 (collectively, "first set of semiconductor layers 438") and a second set of semiconductor layers 108-1, 108-2, and 108-3 (collectively, "second set of semiconductor layers 108") may be formed over the substrate 104. The first group of semiconductor layers 438 and the second group of semiconductor layers 108 may be stacked in an alternating configuration.

In some embodiments, the first set of semiconductor layers 438 and the second set of semiconductor layers 108 may be epitaxially grown on the substrate 104. In some embodiments, the first set of semiconductor layers 438 may comprise a different semiconductor material than the substrate 104. The second set of semiconductor layers 108 may comprise the same semiconductor material as the substrate 104. In some embodiments, the substrate 104 and the second set of semiconductor layers 108 may comprise silicon. The first set of semiconductor layers 438 may comprise silicon germanium. In some embodiments, the germanium concentration in the silicon germanium may be in a range of about 10% to about 50% to increase the etch selectivity between the first set of semiconductor layers 438 and the second set of semiconductor layers 108. In some embodiments, the first set of semiconductor layers 438 may have a thickness 438t along the Z-axis in a range of about 3nm to about 10 nm. The second set of semiconductor layers 108 may have a thickness 108t along the Z-axis in the range of about 5nm to about 15 nm.

Referring to fig. 3, in operation 320, a gate structure is formed on a plurality of semiconductor layers. For example, as shown in fig. 5-7, a sacrificial gate structure 510 may be formed over semiconductor layer 438 and semiconductor layer 108. In some embodiments, operation 320 may include forming sacrificial gate structures 510 and gate cap structures 542, forming gate spacers 120, and recessing the S/D regions. Referring to fig. 5, in some embodiments, the sacrificial gate structure 510 may be formed by blanket depositing amorphous silicon or polysilicon and a hard mask layer, followed by photolithography to form the gate cap structure 542, and etching the deposited amorphous silicon or polysilicon that is not protected by the gate cap structure 542. In some embodiments, the gate cap structure 542 may include silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or other suitable dielectric materials.

In some embodiments, as shown in fig. 6, gate spacers 120 may be formed by blanket depositing a dielectric material, followed by a directional etch to retain the dielectric material on the sidewall surfaces of sacrificial gate structure 510. In some embodiments, the dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, low-k materials, and combinations thereof.

In some embodiments, as shown in fig. 7, semiconductor layer 438 and semiconductor layer 108 may be recessed along with substrate 104 to form S/D regions of nanostructure transistors 102-1 and nanostructure transistor 102-2. Recessing the S/D regions may include a dry etching process performed at a temperature of about 40 ℃ to about 70 ℃. The dry etching process may be biased at a voltage of about 300V to about 600V. In some embodiments, the dry etching process may etch portions of the first set of semiconductor layers 438 and the second set of semiconductor layers 108, and the dry etching process may extend into the substrate 104, as shown in fig. 7. In some embodiments, the dry etching process may extend into the substrate along the Z-axis a distance 104d, the distance 104d being in the range of about 5nm to about 20 nm. After recessing the S/D regions, end portions of the first and second semiconductor layers 438 and 108 may be exposed for subsequent processing.

Referring to fig. 3, at a first end of the plurality of semiconductor layers, portions of the first set of semiconductor layers are replaced with an internal spacer structure in operation 330. For example, as shown in fig. 8-11, at a first end of semiconductor layers 438 and 108, portions of first set of semiconductor layers 438 are replaced with internal spacer structures 111. Replacing portions of the first set of semiconductor layers 438 with the inner spacer structures 111 may include covering second ends of the semiconductor layers 438 and 108, laterally recessing portions of the first set of semiconductor layers 438, and forming the inner spacer structures 111 at the recesses of the first set of semiconductor layers 438 between the second set of semiconductor layers 108.

Referring to fig. 8, a masking layer 844 may be patterned to cover the second ends of semiconductor layers 438 and 108. The composition of the masking layer 844 may include photoresist, bottom antireflective coating, hard mask, and/or other suitable materials. The patterning process may include forming a mask layer 844 over the structure shown in fig. 7, exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the photoresist to form a masking element. The mask layer 844 may be used to protect the second ends of the semiconductor layers 438 and 108 while one or more etching processes may laterally recess the exposed first ends of the first set of semiconductor layers 438.

In some embodiments, as shown in fig. 9, the first set of semiconductor layers 438 may be laterally recessed by a selective etching process, according to some embodiments. The selective etch process may have a high etch selectivity between the first set of semiconductor layers 438 and the second set of semiconductor layers 108. In some embodiments, the selective etching process may include etchants such as Hydrogen Fluoride (HF) and fluorine (F) ₂ ) The gas, and the selective etching process may be performed at a temperature of about 0 ℃ to about 40 ℃ at a pressure of about 100 millitorr to about 1000 millitorr. In some embodiments, the selective etching process may include an etchant, such as a metal selected from nitrogen trifluoride (NF ₃ ) Dissociated fluorine radicals, and the selective etching process may be performed at a temperature of about-10 ℃ to about 10 ℃ and at a pressure of about 3 mtorr to about 1000 mtorr. After the selective etching process, end portions of the first set of semiconductor layers 438 on the first ends of the semiconductor layers 438 and 108 may be laterally recessed to form recesses 911r, 911r have a recess depth 911d in the range of about 5nm to about 10 nm.

After laterally recessing the first set of semiconductor layers 438, an inner spacer structure 111 may be formed. Forming the inner spacer structure 111 may include depositing a spacer layer 111 and trimming the spacer layer 111 to form the inner spacer structure 111. As shown in fig. 10, a spacer layer 111 may be blanket deposited over the first ends of the gate spacers 120 and semiconductor layers 438 and 108 by Atomic Layer Deposition (ALD), chemical Vapor Deposition (CVD), and other suitable deposition methods. In some embodiments, the spacer layer 111 may comprise an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, low k materials, and combinations thereof. In some embodiments, spacer layer 111 may comprise a stack of monolayers or insulating layers. In some embodiments, spacer layer 111 may fill recess 911r and may have a thickness in the range of about 5nm to about 10 nm.

The blanket deposition of spacer layer 111 may be followed by trimming spacer layer 111. For example, as shown in fig. 11, the spacer layer 111 may be trimmed by a directional etching process to form the inner spacer structure 111. The trimming process may remove the spacer layer 111 from the outside of the recess 911 r. After the etching process, the spacer layer 111 in the recess 911r may remain and form the inner spacer structure 111. The inner spacer structure 111 may be in contact with the first ends of the semiconductor layers 438 and 108. In some embodiments, the inner spacer structure 111 may have a thickness 111t in the range of about 5nm to about 10 nm. In some embodiments, the end portions of the semiconductor layer 108 may be etched during an etching process that forms the internal spacer structures 111. In some embodiments, the internal spacer structure 111 may reduce parasitic capacitance between the subsequently formed S/D structure 114A and the gate structure 110. The masking layer 844 may be removed after trimming of the spacer layer 111, as shown in fig. 11.

In some embodiments, as shown in fig. 12, semiconductor layers 438 and 108 may be laterally etched after forming the inner spacer structure 111. In some embodiments, a lateral etching process may be used for the semiconductor layers 438 and 438 108 have substantially the same or similar etch rates. In some embodiments, the lateral etching process may be a dry radial etch and include an etchant such as HF, NF ₃ And F ₂ And (3) gas. In some embodiments, the lateral etching process may be performed at a temperature of about 0 ℃ to about 200 ℃ and a pressure of about 0.5 torr to about 20 torr to achieve an isotropic etch having substantially the same or similar etch rate for semiconductor layers 438 and 108. In some embodiments, semiconductor layers 438 and 108 may be etched laterally along the X-axis a distance 108d, the distance 108d being in the range of about 5nm to about 10 nm. In some embodiments, a first end of the first set of semiconductor layers 438 may be protected by the inner spacer structure 111 during the lateral etching process. Lateral etching of semiconductor layers 438 and 108 may reduce the proximity between subsequently formed S/D structure 114B and gate structure 110 and increase the device on-current of nanostructure transistor 102-1 and nanostructure transistor 102-2.

Referring to fig. 3, in operation 340, an epitaxial layer may be formed in contact with the substrate and the second ends of the plurality of semiconductor layers. For example, as shown in fig. 13, an epitaxial layer 112 (e.g., epitaxial layer 112A and epitaxial layer 112B) may be formed in contact with the substrate 104 and the second ends of the semiconductor layers 438 and 108. In some embodiments, epitaxial layer 112 may be epitaxially grown on substrate 104, on the first end of second set of semiconductor layers 108, and on the second end of semiconductor layers 438 and 108. In some embodiments, the deposition may be performed by (i) CVD, such as Low Pressure CVD (LPCVD), atomic Layer CVD (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced Pressure CVD (RPCVD), and other suitable CVD; (ii) a Molecular Beam Epitaxy (MBE) process; (iii) any suitable epitaxy process; or (iv) combinations thereof, to epitaxially grow the epitaxial layer 112. In some embodiments, the epitaxial layer 112 may be formed with a precursor (such as Silane (SiH) at a temperature of about 200 ℃ to about 600 ℃ and at a pressure of about 5 torr to about 300 torr ₄ ) And Dichlorosilane (DCS)) to conformally grow the epitaxial layer 112. Since the inner spacer structure 111 covers the first end of the first set of semiconductor layers 438, the epitaxial layer 112A may include a horizontal portion epitaxially grown on the substrate 104, and a horizontal portion epitaxially grown on the second set of semiconductor layers 108 but not spaced internallyVertical portions on the device structure 111 or the first set of semiconductor layers 438. On the second end of semiconductor layers 438 and 108, epitaxial layer 112B may include a horizontal portion epitaxially grown on substrate 104 and a vertical portion epitaxially grown on semiconductor layers 438 and 108.

In some embodiments, epitaxial layer 112 may comprise an epitaxially grown semiconductor material, such as silicon. Epitaxial layer 112 may be undoped or doped. In some embodiments, epitaxial layer 112 may comprise undoped silicon. In some embodiments, the epitaxial layer 112 may include silicon, and the epitaxial layer 112 may be doped in situ during the epitaxial growth process with n-type dopants (such as phosphorus and arsenic). The n-type dopant may have about 1 x 10 ¹⁹ Atoms/cm ³ Up to about 1X 10 ²¹ Atoms/cm ³ Is a concentration of (3). In some embodiments, the epitaxial layer 112 may include silicon, and the epitaxial layer 112 may be doped in situ during the epitaxial growth process with a p-type dopant (such as boron). The p-type dopant may have about 1 x 10 ¹⁹ Atoms/cm ³ Up to about 1X 10 ²¹ Atoms/cm ³ Is a concentration of (3).

In some embodiments, epitaxial layer 112 may have a thickness 112t in a range from about 1nm to about 10 nm. The ratio of thickness 112t to thickness 108t may be in the range of about 0.1 to about 2. If the thickness 112t is less than about 1nm or the ratio is less than about 0.1, the epitaxial layer 112 may not grow and the subsequently grown S/D structure 114B may be damaged during formation of the gate structure 110. If the thickness 112t is greater than about 10nm or the ratio is greater than about 2, then the proximity between the subsequently formed S/D structure 114B and the gate structure 110 may increase and the device on-current of the nanostructure transistor 102-1 and the nanostructure transistor 102-2 may decrease.

Referring to fig. 3, in operation 350, a first S/D structure is formed in contact with an internal spacer structure, and a second S/D structure is formed on an epitaxial layer. For example, as shown in fig. 14 and 15, a first S/D structure 114A may be formed in contact with the internal spacer structure 111, and a second S/D structure 114B may be formed on the epitaxial layer 112B. In some embodiments, forming the S/D structure 114 may include forming a first S/D epitaxial layer 116 and forming a second S/D epitaxial layer 118.

In some embodiments, the metal may be deposited by (i) CVD, such as LPCVD and other suitable CVD; (ii) MBE; (iii) any suitable epitaxy process; or (iv) combinations thereof to epitaxially grow the first S/D epitaxial layer 116 and the second S/D epitaxial layer 118. In some embodiments, the first S/D epitaxial layer 116 and the second S/D epitaxial layer 118 may be grown by an epitaxial deposition/partial etch process, which may be repeated multiple times. Such a repeated deposition/partial etch process may be referred to as a Cyclical Deposition Etch (CDE) process. The CDE process may reduce epitaxial defects formed during growth and may control the profile of the S/D structure 114. In some embodiments, the first S/D epitaxial layer 116 and the second S/D epitaxial layer 118 may be in-situ doped with n-type dopants or p-type dopants during the epitaxial growth process.

In some embodiments, the S/D structure 114 may comprise silicon, and the S/D structure 114 may be doped in situ during the epitaxial growth process using n-type dopants (such as phosphorus and arsenic). For n-type in-situ doping, n-type doping precursors such as phosphine, arsine and other n-type doping precursors may be used. In some embodiments, each of the multiple epitaxial layers of the S/D structure 114 may have a different dopant concentration. For example, the first S/D epitaxial layer 116 may include a silicon nitride layer of about 1 x 10 ¹⁹ Atoms/cm ³ Up to about 1X 10 ²¹ Atoms/cm ³ Is doped with arsenide or phosphide. The second S/D epitaxial layer 118 may include a silicon nitride layer of about 1 x 10 ²¹ Atoms/cm ³ Up to about 1X 10 ²² Atoms/cm ³ Is doped with phosphide.

In some embodiments, the S/D structure 114 may comprise silicon, silicon germanium, or III-V material (e.g., indium antimonide or indium gallium antimonide), and the S/D structure 114 may be doped in-situ during the epitaxial growth process using p-type dopants such as boron, indium, and gallium. For p-type in-situ doping, p-type doping precursors such as diborane, boron trifluoride and other p-type doping precursors may be used. In some embodiments, each of the multiple epitaxial layers of the S/D structure 114 may have a different composition, e.g., a different dopant concentration and/or no The same germanium concentration. In some embodiments, the first S/D epitaxial layer 116 may have a lower Ge concentration than the second S/D epitaxial layer 118 to prevent lattice mismatch and dislocation defects. For example, the first S/D epitaxial layer 116 may include silicon germanium having a germanium concentration of about 0 to about 30% and doped with a concentration of about 1 x 10 ²⁰ Atoms/cm ³ Up to about 1X 10 ²¹ Atoms/cm ³ Is a boron of (a). The second S/D epitaxial layer 118 may comprise silicon germanium having a germanium concentration of about 20% to about 100% and doped with a concentration of about 1 x 10 ²¹ Atoms/cm ³ Up to about 2X 10 ²¹ Atoms/cm ³ Is a boron of (a).

The S/D structure 114B may be epitaxially grown with reduced dislocation defects using the epitaxial layer 112B and the second ends of the semiconductor layers 438 and 108 on the substrate 104. The S/D structure 114B may include a first S/D epitaxial layer 116B and a second S/D epitaxial layer 118B. In some embodiments, the first S/D epitaxial layer 116B and the second S/D epitaxial layer 118B may include silicon, and may be in situ doped with n-type dopants having different concentrations. In some embodiments, the first S/D epitaxial layer 116B and the second S/D epitaxial layer 118B may include silicon germanium having different germanium concentrations, and may be in situ doped with p-type dopants having different concentrations. In some embodiments, epitaxial layer 112B may reduce dislocation defects in S/D structure 114B by about 50% to about 80%. The reduction of the dislocation defects in the S/D structure 114B may reduce the resistance of the S/D structure 114B, increase the strain placed on the nanostructures 108, and increase the device on-current of the nanostructure transistor 102-1 and the nanostructure transistor 102-2.

Forming S/D structure 114 may be followed by forming ILD layer 136, as shown in fig. 16. In some embodiments, ILD layer 136 may comprise a dielectric material deposited using a deposition method suitable for flowable dielectric materials. In some embodiments, the dielectric material may include silicon oxide.

Formation of ILD layer 136 may be followed by formation of gate structure 110. For example, as shown in fig. 16 and 17, a gate structure 110 surrounding the second set of semiconductor layers 108 may be formed. In some embodiments, forming the gate structure 110 may include removing the gate cap structure 542, the sacrificial gate structure 510, and the first set of semiconductor layers 438, as shown in fig. 16, and depositing the gate dielectric layer 122 and the metal gate structure 124, as shown in fig. 17.

In some embodiments, the gate cap structure 542 and the sacrificial gate structure 510 may be removed in one or more etching processes. In some embodiments, the etching process may include a dry etching process, a wet etching process, or other suitable etching process to remove the gate capping structure 542 and the sacrificial gate structure 510 without removing the gate spacer 120. After removing the gate cap structure 542 and the sacrificial gate structure 510, the first set of semiconductor layers 438 may be exposed for a subsequent etching process.

In some embodiments, the first set of semiconductor layers 438 may be removed by a selective etching process. In some embodiments, the first set of semiconductor layers 438 may have a higher etch selectivity than the second set of semiconductor layers 108, the gate spacers 120, the epitaxial layer 112, and the inner spacer structure 111. In some embodiments, due to the high etch selectivity, the selective etch process may not remove the epitaxial layer 112, the internal spacer structure 111, or the second set of semiconductor layers 108 after removing the first set of semiconductor layers 438. Thus, the epitaxial layer 112B may protect the S/D structure 114B and prevent damage to the S/D structure 114B. The internal spacer structure 111 may protect the S/D structure 114A and prevent damage to the S/D structure 114A. After the selective etching process, the first set of semiconductor layers 438 may be removed and openings 1610 may be formed over and around the second set of semiconductor layers 108.

Referring to fig. 17, a gate structure 110 may be formed in the opening 1610 and on the second set of semiconductor layers 108. The gate structure 110 may surround the semiconductor layer 108 and may control a channel current flowing through the semiconductor layer 108. In some embodiments, forming the gate structure 110 may include forming a gate dielectric layer 122 and forming a metal gate structure 124.

In some embodiments, forming gate dielectric layer 122 may include forming an interfacial layer on semiconductor layer 108 and forming a high-k dielectric layer on the interfacial layer. As shown in fig. 17, an interfacial layer and a high-k dielectric layer may surround each semiconductor layer 108. In some embodiments, the interfacial layerMay comprise silicon oxide. In some embodiments, the high-k dielectric layer may include HfO ₂ 、ZrO ₂ Or other suitable dielectric material. In some embodiments, forming the metal gate structure 124 may include forming one or more work function layers and forming a gate electrode. Depending on the spacing between adjacent semiconductor layers 108, one or more work function layers and gate electrodes may fill the spacing between adjacent semiconductor layers 108. After forming the gate structure 110, as shown in fig. 17, an end portion of the semiconductor layer 108 may be aligned with a first side (e.g., drain side) of the gate structure 110 due to the lateral etching of the semiconductor layer 438 and the semiconductor layer 108 described above.

The formation of gate structure 110 may be followed by the formation of S/D contact structure 128, as shown in fig. 17. In some embodiments, forming S/D contact structure 128 may include etching through ILD layer 136 to expose S/D structure 114, forming metal silicide layer 130 on exposed S/D structure 114, and forming metal contact 132 on metal silicide layer 130. Examples of metals for forming the metal silicide layer 130 may include cobalt, titanium, and nickel. In some embodiments, the metal contacts 132 may include, for example, tungsten, cobalt, aluminum, copper, titanium, tantalum, silver, ruthenium, metal alloys, or combinations thereof. The formation of the S/D contact structures 128 may be followed by the formation of dielectric layers, the formation of interconnects, and other processes, which are not described in detail for simplicity.

In some embodiments, fig. 18-22 illustrate cross-sectional views of a semiconductor device 100 having another asymmetric S/D design. In some embodiments, after forming the internal spacer structure 111 as shown in fig. 11, the epitaxial layer 112 may be formed on the substrate 104 and the semiconductor layer 438 and the semiconductor layer 108 without laterally etching the semiconductor layer 438 and the semiconductor layer 108, as shown in fig. 18. An S/D structure 114 may be formed on the epitaxial layer 112 as shown in fig. 19 and 20. Gate structure 110, ILD layer 136, and S/D contact structure 128 may be formed on semiconductor layer 108 and S/D structure 114, as shown in fig. 21 and 22. The process of forming epitaxial layer 112, S/D structure 114, gate structure 110, ILD layer 136, and S/D contact structure 128 is described above. In some embodiments, fig. 18-22 depict a fabrication process for forming epitaxial layer 112, S/D structure 114, gate structure 110, ILD layer 136, and S/D contact structure 128 without laterally etching semiconductor layers 438 and 108. Since the semiconductor layer 438 and the semiconductor layer 108 are not laterally etched in fig. 18, the first end portion of the semiconductor layer 108 may be under the gate spacer 120 as shown in fig. 18 to 22. In some embodiments, not laterally etching semiconductor layer 438 and semiconductor layer 108 may simplify the manufacturing process of semiconductor device 100 and reduce manufacturing costs. In some embodiments, not laterally etching semiconductor layer 438 and semiconductor layer 108 may increase the proximity between S/D structure 114 and gate structure 110 and reduce the device on-current of nanostructure transistor 102-1 and nanostructure transistor 102-2.

In some embodiments, fig. 23-27 illustrate cross-sectional views of a semiconductor device 100 having yet another asymmetric S/D design. In some embodiments, after laterally etching the semiconductor layer 438 and the semiconductor layer 108 as shown in fig. 11, an epitaxial layer 112B may be formed on one end (e.g., a source side) of the semiconductor layer 438 and the semiconductor layer 108 as shown in fig. 23. In some embodiments, a mask layer may be patterned to cover the first ends of semiconductor layer 438 and semiconductor layer 108 in fig. 23, and epitaxial layer 112B may be epitaxially grown on substrate 104 and the second ends of semiconductor layer 438 and semiconductor layer 108. An S/D structure 114 may be formed on the epitaxial layer 112B, the semiconductor layer 108, and the substrate 104, as shown in fig. 24 and 25. Gate structure 110, ILD layer 136, and S/D contact structure 128 may be formed on semiconductor layer 108 and S/D structure 114, as shown in fig. 26 and 27. The process of forming epitaxial layer 112B, S/D structure 114, gate structure 110, ILD layer 136, and S/D contact structure 128 is described above. In some embodiments, fig. 23-27 depict a fabrication process for forming epitaxial layer 112, S/D structure 114, gate structure 110, ILD layer 136, and S/D contact structure 128 with epitaxial layer 112B on one end of semiconductor layer 438 and semiconductor layer 108. In some embodiments, forming epitaxial layer 112B on one end of semiconductor layer 438 and semiconductor layer 108 may reduce the proximity between S/D structure 114A and gate structure 110 and reduce the device on-current of nanostructure transistor 102-1 and nanostructure transistor 102-2. In some embodiments, forming epitaxial layer 112B on one end of semiconductor layer 438 and semiconductor layer 108 may increase the complexity of the manufacturing process of semiconductor device 100 and thus increase the manufacturing cost.

Various embodiments of the present invention provide an exemplary method of forming an asymmetric S/D design for semiconductor device 100. The semiconductor device 100 may have a nanostructure 108 serving as a channel and a gate structure 110 surrounding the nanostructure 108. The internal spacer structure 111 may be in contact with a first side (e.g., drain side) of the gate structure 110, and the internal spacer structure 111 may be disposed between the gate structure 110 and the S/D structure 114A. The epitaxial layer 112B may be in contact with a second side (e.g., source side) of the gate structure 110, and the epitaxial layer 112B may be disposed between the gate structure 110 and the S/D structure 114B. The second side may be opposite the first side. With the epitaxial layer 112B on the source side, dislocation defects in the S/D structure 114B may be reduced by about 50% to about 80%, the resistance of the S/D structure 114B may be significantly reduced, the proximity between the S/D structure 114B and the gate structure 110 may be reduced, the strain applied to the nanostructures 108 may be improved, and the device current of the semiconductor device 100 may be increased. In addition, the internal spacer structure 111 on the drain side may reduce parasitic capacitance between the gate structure 110 and the S/D structure 114A. The asymmetric S/D design may improve the device performance of semiconductor device 100, for example, by about 5% to about 20% for a p-type nanostructured transistor device and about 0.5% to about 5% for an n-type nanostructured transistor device.

In some embodiments, a semiconductor structure includes a plurality of semiconductor layers on a substrate, a gate structure surrounding the plurality of semiconductor layers, an internal spacer structure between the plurality of semiconductor layers and in contact with a first side of the gate structure, and an epitaxial layer in contact with a second side of the gate structure. The second side is opposite to the first side.

In some embodiments, the epitaxial layer is in contact with the substrate.

In some embodiments, the semiconductor structure further includes a source/drain (S/D) structure in contact with the epitaxial layer.

In some embodiments, the semiconductor structure further comprises: an additional epitaxial layer in contact with the plurality of semiconductor layers and the internal spacer structure; and source/drain structures in contact with the additional epitaxial layer and the internal spacer structures.

In some embodiments, the semiconductor structure further comprises: a first source/drain structure in contact with the internal spacer structure and the plurality of semiconductor layers; and a second source/drain structure in contact with the epitaxial layer.

In some embodiments, the inner spacer structure is surrounded by end portions of the plurality of semiconductor layers.

In some embodiments, end portions of the plurality of semiconductor layers are aligned with the first side of the gate structure.

In some embodiments, the epitaxial layer comprises a silicon epitaxial layer doped with a dopant.

In some embodiments, the epitaxial layer has a thickness in the range of about 1nm to about 10 nm.

In some embodiments, a semiconductor device includes a plurality of channel structures on a substrate, a gate structure surrounding the plurality of channel structures, an internal spacer structure in contact with the gate structure and adjacent a first end of the plurality of channel structures, a gate spacer on a sidewall of the gate structure and above the plurality of channel structures, and an epitaxial layer in contact with the gate structure and a second end of the plurality of channel structures. The second end is opposite the first end.

In some embodiments, the semiconductor device further includes a source/drain (S/D) structure in contact with the epitaxial layer.

In some embodiments, the semiconductor device further comprises: an additional epitaxial layer in contact with the first ends of the plurality of channel structures; and source/drain structures in contact with the additional epitaxial layer and the internal spacer structures.

In some embodiments, the semiconductor device further comprises: a first source/drain structure in contact with the internal spacer structure and a first end of the plurality of channel structures; and a second source/drain structure in contact with the epitaxial layer.

In some embodiments, a method includes forming a plurality of semiconductor layers on a substrate. The plurality of semiconductor layers includes a first group of semiconductor layers and a second group of semiconductor layers stacked in an alternating configuration. The method further includes replacing a portion of the first set of semiconductor layers with an internal spacer structure at a first end of the plurality of semiconductor layers, forming an epitaxial layer in contact with the substrate and a second end of the plurality of semiconductor layers, and forming a first S/D structure in contact with the internal spacer structure and forming a second S/D structure on the epitaxial layer. The second end is opposite the first end.

In some embodiments, the method further includes replacing the first set of semiconductor layers with a gate structure, wherein the gate structure surrounds the second set of semiconductor layers and is in contact with the internal spacer structure and the epitaxial layer.

In some embodiments, replacing portions of the first set of semiconductor layers with the inner spacer structures includes: covering the second ends of the plurality of semiconductor layers with a mask layer; laterally etching portions of the first set of semiconductor layers; depositing a spacer layer on a first end of the plurality of semiconductor layers; and removing the spacer layer from the second set of semiconductor layers.

In some embodiments, forming the epitaxial layer includes: laterally etching the plurality of semiconductor layers; and epitaxially growing a silicon layer on the substrate and the plurality of semiconductor layers.

In some embodiments, forming the epitaxial layer includes: laterally etching the first set of semiconductor layers and the second set of semiconductor layers; covering the first end portions of the plurality of semiconductor layers with a mask layer; and epitaxially growing a silicon layer on the substrate and the second ends of the plurality of semiconductor layers.

It is to be understood that the abstract of the detailed description, and not the disclosure, is intended to be used to interpret the scope of the present invention. The abstract of the disclosure may set forth one or more, but not all possible embodiments of the invention contemplated by the inventors, and thus is not intended to limit the scope of the invention in any way.

The foregoing outlines features of a drop-on embodiment so that those skilled in the art may better understand aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor structure, comprising:

a plurality of semiconductor layers on the substrate;

a gate structure surrounding the plurality of semiconductor layers;

an internal spacer structure located between the plurality of semiconductor layers and in contact with a first side of the gate structure; and

and an epitaxial layer in contact with a second side of the gate structure, wherein the second side is opposite to the first side.

2. The semiconductor structure of claim 1, wherein the epitaxial layer is in contact with the substrate.

3. The semiconductor structure of claim 1, further comprising a source/drain (S/D) structure in contact with the epitaxial layer.

4. The semiconductor structure of claim 1, further comprising:

an additional epitaxial layer in contact with the plurality of semiconductor layers and the internal spacer structure; and

source/drain structures in contact with the additional epitaxial layer and the internal spacer structures.

5. The semiconductor structure of claim 1, further comprising:

a first source/drain structure in contact with the internal spacer structure and the plurality of semiconductor layers; and

and a second source/drain structure in contact with the epitaxial layer.

6. The semiconductor structure of claim 1, wherein the inner spacer structure is surrounded by end portions of the plurality of semiconductor layers.

7. The semiconductor structure of claim 1, wherein end portions of the plurality of semiconductor layers are aligned with the first side of the gate structure.

8. The semiconductor structure of claim 1, wherein the epitaxial layer comprises a silicon epitaxial layer doped with a dopant.

9. A semiconductor device, comprising:

a plurality of channel structures located on the substrate;

a gate structure surrounding the plurality of channel structures;

an internal spacer structure in contact with the gate structure and adjacent to first ends of the plurality of channel structures;

a gate spacer on sidewalls of the gate structures and over the plurality of channel structures; and

and an epitaxial layer in contact with second ends of the gate structures and the plurality of channel structures, wherein the second ends are opposite to the first ends.

10. A method of forming a semiconductor structure, comprising:

forming a plurality of semiconductor layers on a substrate, wherein the plurality of semiconductor layers includes a first group of semiconductor layers and a second group of semiconductor layers stacked in an alternating configuration;

replacing a portion of the first set of semiconductor layers with an internal spacer structure at a first end of the plurality of semiconductor layers;

Forming an epitaxial layer in contact with the substrate and a second end of the plurality of semiconductor layers, wherein the second end is opposite to the first end; and

a first source/drain structure is formed in contact with the internal spacer structure and a second source/drain structure is formed on the epitaxial layer.