CN116631873A - Method for improving device performance through selective epitaxial process - Google Patents
Method for improving device performance through selective epitaxial process Download PDFInfo
- Publication number
- CN116631873A CN116631873A CN202310747110.3A CN202310747110A CN116631873A CN 116631873 A CN116631873 A CN 116631873A CN 202310747110 A CN202310747110 A CN 202310747110A CN 116631873 A CN116631873 A CN 116631873A
- Authority
- CN
- China
- Prior art keywords
- seed crystal
- boron
- device performance
- improving device
- crystal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 61
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052796 boron Inorganic materials 0.000 claims abstract description 35
- 239000013078 crystal Substances 0.000 claims abstract description 26
- 238000000137 annealing Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 239000012159 carrier gas Substances 0.000 claims description 9
- 239000007789 gas Substances 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910003818 SiH2Cl2 Inorganic materials 0.000 claims description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 2
- -1 geH4 Chemical compound 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 3
- 229920005591 polysilicon Polymers 0.000 description 9
- 238000000407 epitaxy Methods 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Recrystallisation Techniques (AREA)
Abstract
The invention provides a method for improving device performance through a selective epitaxial process, which comprises the steps of providing a substrate, wherein a grid is arranged on the substrate, and a U-shaped groove is formed in a source region and a drain region on two sides of the grid; forming a seed crystal layer on the inner wall of the U-shaped groove; growing a buffer layer with high boron concentration on the seed crystal layer; the concentration of boron in the buffer layer is 5E 19-5E 21 atoms/cm < 3 >; the boron in the buffer layer is diffused to the seed crystal layer through high-temperature annealing, so that the concentration of the boron in the seed crystal layer is increased; a cap layer is formed on the buffer layer. According to the method, the buffer layer with high boron concentration is used, and the high-temperature annealing is added, so that boron is diffused into the seed crystal layer, the boron concentration in the seed crystal layer is improved, and the requirement of a device is met.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for improving device performance through a selective epitaxial process.
Background
For the source and drain regions of the 14nm PMOS, a U-shaped groove is formed by dry etching, siGeB is grown in the groove and is divided into three layers, and one layer which is tightly attached to the groove wall is L1 (buffer layer). Due to the low boron concentration of L1, the VT of the device can roll off, and the performance of the device can be influenced. The same problem exists for 14nm NMOS source and drain regions.
Therefore, a new method is required to solve the above problems.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for improving device performance by a selective epitaxy process, which is used to solve the problem in the prior art that the device performance is reduced due to low boron concentration in the source/drain region of the MOS device.
To achieve the above and other related objects, the present invention provides a method for improving device performance by a selective epitaxy process, at least comprising:
step one, providing a substrate, wherein a grid electrode is arranged on the substrate, and U-shaped grooves are formed in source and drain regions on two sides of the grid electrode;
step two, forming a seed crystal layer on the inner wall of the U-shaped groove;
step three, growing a buffer layer with high boron concentration on the seed crystal layer; the concentration of boron in the buffer layer is 5E 19-5E 21 atoms/cm < 3 >;
step four, diffusing the boron in the buffer layer to the seed crystal layer through high-temperature annealing so as to improve the concentration of the boron in the seed crystal layer;
and fifthly, forming a cap layer on the buffer layer.
Preferably, the method for forming the U-shaped groove in the first step is dry etching.
Preferably, the gate in the first step is composed of a polysilicon structure, silicon nitride on top of the polysilicon structure, and a sidewall attached to the sidewall of the polysilicon structure.
Preferably, in the second step, an epitaxial method is adopted to grow the seed crystal layer on the inner wall of the U-shaped groove, and the process conditions of the epitaxial method are as follows: the temperature is 500-800 ℃, and the pressure is 1-100 torr.
Preferably, the carrier gas used in the epitaxy method in the second step comprises SiH2Cl2.SiH4, geH4, PH3, HCL, H2, N2; the other gas flows are respectively 1 sccm-1000 sccm except the H2 and N2 carrier gas, and the gas flows of the H2 and N2 carrier gas are respectively 1 slm-50 slm.
Preferably, the buffer layer in the third step is a SiGeB layer.
Preferably, the high temperature annealing temperature in the fourth step is 500-1100 ℃.
Preferably, the high temperature annealing in the fourth step is implemented by using an epitaxial chamber or an RTP chamber.
Preferably, in step four, the boron concentration in the seed layer is raised to greater than 1E20 atoms/cm 3.
As described above, the method for improving device performance by selective epitaxy process of the present invention has the following beneficial effects: according to the method, the buffer layer with high boron concentration is used, and the high-temperature annealing is added, so that boron is diffused into the seed crystal layer, the boron concentration in the seed crystal layer is improved, and the requirement of a device is met.
Drawings
FIGS. 1to 4 are schematic views showing the structure of each stage of the method for improving the performance of a device by a selective epitaxy process according to the present invention;
fig. 5 is a flow chart illustrating a method for improving device performance by a selective epitaxial process in accordance with the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1to 5. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The invention provides a method for improving the performance of a device through a selective epitaxial process, as shown in fig. 5, fig. 5 shows a flow chart of the method for improving the performance of the device through the selective epitaxial process, and the method at least comprises the following steps:
step one, providing a substrate, wherein a grid electrode is arranged on the substrate, and U-shaped grooves are formed in source and drain regions on two sides of the grid electrode;
in the first step of the present embodiment, the method for forming the U-shaped groove is dry etching.
In the first step of the present embodiment, the gate is further comprised of a polysilicon structure, silicon nitride on top of the polysilicon structure, and a sidewall attached to the sidewall of the polysilicon structure.
As shown in fig. 1, in the step one, a gate is provided on the substrate 01, a U-shaped groove 03 is formed in a source-drain region at two sides of the gate, the method for forming the U-shaped groove 03 is dry etching, and the gate is composed of a polysilicon structure 02, silicon nitride at the top of the polysilicon structure 02, and a sidewall attached to the sidewall of the polysilicon structure.
Step two, forming a seed crystal layer on the inner wall of the U-shaped groove;
in the second step of the present embodiment, the seed crystal layer is grown on the inner wall of the U-shaped groove by adopting an epitaxy method, and the process conditions of the epitaxy method are as follows: the temperature is 500-800 ℃, and the pressure is 1-100 torr.
As shown in fig. 1, in the second step, a seed layer 04 is formed on the inner wall of the U-shaped groove 03.
Further, the carrier gas used in the epitaxy method in the second step of the present embodiment includes sih2cl2.sih4, geH4, PH3, HCL, H2, N2; the other gas flows are respectively 1 sccm-1000 sccm except the H2 and N2 carrier gas, and the gas flows of the H2 and N2 carrier gas are respectively 1 slm-50 slm.
Step three, growing a buffer layer with high boron concentration on the seed crystal layer; the concentration of boron in the buffer layer is 5E 19-5E 21 atoms/cm < 3 >;
in the third embodiment, the buffer layer is a SiGeB layer.
As shown in fig. 2, this step three grows a buffer layer 05 of high boron concentration on the seed layer 04; the concentration of boron in the buffer layer 05 is 5E 19-5E 21 atoms/cm 3; the buffer layer 05 is a SiGeB layer.
Step four, diffusing the boron in the buffer layer to the seed crystal layer through high-temperature annealing so as to improve the concentration of the boron in the seed crystal layer; further, the high temperature annealing temperature in the fourth step of the present embodiment is 500 to 1100 ℃.
And step four, the high-temperature annealing is realized by adopting an epitaxial cavity or an RTP cavity.
The invention further provides that in step four of this embodiment, the boron concentration in the seed layer is raised to greater than 1E20atom/cm3.
As shown in fig. 3, this step is performed by high temperature annealing to diffuse boron in the buffer layer 05 into the seed layer 04, so as to increase the concentration of boron in the seed layer 04; further, the high temperature annealing temperature in the fourth step of the present embodiment is 500 to 1100 ℃. The high-temperature annealing is realized by adopting an epitaxial cavity or an RTP cavity. The boron concentration in the seed layer 04 is raised to greater than 1E20atom/cm3.
And fifthly, forming a cap layer on the buffer layer.
As shown in fig. 4, in the fifth step, a cap layer 06 is formed on the buffer layer 05.
In summary, the method of the invention diffuses boron into the seed crystal layer by the buffer layer with high boron concentration and the high-temperature annealing, so that the boron concentration in the seed crystal layer is improved, which is beneficial to meeting the requirements of devices. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (9)
1. A method for improving device performance by a selective epitaxial process, comprising at least:
step one, providing a substrate, wherein a grid electrode is arranged on the substrate, and U-shaped grooves are formed in source and drain regions on two sides of the grid electrode;
step two, forming a seed crystal layer on the inner wall of the U-shaped groove;
step three, growing a buffer layer with high boron concentration on the seed crystal layer; the concentration of boron in the buffer layer is 5E 19-5E 21 atoms/cm < 3 >;
step four, diffusing the boron in the buffer layer to the seed crystal layer through high-temperature annealing so as to improve the concentration of the boron in the seed crystal layer;
and fifthly, forming a cap layer on the buffer layer.
2. The method of improving device performance by a selective epitaxial process of claim 1, wherein: and in the first step, the method for forming the U-shaped groove is dry etching.
3. The method of improving device performance by a selective epitaxial process of claim 1, wherein: the grid electrode in the first step is composed of a polycrystalline silicon structure, silicon nitride on the top of the polycrystalline silicon structure and a side wall attached to the side wall of the polycrystalline silicon structure.
4. The method of improving device performance by a selective epitaxial process of claim 1, wherein: in the second step, an epitaxial method is adopted to grow the seed crystal layer on the inner wall of the U-shaped groove, and the process conditions of the epitaxial method are as follows: the temperature is 500-800 ℃, and the pressure is 1-100 torr.
5. The method of improving device performance by a selective epitaxial process of claim 1, wherein: the carrier gas used in the epitaxial method in the second step comprises SiH2Cl2.SiH4, geH4, PH3, HCL, H2 and N2; the other gas flows are respectively 1 sccm-1000 sccm except the H2 and N2 carrier gas, and the gas flows of the H2 and N2 carrier gas are respectively 1 slm-50 slm.
6. The method of improving device performance by a selective epitaxial process of claim 1, wherein: and step three, the buffer layer is a SiGeB layer.
7. The method of improving device performance by a selective epitaxial process of claim 1, wherein: the high-temperature annealing temperature in the fourth step is 500-1100 ℃.
8. The method of improving device performance by a selective epitaxial process of claim 1, wherein: and step four, the high-temperature annealing is realized by adopting an epitaxial cavity or an RTP cavity.
9. The method of improving device performance by a selective epitaxial process of claim 1, wherein: and step four, the concentration of boron in the seed crystal layer is increased to be more than 1E20atom/cm < 3 >.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310747110.3A CN116631873A (en) | 2023-06-21 | 2023-06-21 | Method for improving device performance through selective epitaxial process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310747110.3A CN116631873A (en) | 2023-06-21 | 2023-06-21 | Method for improving device performance through selective epitaxial process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116631873A true CN116631873A (en) | 2023-08-22 |
Family
ID=87621366
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310747110.3A Pending CN116631873A (en) | 2023-06-21 | 2023-06-21 | Method for improving device performance through selective epitaxial process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116631873A (en) |
-
2023
- 2023-06-21 CN CN202310747110.3A patent/CN116631873A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7611973B2 (en) | Methods of selectively forming epitaxial semiconductor layer on single crystalline semiconductor and semiconductor devices fabricated using the same | |
| US8853060B1 (en) | Epitaxial process | |
| US7175709B2 (en) | Epitaxy layer and method of forming the same | |
| US20080233722A1 (en) | Method of forming selective area compound semiconductor epitaxial layer | |
| KR20050031455A (en) | Method of forming nanocrystals | |
| US20150097235A1 (en) | Semiconductor device | |
| CN111599764A (en) | Method for manufacturing embedded epitaxial layer | |
| US8642414B2 (en) | MOS transistor structure with in-situ doped source and drain and method for forming the same | |
| US9831251B2 (en) | Method of fabricating semiconductor device and semiconductor device fabricated thereby | |
| US7560350B2 (en) | Method for forming strained semiconductor device and method for forming source/drain region | |
| US20190157425A1 (en) | Semiconductor device and fabrication method thereof | |
| CN116344590B (en) | Semiconductor device and manufacturing method thereof | |
| CN116631873A (en) | Method for improving device performance through selective epitaxial process | |
| CN113130323B (en) | Manufacturing method of embedded SiP epitaxial layer | |
| US11476114B2 (en) | Epitaxial growth process for semiconductor device and semiconductor device comprising epitaxial layer formed by adopting the same | |
| US10096518B2 (en) | Semiconductor structures and fabrication methods thereof | |
| US20070128819A1 (en) | Film forming method and method of manufacturing semiconductor device | |
| US20170294515A1 (en) | Recess liner for silicon germanium fin formation | |
| CN111697051B (en) | Semiconductor structure and forming method thereof | |
| CN113013232A (en) | Method for improving device performance through selective epitaxy | |
| US20060148139A1 (en) | Selective second gate oxide growth | |
| CN116190239A (en) | Method for improving device performance through selective epitaxy | |
| CN111599763A (en) | Method for manufacturing embedded epitaxial layer | |
| US10090170B2 (en) | Semiconductor fabrication method including non-uniform cover layer | |
| CN107665807B (en) | Semiconductor device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |