CN113113496B - 垂直型器件的制作方法 - Google Patents

垂直型器件的制作方法 Download PDF

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CN113113496B
CN113113496B CN202010027027.5A CN202010027027A CN113113496B CN 113113496 B CN113113496 B CN 113113496B CN 202010027027 A CN202010027027 A CN 202010027027A CN 113113496 B CN113113496 B CN 113113496B
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程凯
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Enkris Semiconductor Inc
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Abstract

本申请提供一种垂直型器件的制作方法，以提高垂直型器件的反向击穿电压。该制备方法包括：在N型重掺杂层的正面形成多个第一凹槽；在第一凹槽内以及N型重掺杂层的正面形成N型轻掺杂层，在N型轻掺杂层上形成第二凹槽，第二凹槽位置对应第一凹槽形成；在第二凹槽内以及N型轻掺杂层的正面形成P型半导体层；平坦化P型半导体层，除去位于N型轻掺杂层的正面的P型半导体层，仅保留第二凹槽内的P型半导体层；在上述结构上形成钝化层，钝化层形成有第三凹槽，第三凹槽位于第二凹槽内的部分P型半导体层上、以及相邻的两个第二凹槽之间的N型轻掺杂层上第三凹槽的深度等于钝化层的厚度；形成第一电极和第二电极。

Description

垂直型器件的制作方法
技术领域
本申请涉及半导体领域，尤其涉及一种垂直型器件的制作方法。
背景技术
目前，半导体肖特基二极管在现代电子工业有广泛的应用，其具有可靠性好、电路设计容易等优点，广泛应用于电力电子、微波射频等领域。半导体肖特基二极管一个重要技术指标是二极管反向击穿电压，二极管反向击穿电压限制了器件的性能及可靠性。
随着对应用于越来越小型化的电子装置的具有超高集成、超高速度、以及超低功率的半导体器件的需求，垂直型半导体肖特基二极管越来越受到关注。而在制作垂直型半导体肖特基二极管时，很多因素会影响反向击穿电压，如在运用刻蚀工艺时会造成结构的不均匀性及外延层缺陷增加的不良影响等。
因此，如何进一步提高垂直型半导体肖特基二极管的反向击穿电压，仍然是目前亟待解决的难题。
发明内容
本申请提供一种垂直型器件的制作方法，能够提高垂直型器件的反向击穿电压。
为实现上述目的，根据本申请实施例提供一种半导体结构的制备方法，所述制备方法包括：
提供N型重掺杂层，所述N型重掺杂层具有相对的正面与背面，在所述N型重掺杂层的正面形成多个第一凹槽；
在所述第一凹槽内以及所述N型重掺杂层的正面形成N型轻掺杂层，所述N型轻掺杂层远离所述N型重掺杂层的一面形成第二凹槽，所述第二凹槽位置对应所述第一凹槽形成；
在所述第二凹槽内以及所述N型轻掺杂层的正面形成P型半导体层；
平坦化所述P型半导体层，除去位于所述N型轻掺杂层的正面的部分所述P型半导体层，仅保留所述第二凹槽内的所述P型半导体层；
在上述结构上形成钝化层，所述钝化层形成有第三凹槽，所述第三凹槽位于所述第二凹槽内的部分所述P型半导体层上、以及相邻的两个所述第二凹槽之间的所述N型轻掺杂层上，所述第三凹槽的深度等于所述钝化层的厚度；
形成第一电极，所述第一电极设置于部分所述钝化层上、以及所述第三凹槽内，使得所述第一电极与所述第二凹槽内的所述P型半导体层部分接触，且与位于相邻的两个所述第二凹槽之间的所述N型轻掺杂层接触；
形成第二电极，所述第二电极设置于所述N型重掺杂层的背面。
可选的，在所述N型轻掺杂层生长过程中形成所述第二凹槽。
可选的，所述N型重掺杂层的掺杂浓度在1018/cm3量级以上，所述N型轻掺杂层的掺杂浓度在1018/cm3量级以下。
可选的，所述N型重掺杂层和N型轻掺杂层之间可以包括缓冲层。
可选的，在所述钝化层形成有第三凹槽中，所述第三凹槽通过刻蚀形成。
可选的，所述N型重掺杂层为GaN基材料；和/或，
所述N型轻掺杂层为GaN基材料；和/或，
所述P型半导体层为GaN基材料。
可选的，所述N型重掺杂层、所述N型轻掺杂层和所述P型半导体层的材料均相同或均不同。
可选的，采用化学机械抛光法平坦化所述P型半导体层。
上述实施例的垂直型器件的制作方法中，通过制作N型重掺杂层和N型轻掺杂层，以及在所述N型重掺杂层的正面形成多个第一凹槽以便于在N型轻掺杂层与第一凹槽对应位置形成第二凹槽，相对于传统制作方法减少了刻蚀带来的不均匀性及对外延层的影响，进而能够更接近设计的理论目的，在缺陷减少的过程中，导电条件降低，即载流子减少，而实现反向击穿电压的提高。同时P型半导体的设置及电极场板的存在可以减弱电场尖峰的产生，从而达到减少漏电效果。
附图说明
图1是本申请的实施例1的垂直型器件的制备方法的流程图。
图2(a)-图2(g)是本申请的实施例1的垂直型器件的制备方法的工艺流程图。
图3是本申请的实施例1的垂直型器件的制备方法制得的垂直型器件的结构示意图。
图4(a)-图4(b)是本申请的实施例2的垂直型器件的制备方法的部分工艺流程图。
图5是本申请的实施例2的垂直型器件的制备方法制得的垂直型器件的结构示意图。
附图标记说明
N型重掺杂层11
N型重掺杂层的正面11a
N型重掺杂层的背面11b
第一凹槽12
N型缓冲层13
N型缓冲层的正面13a
缓冲层凹槽131
N型轻掺杂层14
N型轻掺杂层的正面14a
第二凹槽15
P型半导体层20
钝化层30
第三凹槽31
阳极40
阴极50
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。除非另作定义，本申请使用的技术术语或者科学术语应当为本申请所属领域内具有一般技能的人士所理解的通常意义。本申请说明书以及权利要求书中使用的“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而且可以包括电性的连接，不管是直接的还是间接的。“多个”包括两个，相当于至少两个。在本申请说明书和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
实施例1
如图1、以及图2(a)-图2(g)所示，本实施例提供一种垂直型器件的制备方法，所述制备方法包括：
步骤100：提供N型重掺杂层，所述N型重掺杂层具有相对的正面与背面，在所述N型重掺杂层的正面形成多个第一凹槽；
步骤200：在所述第一凹槽内以及所述N型重掺杂层的正面形成N型轻掺杂层，所述N型轻掺杂层远离所述N型重掺杂层的一面形成第二凹槽，所述第二凹槽位置对应所述第一凹槽形成；
步骤300：在所述第二凹槽内以及所述N型轻掺杂层的正面形成P型半导体层；
步骤400：平坦化所述P型半导体层，除去位于所述N型轻掺杂层的正面的部分所述P型半导体层，仅保留所述第二凹槽内的所述P型半导体层；
步骤500：在上述结构上形成钝化层，所述钝化层形成有第三凹槽，所述第三凹槽位于所述第二凹槽内的部分所述P型半导体层上、以及相邻的两个所述第二凹槽之间的所述N型轻掺杂层上，所述第三凹槽的深度等于所述钝化层的厚度；
步骤600：形成第一电极，所述第一电极设置于部分所述钝化层上、以及所述第三凹槽内，使得所述第一电极与所述第二凹槽内的所述P型半导体层部分接触，且与位于相邻的两个所述第二凹槽之间的所述N型轻掺杂层接触；
形成第二电极，所述第二电极设置于所述N型重掺杂层的背面。
在步骤100中，如图2(a)所示，提供N型重掺杂层11，N型重掺杂层11具有相对的正面11a与背面11b。N型重掺杂层11的掺杂浓度在1018/cm3量级以上。在形成N型重掺杂层11后，在N型重掺杂层11的正面11a通过刻蚀形成多个第一凹槽12。在本实施例中，第一凹槽12的数量不作特别限制，本领域人员应当知晓，可根据不同的材料参数，设置不同的凹槽11的个数，以能够达到技术效果为目的。
N型重掺杂层11为GaN基材料。GaN基N型重掺杂层11可以为单层结构，也可以为叠层结构。每层的材料可以为GaN、AlGaN或AlInGaN，或者是其它包括Ga原子、N原子的半导体材料，或者上述至少两种材料的或混合物。
接续，在步骤200中，如图2(b)所示，沿生长方向F，在第一凹槽12内以及N型重掺杂层的正面11a形成N型轻掺杂层14，在所述N型轻掺杂层生长过程中，N型轻掺杂层14远离N型重掺杂层的一面形成第二凹槽15，即在N型轻掺杂层14的正面14a形成第二凹槽15。N型轻掺杂层14的掺杂浓度在1018/cm3量级以下。在多个第一凹槽12内以及N型重掺杂层11的正面11a生长形成N型轻掺杂层14，由于N型重掺杂层11的正面11a有第一凹槽12，在N型轻掺杂层14生长过程中，N型轻掺杂层14远离N型重掺杂层11的一面对应于第一凹槽12的位置会自然而然地生长形成第二凹槽15。也就是说，第二凹槽15的数量根据第一凹槽12的数量而决定，且与第一凹槽12的数量相同。此外，第二凹槽15的数量可根据上述第一凹槽12的不同而灵活设计。
N型轻掺杂层14为GaN基材料。GaN基N型轻掺杂层14可以为单层结构，也可以为叠层结构。每层的材料可以为GaN、AlGaN或AlInGaN，或者是其它包括Ga原子、N原子的半导体材料，或者上述至少两种材料的或混合物。
这样，通过在N型轻掺杂层14生长过程中形成第二凹槽15，能够进一步减少刻蚀步骤，从而减少了刻蚀带来的不均匀性及对外延层的影响，进而能够更接近设计的理论目的，在缺陷减少的过程中，导电条件降低，即载流子减少，而进一步实现反向击穿电压的提高。
在步骤300中，如图2(c)所示，沿生长方向F，在第二凹槽15内以及N型轻掺杂层14的正面14a形成P型半导体层20。P型半导体层20为GaN基材料。GaN基P型半导体层20可以为单层结构，也可以为叠层结构。每层的材料可以为GaN、AlGaN或AlInGaN，或者是其它包括Ga原子、N原子的半导体材料，或者上述至少两种材料的或混合物。P型半导体层20、N型重掺杂层11和N型轻掺杂层14的材料可以均相同，也可以均不同。
在步骤400中，如图2(d)所示，平坦化P型半导体层20，除去位于N型轻掺杂层14的正面14a的部分P型半导体层20，仅保留第二凹槽15内的P型半导体层20。其中，可以采用化学机械抛光法平坦化P型半导体层20。
在步骤500中，如图2(e)所示，在上述结构上形成钝化层30，在P型半导体层20和部分N型轻掺杂层14的正面14a形成钝化层30。钝化层30为SiO2，但不仅限于SiO2。
如图2(f)所示，在钝化层30形成有第三凹槽31中，所述制作方法包括：在形成钝化层30后，通过刻蚀钝化层30形成第三凹槽31。第三凹槽31位于第二凹槽15内的部分P型半导体层20上、以及相邻的两个第二凹槽15之间的N型轻掺杂层14上，第三凹槽31的深度等于钝化层30的厚度。其中，第三凹槽31的数量小于或等于相邻两个第二凹槽15之间的间隙的数量。此外，第三凹槽31的数量可根据上述第二凹槽15的不同而灵活设计。
在步骤600中，如图2(g)所示，形成第一电极，所述第一电极设置于部分钝化层30上、以及第三凹槽31内，使得所述第一电极与第二凹槽15内的P型半导体层20部分接触，且与位于相邻的两个第二凹槽15之间的N型轻掺杂层14接触，第一电极为阳极40。
形成第二电极，所述第二电极设置于N型重掺杂层11的背面11b，第二电极为阴极50。本申请不对第一电极和第二电极作特别限定，可根据不同的器件种类，设置不同种类的电极。
通过本实施例提供的垂直型器件的制备方法制得的垂直型器件的结构如图3所示。
上述实施例的垂直型器件的制作方法中，通过制作N型重掺杂层和N型轻掺杂层，以及在所述N型重掺杂层的正面形成多个第一凹槽以便于在N型轻掺杂层与第一凹槽对应位置形成第二凹槽，相对于传统制作方法减少了刻蚀带来的不均匀性及对外延层的影响，进而能够更接近设计的理论目的，在缺陷减少的过程中，导电条件降低，即载流子减少，而实现反向击穿电压的提高。
实施例2
如图4(a)和图4(b)所示，本实施例提供的垂直型器件的制备方法与实施例1中的垂直型器件的制备方法的内容基本相同，其不同之处在于，在步骤100之后，以及步骤200之前，所述制备方法包括：
步骤150：如图4(a)所示，在第一凹槽12内以及N型重掺杂层11的正面11a形成生成N型缓冲层13，在N型缓冲层13的远离N型重掺杂层11的一面形成缓冲层凹槽131，缓冲层凹槽131位置对应第一凹槽12形成。
N型缓冲层13为GaN基材料。N型缓冲层13可以为单层结构，也可以为叠层结构。每层的材料可以为GaN、AlGaN或AlInGaN，或者是其它包括Ga原子、N原子的半导体材料，或者上述至少两种材料的或混合物。
接续，将实施例1中的垂直型器件的制备方法的步骤200改为：
如图4(b)所示，在缓冲层凹槽131内以及N型缓冲层13的正面13a形成N型轻掺杂层14，N型轻掺杂层14远离N型缓冲层13的一面形成第二凹槽15，第二凹槽15位置对应缓冲层凹槽131形成。
通过本实施例提供的垂直型器件的制备方法制得的垂直型器件的结构如图5所示。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请保护的范围之内。

Claims (8)

1.一种垂直型器件的制作方法，其特征在于，包括：
提供N型重掺杂层，所述N型重掺杂层具有相对的正面与背面，在所述N型重掺杂层的正面形成多个第一凹槽；
在所述第一凹槽内以及所述N型重掺杂层的正面形成N型轻掺杂层，所述N型轻掺杂层远离所述N型重掺杂层的一面形成第二凹槽，所述第二凹槽位置对应所述第一凹槽形成；
在所述第二凹槽内以及所述N型轻掺杂层的正面形成P型半导体层；
平坦化所述P型半导体层，除去位于所述N型轻掺杂层的正面的部分所述P型半导体层，仅保留所述第二凹槽内的所述P型半导体层；
在上述结构上形成钝化层，所述钝化层形成有第三凹槽，所述第三凹槽位于所述第二凹槽内的部分所述P型半导体层上、以及相邻的两个所述第二凹槽之间的所述N型轻掺杂层上，所述第三凹槽的深度等于所述钝化层的厚度；
形成第一电极，所述第一电极设置于部分所述钝化层上、以及所述第三凹槽内，使得所述第一电极与所述第二凹槽内的所述P型半导体层部分接触，且与位于相邻的两个所述第二凹槽之间的所述N型轻掺杂层接触；
形成第二电极，所述第二电极设置于所述N型重掺杂层的背面。
2.根据权利要求1所述的垂直型器件的制作方法，其特征在于，在所述N型轻掺杂层生长过程中形成所述第二凹槽。
3.根据权利要求1所述的垂直型器件的制作方法，其特征在于，所述N型重掺杂层的掺杂浓度在1018/cm3量级以上，所述N型轻掺杂层的掺杂浓度在1018/cm3量级以下。
4.根据权利要求1所述的垂直型器件的制作方法，其特征在于，所述N型重掺杂层和N型轻掺杂层之间可以包括缓冲层。
5.根据权利要求1所述的垂直型器件的制作方法，其特征在于，在所述钝化层形成有第三凹槽中，所述第三凹槽通过刻蚀形成。
6.根据权利要求1所述的垂直型器件的制作方法，其特征在于，
所述N型重掺杂层为GaN基材料；和/或，
所述N型轻掺杂层为GaN基材料；和/或，
所述P型半导体层为GaN基材料。
7.根据权利要求1所述的垂直型器件的制作方法，其特征在于，所述N型重掺杂层、所述N型轻掺杂层和所述P型半导体层的材料均相同或均不同。
8.根据权利要求1的垂直型器件的制作方法，其特征在于，采用化学机械抛光法平坦化所述P型半导体层。
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