CN113098516A

CN113098516A - Staggered ADC ping-pong pre-sampling holding buffer

Info

Publication number: CN113098516A
Application number: CN202110241518.4A
Authority: CN
Inventors: 郭啸峰; 陈润; 陈振骐; 陈勇刚
Original assignee: Shenzhen Nuoruixin Technology Co ltd
Current assignee: Shenzhen Nuoruixin Technology Co ltd
Priority date: 2021-03-04
Filing date: 2021-03-04
Publication date: 2021-07-09
Anticipated expiration: 2041-03-04
Also published as: CN113098516B

Abstract

The invention relates to a ping-pong pre-sampling hold buffer of an interleaved ADC (analog to digital converter), belonging to the technical field of analog to digital converter circuits in integrated circuit design. The buffer comprises a pre-sample-and-hold buffer circuit of a ping-pong architecture and a ping-pong clock generation circuit in a signal link; the circuit of the pre-sampling holding buffer consists of a first-stage emitter-stage following isolator, a pre-sampling holding circuit and a second-stage source-stage following isolator; the ping-pong clock generating circuit consists of a reset signal phase shift circuit and two frequency dividers which are mirror images of each other. The invention has the advantage that the classical pre-sampling holding buffer does not need to additionally calibrate the sampling delay error of the sub-channel ADC, and simultaneously reduces the speed requirement of the pre-sampling holding buffer by one time by utilizing a ping-pong architecture, thereby realizing more conciseness and robustness and having much lower realization cost.

Description

Staggered ADC ping-pong pre-sampling holding buffer

Technical Field

The invention belongs to the technical field of analog-to-digital converter (ADC) circuits in integrated circuit design, and particularly relates to a ping-pong pre-sampling holding buffer of an interleaved ADC (multichannel time-interleaved ADC).

Background

Interleaved analog-to-digital converter (ADC) architectures are generally suitable for high-speed high-precision ADC applications such as 5G rf chips, ultra-wideband receivers, phased array radars, electronic warfare, and the like. The conversion accuracy requirements for ADCs for these scenarios are typically above 12 bits, while the sampling rate requirements reach several GSPS. For an ADC with high sampling rate and high linearity requirement, a buffer with high driving capability is needed to isolate an ADC sampling capacitor and a sampling switch, and the stray-free dynamic range (SFDR) of the system is improved by injecting a peak to a pre-stage anti-aliasing filter (or a transformer coupling front end) during sampling. Meanwhile, due to the fact that a large delay error exists in the sampling clock between each subchannel ADC of the interleaved ADC, the error can cause the actual sampling signal of each subchannel ADC to generate a sampling error related to the delay error and the signal, and finally, the signal-to-noise-and-distortion ratio (SNDR) of the interleaved ADC can be greatly limited. At present, two schemes are used to solve the limitation of the delay error, the first scheme is to eliminate the delay error between the sub-channels by an extra heavy and complex calibration circuit, and the implementation cost of the delay error requirement of several 10fs stages is very high. The second scheme is that a pre-sampling holding buffer is used for sampling, holding and converting an input signal which changes at a high speed into a fixed level step signal, even if a certain amount of delay error exists between the sub-channel ADCs, the sampling error between the sub-channel ADCs cannot be caused finally, and therefore the requirement on the delay error is relaxed.

For the pre-sample-and-hold buffer architecture of a classical interleaved analog-to-digital converter (for example, for an interleaved ADC with four sub-channel ADCs), the system architecture is shown in fig. 1, and comprises two buffers, a full-rate pre-sample-and-hold circuit composed of a cascade of a sample switch SW and a sample-and-hold capacitor Cs in a dashed box. Wherein the input signal is connected with the input end of the buffer 1, and the buffer 1, the sample hold circuit and the buffer 2 are cascaded in sequence. The input terminals of the buffer 2 are respectively connected to the sub-channel ADC1, the sub-channel ADC2, the sub-channel ADC3 and the sub-channel ADC 4. The clock timing of the pre-sample-hold and sub-channel sample-hold is shown in fig. 2, the sampling frequency of the sample-hold circuit is Fs, the sampling frequency of the four sub-channel ADCs is Fs/4, and the phases of their sampling clocks are 0 °, 90 °, 180 ° and 270 °, respectively (the sampling rate Fs/4 of the sub-channel ADC is one cycle). The working principle is as shown in fig. 3, a full-rate sample-and-hold circuit with a sampling frequency of Fs is used to sample and hold a variable input signal, at the holding stage, the signal is a fixed level, and the four sub-channel ADCs complete their sampling at four successive holding stages of the sample-and-hold circuit in phases of 0 °, 90 °, 180 ° and 270 °, respectively, and the sampling rate and conversion rate of each sub-channel ADC are increased by 4 times in such a time-interleaved sampling manner. Because the sampling of each sub-channel ADC is completely carried out in the holding stage of the sampling holding circuit, when the sampling clock of the sub-channel ADC has a certain delay error, the final sampling error can not be caused. As shown in fig. 3, which is an exemplary diagram of the operation principle of the pre-sample-and-hold buffer, the sine wave signal in the upper half is the input signal, and the waveform in the lower half is the pre-sample-and-hold signal, which is a sample-and-hold signal based on the sampling structure of the lower plate of the sample-and-hold capacitor. The sampling stage is that the signal is turned to the upper polar plate after the sampling of the lower polar plate of the sampling holding capacitor is finished, and the signal is kept unchanged on the upper polar plate in the holding stage. For the interleaved ADC of this classical pre-sample and hold buffer architecture, no extra calibration circuit is generally needed to calibrate the sample clock delay error between the sub-channels, but it is very demanding for the pre-sample and hold circuit. Taking 5GSPS12bit adc as an example, the above architecture requires a pre-sample hold circuit and buffer with the same 5GSPS sampling rate and 12bit precision, which is not achievable for non-advanced processes (below 28 nm) except design optimization, which is a limit of process limit performance. The staggered ADC mainly based on the sub-channel delay error calibration without adding the pre-sampling holding buffer can realize higher sampling rate by increasing the number of channels, and does not excessively depend on the process.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a ping-pong pre-sampling holding buffer of an interleaved analog-to-digital converter, which has the advantage that the classic pre-sampling holding buffer does not need to additionally calibrate the sampling delay error of a sub-channel ADC (analog-to-digital converter), and simultaneously reduces the speed requirement of the pre-sampling holding buffer by one time by utilizing a ping-pong framework. Its advantages over conventional full-rate pre-sample-and-hold buffers are reduced requirements for pre-sample-and-hold buffers and the dependency of this type of architecture on advanced processes (below 28 nm). The realization is more concise and robust, and the realization cost is much lower.

The invention provides a ping-pong pre-sampling hold buffer of an interleaved ADC, which is used for the interleaved ADC with N sub-channel ADCs, wherein N is a positive integer of more than 2, and the buffer is characterized by comprising a pre-sampling hold buffer circuit with a ping-pong structure and a ping-pong clock generating circuit in a signal link;

the pre-sampling holding buffer circuit consists of a first-stage emitter-stage following isolator, a pre-sampling holding circuit and a second-stage source-stage following isolator; the first-stage emitter-stage following isolator consists of an NPN type triode and an initial current source; the pre-sampling holding circuit is a lower polar plate sampling circuit consisting of a first group of three sampling switches, a first sampling capacitor, a second group of three sampling switches and a second sampling capacitor which are mirrored; the second-stage source-level following isolator consists of a first NMOS tube, a first current source, a second NMOS tube and a second current source which are mirror images of the first NMOS tube and the first current source; the connection relationship is as follows: the base electrode of the NPN type triode is connected with the radio frequency signal input, the collector electrode of the NPN type triode is connected with the power supply, and the emitter electrode of the NPN type triode is connected to the ground through the initial current source; two transmission ends of a second switch in the first group of sampling switches are respectively connected with an emitting electrode of the NPN type triode and a lower polar plate of the first sampling capacitor, and a control end is connected with a first bootstrap clock of the first ping-pong clock; two transmission ends of a third switch in the first group of sampling switches are respectively grounded and a lower polar plate of the first sampling capacitor, and a control end is connected with an inverted clock of the first bootstrap clock; two transmission ends of a first switch in the first group of sampling switches are respectively connected with a power supply and an upper polar plate of a first sampling capacitor, and a control end is connected with a first ping-pong clock; the lower pole plate of the first sampling capacitor is connected with a second switch and a third switch in the first group of sampling switches, and the upper pole plate is connected with a first switch in the first group of sampling switches and is simultaneously connected with the grid electrode of the first NMOS tube; the grid electrode of the first NMOS tube is connected with the upper polar plate of the first sampling capacitor, the drain electrode of the first NMOS tube is connected with the power supply, the source electrode of the first NMOS tube is connected to the ground through the first current source, and meanwhile, the source electrode of the first NMOS tube is connected with the interleaved ADC sub-channels ADC-1, ADC-3 and … … ADC-N-1; two transmission ends of a second switch in the second group of sampling switches are respectively connected with an emitting electrode of the NPN type triode and a lower polar plate of a second sampling capacitor, and a control end is connected with a second bootstrap clock of a second ping-pong clock; two transmission ends of a third switch in the second group of sampling switches are respectively grounded and a lower polar plate of a second sampling capacitor, and a control end is connected with a second bootstrap clock and a clock with the opposite phase thereof; two transmission ends of a second switch in the second group of sampling switches are respectively connected with the power supply and an upper polar plate of a second sampling capacitor, and a control end is connected with a second ping-pong clock; the lower pole plate of the second sampling capacitor is connected with a second switch and a third switch in the second group of sampling switches, and the upper pole plate is connected with the second switch in the second group of sampling switches and simultaneously connected with the grid electrode of a second NMOS tube; the grid electrode of the second NMOS tube NMOS2 is connected with the upper polar plate of the second sampling capacitor Cs2, the drain electrode is connected with a power supply, and the source electrode passes through a current source;

the ping-pong clock generating circuit consists of a reset signal phase shift circuit and two frequency dividers which are mirror images of each other, wherein the reset signal phase shift circuit consists of two cascaded D-triggers, each frequency divider consists of a D-trigger with reset and an inverter, and the two frequency dividers are mirror images of each other; the connection relationship is as follows: an input signal D of the first D-trigger is connected with an initial reset signal, a trigger clock CK is connected with a main clock, and an output Q end outputs a first reset signal; an input signal D of the second D-trigger is connected with the first reset signal, a trigger clock CK is connected with the main clock, and an output Q end outputs a second reset signal; the output Q end of the first D-flip-flop with reset is connected with the input end of the first inverter, and the input D end is connected with the output end of the first inverter; the reset rst of the first two-frequency divider is connected with a first reset signal, and the trigger clock CK is connected with the output of the first delay unit; the output Q of the second D-flip-flop with reset is connected with the input of the second inverter, the input D is connected with the output of the second inverter, the reset rst of the second frequency divider is connected with the trigger clock CK of the second reset signal and is connected with the output of the first delay unit; the input of the first delay unit is connected with the main clock signal, and the output of the first delay unit is connected with the CK-end clock input of the first frequency divider and the CK-end clock input of the second frequency divider.

The invention has the characteristics and beneficial effects that:

(1) the structure provided by the invention is based on the mathematical symmetry of a ping-pong structure, the function of a full-rate pre-sampling holding buffer is realized by two physical layouts which are completely mirror-symmetrical, and ping-pong staggered half-rate pre-sampling holding buffers in time sequence, and compared with the conventional full-rate pre-sampling holding buffer, the structure has the advantages that the requirement on the pre-sampling holding buffer and the dependency of the type of architecture on an advanced process (below 28 nm) are reduced.

(2) For the realization of a ping-pong clock with extremely low phase error, the invention provides a double-initial-state frequency divider structure, the delay error of the double-initial-state frequency divider structure is only caused by the process mismatch between mirror image frequency dividers, the influence of the process deviation can be robustly eliminated by increasing the layout area (a plurality of standard unit frequency dividers are connected in parallel), and the specific expression is that the standard deviation of the delay error is reduced by one time when the standard unit of the frequency divider is increased by four times.

(3) For the implementation of the two-stage buffer, the invention provides a mixed structure combination of emitter follower (composed of NPN and a current source Ie) and source follower (composed of NMO1 and Ie1, and NMOS2 and Ie 2)

Drawings

Fig. 1 is a schematic diagram of a conventional pre-sample hold buffer architecture.

FIG. 2 is a diagram of an example of conventional pre-sample-and-hold and sub-channel sample-and-hold clock timing.

Fig. 3 is a schematic diagram of the operation of a conventional pre-sample-and-hold buffer.

Fig. 4 is a circuit schematic diagram of a ping-pong pre-sample hold buffer of the present invention.

FIG. 5 is an exemplary diagram of a ping-pong pre-sample-and-hold and sub-channel sample-and-hold clock timing of the present invention.

Fig. 6 is a schematic diagram of the operating principle of the ping-pong pre-sample hold buffer of the present invention.

Detailed Description

The ping-pong pre-sample hold buffer of interleaved ADC proposed by the present invention is described in detail below with reference to the accompanying drawings and embodiments:

the present invention provides a ping-pong pre-sample-and-hold buffer for interleaved ADC, the composition of which is shown in FIG. 4, for use with N

N is a positive integer more than 2, and the buffer comprises a pre-sampling holding buffer circuit with a ping-pong structure and a ping-pong clock generating circuit. The input signal of the pre-sampling holding buffer circuit is a radio frequency signal input and is output to each sub-channel ADC, the input clock of the clock generating circuit is CLK, and the output clocks are CLK1 and CLK 2. Two bootstrap clocks CLK1_ P, CLK2_ P and their inverted clocks CLK1_ Pb, CLK2_ Pb (CLK1_ P, CLK2_ P and CLK1_ Pb, CLK2_ Pb are generated by CLK1 and CLK2, respectively, through bootstrap peripheral circuits (which include bootstrap circuits and inverter circuits, not shown in the figure).

The circuit of the pre-sampling holding buffer of the ping-pong structure in the signal link is composed of a first stage emitter stage following isolator, a pre-sampling holding circuit and a second stage source stage following isolator as shown in the upper half dotted line frame of fig. 4; the first emitter follower isolator is composed of an NPN type triode BJT tube NPN and an initial current source Ie (the BJT tube has stronger driving capability and higher linearity compared with an MOS tube, and the NPN type triode BJT has higher speed than the PNP type triode). The pre-sampling hold circuit is composed of a first set of three sampling switches S1/SS1/SSS1 and a first sampling capacitor Cs1 and a mirrored second set of three sampling switches S2/SS2/SSS2 and a second sampling capacitor Cs2, wherein SS1 is used as a switch for supplying power to the upper plate of Cs1 at the time of sampling, its control signal is CLK1, S1 is used as a switch for supplying a signal at the time of sampling to the lower plate of Cs1, its control signal is a first bootstrap clock CLK1_ P generated after CLK1 passes through a bootstrap circuit (bootstrap is a common technique for improving the linearity of the switch by raising the high level following signal of the switch control terminal clock), SSS1 is used as a switch for supplying the signal at the time of sampling to the lower plate of Cs1, and its control signal is a first inverted clock CLK1_ Pb signal of the first bootstrap clock CLK1_ P. (for a bottom plate sampling structure, the specific sampling phase of the sample-and-hold signal is determined by the control clock phase of the top plate switch, i.e., by the two clocks CLK1 and CLK2, the two bootstrap clocks CLK1_ P/CLK2_ P and their inverted clocks CLK1_ Pb/CLK2_ Pb only affect the functional implementation). The second stage source follower isolator is composed of a first NMOS transistor NMOS1 and a first current source Ie1, and its mirror image second NMOS transistor NMOS2 and a second current source Ie2 (the source follower is widely used as an isolator in CMOS circuits, while the NMOS transistor source follower has stronger driving capability relative to PMOS transistors). The connection relationship is as follows: the base (b) of NPN type triode NPN is connected with radio frequency signal input, the collector (c) is connected with power supply, and the emitter (e) is connected to ground through initial current source Ie. Two transmission ends of a second switch SS1 in the first group of sampling switches are respectively connected with an emitter of an NPN type triode NPN and a lower plate of a first sampling capacitor Cs1, and a bootstrap clock CLK1_ P connected with a ping-pong clock CLK1 is controlled. Two transmission terminals of a third switch SSS1 in the first group of sampling switches are respectively connected to the ground and the lower plate of a first sampling capacitor Cs1, and the clock CLK1_ Pb which is connected with the reverse phase of the first bootstrap clock CLK1_ P is controlled. Two transmission ends of a first switch S1 in the first group of sampling switches are respectively connected with a power supply and the upper plate of a first sampling capacitor Cs1, and the control end is connected with a ping-pong clock CLK 1. The lower pole plate of the first sampling capacitor Cs1 is connected with a second switch SS1 and a third switch SSS1 in the first group of sampling switches, and the upper pole plate is connected with a first switch S1 in the first group of sampling switches and is also connected with the grid electrode of a first NMOS transistor NMOS 1. The grid electrode of the NMOS1 of the first NMOS tube is connected with the upper polar plate of the Cs1 of the first sampling capacitor, the drain electrode is connected with the power supply, the source electrode is connected to the ground through the first current source Ie1, and meanwhile, the source electrode is connected with the odd-channel ADCs such as the interleaved ADC sub-channels ADC-1, ADC-3 and … … ADC-N-1. Two transmission ends of a second switch SS2 in the second group of sampling switches are respectively connected with an emitter of an NPN type triode NPN and a lower plate of a second sampling capacitor Cs2, and a second bootstrap clock CLK2_ P connected with a second ping-pong clock CLK2 is controlled; two transmission terminals of a third switch SSS2 in the second group of sampling switches are respectively connected to the ground and the lower plate of a second sampling capacitor Cs2, and control terminals are connected with a second bootstrap clock CLK2_ P and an inverted clock CLK2_ Pb. Two transmission ends of a second switch S2 in the second group of sampling switches are respectively connected with the power supply and the upper plate of a second sampling capacitor Cs2, and the control end is connected with a second ping-pong clock CLK 2. The lower pole plate of the second sampling capacitor Cs2 is connected with a second switch SS2 and a third switch SSS2 in the second group of sampling switches, and the upper pole plate is connected with a second switch S2 in the second group of sampling switches and is also connected with the grid electrode of a second NMOS transistor NMOS 2. The grid electrode of the second NMOS tube NMOS2 is connected with the upper polar plate of the second sampling capacitor Cs2, the drain electrode is connected with a power supply, the source electrode is connected to the ground through a current source Ie2, and meanwhile, the source electrode is connected with even-numbered channel ADCs such as sub-channels ADC-2, ADC-4 and … … ADC-N in the staggered ADC.

The structure provided by the invention is based on the mathematical symmetry of a ping-pong structure, the function of a full-rate pre-sampling holding buffer is realized by two physical layouts which are completely mirror-symmetrical, and ping-pong staggered half-rate pre-sampling holding buffers in time sequence, and compared with the conventional full-rate pre-sampling holding buffer, the structure has the advantages that the requirement on the pre-sampling holding buffer and the dependency of the type of architecture on an advanced process (below 28 nm) are reduced. In principle, a new error is introduced due to the influence of process mismatch of mirror-symmetric layouts on the ping-pong pre-sampling hold buffer, the process mismatch which mainly influences the new error comprises mismatch of used sampling metal insertion finger capacitors (MoM capacitors) and mismatch of MOS (metal oxide semiconductor) tubes, the mismatch is inversely proportional to the size of a device, and the influence of the process mismatch on the sampling precision of the ADC (analog to digital converter) can be reduced to the required range by reasonably increasing the size of part of circuit layouts and symmetrical routing connection. Due to the limitation of sampling KT/C noise (the KT/C noise is the basic limiting condition of a sampling circuit, the generated noise source is the current thermal noise of the on-resistance of a sampling switch, and the noise source is inversely proportional to the sampling capacitance in design), the layout sizes of the sampling MoM capacitors Cs1 and Cs2 need to be large enough to eliminate the influence of the KT/C noise on the signal-to-noise ratio (SNR) of the ADC, while the size is large enough to eliminate the influence of process mismatch, the sampling switches S1/SS1/SSS1 and S2/SS2/SSS2 matched with the sampling capacitor, the bootstrap circuit (omitted in the figure), NMOS1 and NMOS2 which are NPN and source follower buffers of the emitter follower buffer respectively also need large layout size, the size of the layout dimension of the circuit is also large enough to eliminate the influence of process mismatch on the sampling precision, and the dimension does not need to be additionally increased generally. The part needing to increase the size of the layout compared with the conventional circuit is the first frequency divider circuit and the second frequency divider circuit, and the power consumption and the area of the first frequency divider circuit and the second frequency divider circuit only account for the expense of a very small part of the system, so that the layout size of the circuit cannot be increased at a large cost. Compared with the method for eliminating the delay error (the requirement of 10fs level) by complicated calibration, the method for realizing the delay error of the high-speed and low-speed integrated circuit has the advantages that the realization is simpler, the robustness is realized, and the realization cost is much lower.

For the implementation of the two-stage buffer, the invention provides a mixed structure combination of emitter follower (composed of NPN and a current source Ie) and source follower (composed of NMO1 and Ie1, and NMOS2 and Ie 2), which needs to be realized by relying on a Bi-CMOS (BJT and CMOS fused process, which is a process provided by current mainstream process manufacturers). An input stage following isolator is inserted between an input signal and a pre-sampling following circuit to meet the requirements of high driving capability and high linearity and ADC fixed input impedance, a source stage following isolator is inserted between an output signal and a pre-sampling holding circuit to meet the requirements of high driving capability and high linearity (due to the design of insertion loss effect and the overall linearity of a system, the linearity requirement of a post-stage circuit is generally lower than that of a pre-stage circuit), and meanwhile, because the grid stage of an NMOS (N-channel metal oxide semiconductor) tube hardly injects current, unlike the base stage of an NPN (negative-positive-negative) tube, the grid stage of the NMOS tube needs a certain injection current, the grid stage does not affect the holding of the signal. The two structures of emitter stage following and source stage following belong to the classic structure of isolators on textbooks.

The ping-pong clock generating circuit consists of a reset signal RST phase shifting circuit and two frequency dividers which are mirror images of each other. The reset signal RST is output by a reset signal RST phase shift circuit composed of two cascaded D-flip-flops that generates specific phase-shifted reset signals RST1 and RST2, while the phase shift between RST1 and RST2 is greater than one clock period T and less than two clock periods 2T. Each frequency divider consists of a D-trigger with reset and an inverter, and the two frequency dividers are mirror circuits. The two-frequency division clocks output by the mirror two-frequency division circuit are perfectly 180 DEG phase-shifted from each other by phase-shifting the reset signal between T and 2T. The connection relationship is as follows: the input signal D of the first D-flip-flop is connected with the reset signal RST, the trigger clock CK is connected with the main clock CLK, and the output Q end outputs the first reset signal RST 1. An input signal D of the second D-flip-flop is connected with the first reset signal RST1, a trigger clock CK is connected with the main clock CLK, and an output Q end outputs a second reset signal RST 2; the output Q of the first D-flip-flop with reset is connected with the input of the first inverter, and the input D is connected with the output of the first inverter (the two are combined into a first frequency divider); the reset RST of the first two-frequency divider is connected with a first reset signal RST1, and the trigger clock CK is connected with the output of the first delay unit. The output Q of the second D-flip-flop with reset is connected with the input of the second inverter, the input D is connected with the output of the second inverter (the two inverters are combined into a second frequency divider), the reset RST of the second frequency divider is connected with the second reset signal RST2, and the trigger clock CK is connected with the output of the first delay unit. The input of the first delay unit is connected with the main clock signal, and the output of the first delay unit is connected with the CK-end clock input of the first frequency divider and the CK-end clock input of the second frequency divider.

According to the double initial state frequency divider structure, the reset signal RST1 with the phase shift of T + D (T is a main clock period, and D is D flip-flop delay) and the reset signal RST2 with the phase shift of 2(T + D) are obtained by synchronizing the reset signal RST2 times by using the main clock CLK, the two reset signals RST1 and RST2 with the phase shift of (T + D) are used for respectively resetting a frequency divider driven by the same main clock CLK, and due to the fact that the phase shift of the reset signal is larger than T, two initial state frequency divider outputs CLK1 and CLK2 can be obtained in a definite mode, and the phase shift between the two initial state frequency divider outputs is a perfect main clock period T. The mathematical interpretation is: after a clock with period T generates a clock output with period 2T through a frequency divider, if the phase of the reset signal is arbitrary, the phase shift is N x T (N epsilon Z), which depends on the phase of the reset signal, and they can converge to two states of 0 and T. Delay asymmetry and delay error of the reset signal do not affect delay error between CLK1 and CLK2, delay error between CLK1 and CLK2 is only caused by process mismatch between mirror image frequency dividers, and the influence of process deviation can be robustly eliminated by increasing layout area (a plurality of standard cell frequency dividers are connected in parallel), specifically, delay error standard deviation is reduced by one time for each time of the frequency divider standard cell which is increased by four times.

For an N-channel interleaved ADC, if the number of channels N is 8, the ping-pong pre-sample hold clock timing and the sub-channel ADC sample hold clock timing diagram are shown in fig. 5. CLK1 and CLK2 are ping-pong two-divide sampling clocks with a perfect 180 ° phase shift between them, CLK _ ADC1, CLK _ ADC2, … …, and CLK _ ADC8 are eight-divide sub-channel ADC sampling clocks with a phase shift of 0 °, 45 °, 90 °, 135 °, 180 °, 225 °, 270 °, 315 ° with some error. During the holding phase of the pre-sample hold controlled by the clock CLK1, CLK _ ADC1, CLK _ ADC3, CLK _ ADC5 and CLK _ ADC7 complete sampling, and during the holding phase of the pre-sample hold controlled by the clock CLK2, CLK _ ADC2, CLK _ ADC4, CLK _ ADC6 and CLK _ ADC8 complete sampling.

Fig. 6 is a schematic diagram illustrating the working principle of the present invention. The pre-sampling holding circuit samples and holds the changed input signals and then outputs signals with fixed level, the sampling of the sub-channel ADC is completely carried out in the holding stage, and the influence of sampling clock phase errors of the sub-channel ADC can be eliminated. The ping-pong pre-sampling holding structure uses the mirror circuit, and the sampling stage-ping and holding stage-pong and the sampling stage-pong and holding stage-ping are carried out simultaneously, so that the maximum bandwidth of the pre-sampling holding circuit can be doubled.

Claims

1. A ping-pong pre-sample hold buffer for an interleaved ADC having N sub-channel ADCs, N being a positive integer of 2 or more, the buffer comprising a ping-pong pre-sample hold buffer circuit and a ping-pong clock generation circuit in a signal chain;