CN113097060A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113097060A
CN113097060A CN202010016189.9A CN202010016189A CN113097060A CN 113097060 A CN113097060 A CN 113097060A CN 202010016189 A CN202010016189 A CN 202010016189A CN 113097060 A CN113097060 A CN 113097060A
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Prior art keywords
layer
blocking
forming
etched
blocking layer
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张俊红
胡友存
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate; forming a layer to be etched on a substrate; forming a discrete core layer on the layer to be etched; forming a side wall film on the top and the side wall of the core layer and the surface of the layer to be etched; removing the side wall films positioned at the top of the core layer and on the surface of the layer to be etched, reserving the residual side wall films positioned on the side wall of the core layer as side walls, and enabling adjacent side walls positioned on the side walls of adjacent core layers and the layer to be etched to form a plurality of first grooves in a surrounding mode, wherein the first grooves extend in a first direction; forming a blocking layer in part of the first grooves, wherein the blocking layer fills the first grooves along a second direction, and the second direction is perpendicular to the first direction; after the blocking layer is formed, removing the core layer to form a second groove, wherein the second groove is separated from the first groove by a side wall; and etching the layers to be etched at the bottoms of the first groove and the second groove by using the side walls and the blocking layer as masks to form a target pattern. The embodiment of the invention is beneficial to improving the precision of pattern transfer.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the rapid growth of the semiconductor Integrated Circuit (IC) industry, semiconductor technology is driven by moore's law to move towards smaller process nodes, so that the Integrated circuit is developed towards smaller size, higher circuit precision and higher circuit complexity.
In the development of integrated circuits, as the functional density (i.e., the number of interconnect structures per chip) generally increases, the geometric size (i.e., the minimum component size that can be produced by the process steps) also decreases, which increases the difficulty and complexity of integrated circuit fabrication.
At present, with the shrinking of technology nodes, it is a challenge how to improve the matching between the pattern formed on the wafer and the target pattern.
Disclosure of Invention
The embodiment of the invention provides a semiconductor structure and a forming method thereof, which can improve the precision of pattern transfer.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a layer to be etched on the substrate; forming a discrete core layer on the layer to be etched; forming a side wall film on the top and the side wall of the core layer and the surface of the layer to be etched; removing the side wall films positioned at the top of the core layer and on the surface of the layer to be etched, and reserving the residual side wall films positioned on the side wall of the core layer as side walls, wherein a plurality of first grooves are formed by the adjacent side walls positioned on the adjacent side walls of the core layer and the layer to be etched in a surrounding manner, and the first grooves extend along a first direction; forming a blocking layer in a portion of the first groove, the blocking layer filling the first groove along a second direction, the second direction being perpendicular to the first direction; after the blocking layer is formed, removing the core layer to form a second groove, wherein the second groove and the first groove are isolated by the side wall; and etching the layers to be etched at the bottoms of the first groove and the second groove by taking the side walls and the blocking layer as masks to form a target pattern.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; a layer to be etched on the substrate; the core layer is separated on the layer to be etched; the side walls are positioned on the side walls of the layers to be etched, a plurality of first grooves are formed by the side walls adjacent to the side walls of the core layers and the layers to be etched in a surrounding mode, and the first grooves extend along a first direction; and the blocking layer is positioned in part of the first groove, the blocking layer fills the first groove along a second direction, the second direction is vertical to the first direction, and the blocking layer and the side wall are used as masks for etching the layer to be etched.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming a semiconductor structure according to the embodiment of the present invention, after the side wall film is formed and before the blocking layer is formed, the side wall film on the top of the core layer and the surface of the to-be-etched layer is removed to form the side wall, so that, in the step of forming the blocking layer, the side wall film is not formed on the top of the core layer, which is beneficial to preventing the problem that the blocking layer still covers the side wall film on the top of the core layer, and if the blocking layer still covers part of the core layer, the step of removing the side wall film on the top of the core layer is not required, the core layer can be exposed by performing over-etching on the blocking layer, which is beneficial to increasing a process window for performing over-etching (over-etching) on the blocking layer, so that the core layer can be easily removed completely when the core layer is removed, and the problem that the side wall is lost for removing the side wall film on the top of the core layer, the process difficulty is correspondingly reduced, the process window is enlarged, the blocking layer and the side wall are favorable for ensuring the function of the blocking layer and the side wall as a mask for etching the layer to be etched, the pattern transfer precision is further improved, and the formed target pattern meets the process requirement.
Drawings
Fig. 1 to 6 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
FIG. 7 is a partial top view of a semiconductor structure formed using the method of forming the semiconductor structure of FIGS. 1-6;
FIG. 8 is a corresponding schematic diagram of another method of forming a semiconductor structure;
FIG. 9 is a schematic diagram illustrating a structure corresponding to another method for forming a semiconductor structure;
fig. 10 to 20 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The pattern transfer precision of the existing forming method of the semiconductor structure is low, and the formed actual pattern is difficult to meet the design requirement. The reason why the precision of pattern transfer is low is analyzed in combination with a method for forming a semiconductor structure.
Referring to fig. 1 to 6, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, a substrate 1 is provided; a layer 2 of metallic hard mask material is formed on the substrate 1.
With continued reference to fig. 1, a discrete core layer 3 is formed on the metallic hard mask material layer 2.
Referring to fig. 2, a side wall film 4 is formed on the top and the side wall of the core layer 3 and the surface of the metal hard mask material layer 2, and the side wall film 4 adjacent to the side wall of the core layer 3 and the side wall film 4 on the surface of the metal hard mask material layer 2 form a trench 5, where the trench 5 extends along a first direction (not shown).
Referring to fig. 3, a blocking layer 6 is formed in a portion of the trench 5, the blocking layer 6 fills the trench 5 along a second direction (not labeled), the second direction is perpendicular to the first direction, and the blocking layer 6 also covers a portion of the sidewall film 4 on top of the core layer 3 on both sides of the trench 5.
Referring to fig. 4, the side wall film 4 on the top of the core layer 3 and the surface of the metal hard mask material layer 2 exposed by the blocking layer 6 is removed, the remaining side wall film 4 on the side wall of the core layer 3 is used as a side wall 7, and a first groove 8 is enclosed by the adjacent side wall 7 on the side wall of the adjacent core layer 3 and the metal hard mask material layer 2.
Referring to fig. 5, after removing the top of the core layer 3 and the side wall film 4 on the surface of the metal hard mask material layer 2 exposed by the blocking layer 6, the core layer 3 is removed to form a second groove 9, and the first groove 8 and the second groove 9 are isolated by the side wall 7.
Referring to fig. 6, the metal hard mask material layer 2 at the bottom of the first groove 8 and the second groove 9 is etched by using the side walls 7 and the blocking layer 6 as masks, wherein the metal hard mask material layer 2 is etched by using the side walls 7 as masks to form a metal hard mask layer 10, and the metal hard mask material layer 2 is etched by using the blocking layer 6 as masks to form a blocking mask layer 11.
In the above method, after the side wall film 4 is formed, the blocking layer 6 is formed in a part of the trench 5, and the blocking layer 6 also covers a part of the side wall film 4 on the top of the core layer 3 on both sides of the trench 4, so that, in the step of removing the exposed top of the core layer 3 and the side wall film 4 on the surface of the metal hard mask material layer 2 by the blocking layer 6, a part of the side wall film 4 on the top of the core layer 3 is remained under the covering of the blocking layer 6, which easily causes the following problems:
firstly, the residual side wall film 4 covers part of the top of the core layer 3, which easily increases the difficulty of removing the core layer 3, and the core layer 3 is difficult to be removed completely;
secondly, when the sidewall 7 and the blocking layer 6 are used as masks in the subsequent etching of the metal hard mask material layer 2 at the bottoms of the first groove 8 and the second groove 9, the accuracy of pattern transfer is easily affected, so that the width of the blocking mask layer 11 is too large, when the metal hard mask layer 10 and the blocking mask layer 11 are used as masks in the subsequent etching of the substrate 1, a dielectric interlayer a (shown in fig. 7) corresponding to the metal hard mask layer 10 is formed in the substrate 1, a blocking structure B (shown in fig. 7) corresponding to the blocking mask layer 11 is formed in the substrate 1, an interconnection trench for forming a metal interconnection line M (shown in fig. 7) is defined between the adjacent dielectric interlayers a or blocking structures B, the blocking structure B occupies too much space for forming the metal interconnection line M, so that the filling difficulty of the metal interconnection line M in the interconnection trench is large, and causes a deterioration in the pattern quality of the metal interconnection lines M (as indicated by the dashed line box in fig. 7), and even easily causes the interruption structure B to interrupt the metal interconnection lines M at a position where the interruption is not required (as indicated by the position indicated by the arrow in fig. 7).
In order to prevent the above problem, in the current method, in the step of removing the side wall film on the top of the core layer and on the surface of the metal hard mask material layer exposed by the blocking layer, an over-etching process is performed to remove the side wall film on the top of the core layer.
However, the difficulty of precisely controlling over-etching is large. If over-etching is more, as shown in fig. 8, since the material of the sidewall film on the top of the core layer 3b is the same as that of the sidewall 7b, the sidewall 7b is easily etched, and further the height loss of the sidewall 7b is caused (as shown by a dashed line frame in fig. 8), so that it is difficult to ensure the function of the sidewall 7b as an etching mask, and the precision of pattern transfer is easily reduced.
Moreover, if the over-etching is too much, as shown in fig. 9, the remaining thickness of the blocking layer 6a in the trench 8a may be too small (as shown by the dashed line in fig. 9), which makes it difficult for the blocking layer 6a to perform the blocking function, for example: if the top of the remaining blocking layer 6a is lower than the top of the sidewall 7a, after the patterned metal hard mask material layer and the substrate 1a are etched by using the patterned metal hard mask material layer 2a as a mask, the top surface of the blocking structure formed in the substrate and corresponding to the blocking layer 6a is lower than the top surface of the dielectric layer, and a groove is formed by the top surface of the blocking structure and the dielectric layer, which easily causes that the pattern formed in the substrate 1a is difficult to meet the process requirements, as an example: when the patterned substrate 1a is used to form metal interconnection lines, adjacent metal interconnection lines are easily filled into the grooves, thereby causing the adjacent metal interconnection lines to be short-circuited (large) with each other, and further causing circuit failure.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a layer to be etched on the substrate; forming a discrete core layer on the layer to be etched; forming a side wall film on the top and the side wall of the core layer and the surface of the layer to be etched; removing the side wall films positioned at the top of the core layer and on the surface of the layer to be etched, and reserving the residual side wall films positioned on the side wall of the core layer as side walls, wherein a plurality of first grooves are formed by the adjacent side walls positioned on the adjacent side walls of the core layer and the layer to be etched in a surrounding manner, and the first grooves extend along a first direction; forming a blocking layer in a portion of the first groove, the blocking layer filling the first groove along a second direction, the second direction being perpendicular to the first direction; after the blocking layer is formed, removing the core layer to form a second groove, wherein the second groove and the first groove are isolated by the side wall; and etching the layers to be etched at the bottoms of the first groove and the second groove by taking the side walls and the blocking layer as masks to form a target pattern.
In the method for forming a semiconductor structure according to the embodiment of the present invention, after the formation of the sidewall film and before the formation of the blocking layer, the sidewall film on the top of the core layer and the surface of the sidewall film to be etched are removed to form the sidewall, so that, in the step of forming the blocking layer, the sidewall film is not formed on the top of the core layer, which is beneficial to preventing the blocking layer from covering the sidewall film on the top of the core layer, and if the blocking layer covers part of the core layer, the step of removing the sidewall film on the top of the core layer is not required, the core layer can be exposed by performing over-etching on the blocking layer, so that when the core layer is removed, the core layer is easily removed completely, which is beneficial to preventing the loss problem of the sidewall film on the top of the core layer from being removed, and accordingly, the process difficulty is reduced, The process window is enlarged, and the blocking layer and the side wall are favorable for ensuring the function of the blocking layer and the side wall as masks for etching the layer to be etched, so that the precision of pattern transfer is improved, and the formed target pattern meets the process requirements.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 10 to 20 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 10, a substrate is provided.
The substrate is used for providing a process platform for subsequent process procedures.
In this embodiment, semiconductor devices such as transistors and capacitors may be formed in the substrate, and functional structures such as a resistor structure and a conductive structure may be formed in the substrate.
In this embodiment, the substrate includes an inter-metal dielectric (IMD) layer 110, and the IMD layer 110 is used to implement electrical isolation between interconnection lines in a Back end of line (BEOL) process.
The inter-metal dielectric layer 110 is used as a film layer to be patterned, and after the inter-metal dielectric layer 110 is subsequently patterned, an interconnection groove is formed and used for providing a space position for forming an interconnection line.
Therefore, the inter-metal dielectric layer 110 is made of a low-k dielectric material (low-k dielectric material refers to a dielectric material having a relative dielectric constant of 2.6 or more and 3.9 or less), an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material having a relative dielectric constant of less than 2.6), silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the inter-metal dielectric layer 110 is made of an ultra-low-k dielectric material, so that parasitic capacitance between the interconnection lines at the rear section is reduced, and further, the RC delay at the rear section is reduced. In particular, the ultra-low k dielectric material may be SiOCH.
With continued reference to fig. 10, a layer to be etched 120 is formed over the substrate.
The layer to be etched 120 is used as a film layer to be patterned to form a target pattern.
In this embodiment, the layer to be etched 120 is a metal hard mask material layer, and the layer to be etched 120 is located on the inter-metal dielectric layer 110.
After the layer to be etched 120 is patterned subsequently, a metal hard mask layer is formed on the metal hard mask material layer, and the metal hard mask layer is used as an etching mask for etching the inter-metal dielectric layer 110 to form the interconnection trench.
In this embodiment, the layer to be etched 120 is made of silicon nitride. In other embodiments, the material of the layer to be etched may also be silicon oxide, silicon oxynitride, silicon carbide, titanium oxide, titanium nitride, tantalum oxide, tantalum nitride, boron nitride, copper nitride, aluminum nitride, or tungsten nitride.
With continued reference to fig. 10, a discrete core layer 130 is formed over the layer to be etched 120.
The core layer 130 is used for providing a supporting function for the subsequent formation of the side wall film.
Moreover, the region between adjacent core layers 130 is also used to define the formation region of a subsequent first groove, and the position occupied by the core layer 130 is used to define the formation region of a subsequent second groove.
The core layer 130 is subsequently removed, so that the core layer 130 is a material that is easy to remove, and the process of removing the core layer 130 has less damage to other film layers.
In this embodiment, the material of the core layer 130 is amorphous silicon. In other embodiments, the material of the core layer may also be amorphous germanium, silicon oxide, silicon oxynitride, carbon nitride, polysilicon, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or other suitable materials.
Referring to fig. 11, a sidewall film 135 is formed on the top and sidewalls of the core layer 130 and the surface of the layer to be etched 120.
The sidewall film 135 is used to form a sidewall. The sidewall is used as a partial etching mask for subsequent patterning of the layer to be etched 120.
In this embodiment, the sidewall film 135 is made of titanium nitride. The titanium nitride material has a larger etching selectivity with amorphous silicon, silicon nitride and SiOCH, which is beneficial to ensuring the function of the subsequent side wall as an etching mask for etching the layer to be etched 120, and is also beneficial to reducing the loss of the side wall film 135 when the core layer 130 is subsequently removed. In other embodiments, the material of the sidewall film may be titanium oxide or silicon oxide, or other suitable materials according to the actual process.
In this embodiment, the sidewall film 135 is formed by an Atomic deposition (ALD) process. The atomic layer deposition process is a Self-limiting (Self-limiting) reaction process based on the atomic layer deposition process, the thickness of a deposited film can reach the thickness of a single layer of atoms, and because the atomic layer deposition process can accurately deposit one atomic layer in each period, the atomic layer deposition process is selected to be beneficial to accurately controlling the thickness of the side wall film 135, the step coverage performance of the atomic layer deposition process is good, the conformal coverage capability of the side wall film 135 on the top and the side wall of the core layer 130 and the surface of the layer to be etched 120 is improved, and in addition, the film prepared by the atomic layer deposition process has the characteristics of good bonding strength, consistent film thickness, good component uniformity, good conformality and the like, and the thickness uniformity and the film quality of the side wall film 135 are improved.
In other embodiments, other suitable deposition processes may be used to form the sidewall film, depending on the actual process.
Referring to fig. 12, fig. 12a in fig. 12 is a top view, fig. 12b is a cross-sectional view taken along a-a1 direction in fig. 12a, the sidewall films 135 on the top of the core layer 130 and the surface of the layer to be etched 120 are removed, the remaining sidewall films 135 on the sidewalls of the core layer 130 are remained as the sidewall 140, the adjacent sidewall 140 on the sidewalls of the adjacent core layer 130 and the layer to be etched 120 enclose a plurality of first grooves 20, and the first grooves 20 extend along a first direction (as shown in X direction in fig. 12 a).
The sidewalls 140 are used as a partial mask for etching the layer to be etched 120.
In this embodiment, the first grooves 20 extend along a first direction (shown as an X direction in fig. 12 a), and the plurality of first grooves 20 are arranged along a second direction (shown as a Y direction in fig. 12 a), which is perpendicular to the first direction.
The subsequent steps further comprise: a blocking layer is formed in a portion of the first recess 20.
In the method for forming a semiconductor structure according to the embodiment of the present invention, after the formation of the side wall film 135 and before the formation of the blocking layer, the side wall film 135 on the top of the core layer 130 and the surface of the layer to be etched 120 are further removed to form the side wall 140, so that in the subsequent step of forming the blocking layer, the top of the core layer 130 is not formed with the side wall film 135, which is beneficial to preventing the blocking layer from covering the side wall film 135 on the top of the core layer 130, and if the blocking layer still covers part of the core layer 130, the step of removing the side wall film 135 on the top of the core layer 130 is not required, the core layer 130 can be exposed by performing over-etching on the blocking layer, so that when the core layer 130 is removed, the core layer 130 is easily removed, and the problem of loss of the side wall 140 for removing the side wall film 135 on the top of the core layer 130 is also beneficial to preventing, accordingly, the process difficulty is reduced, the process window is enlarged, and the blocking layer and the sidewall 140 can be used as a mask for etching the layer to be etched 120, so that the pattern transfer precision is improved, and the formed target pattern meets the process requirements.
Specifically, by removing the sidewall film 135 on the top of the core layer 130 and the surface of the layer to be etched 120, a process window for performing over-etching (over-etching) on the blocking layer is advantageously increased.
In this embodiment, an anisotropic dry etching process is used to remove the sidewall film 135 on the top of the core layer 130 and the surface of the layer to be etched 120. The anisotropic dry etching process has the anisotropic etching characteristic, so that in the process of removing the side wall film 135 on the surfaces of the core layer 130 and the layer to be etched 120, the lateral etching on the side wall film 135 on the side wall of the core layer 130 is less, and the side wall film 135 on the side wall of the core layer 130 can be reserved as the side wall 140; moreover, the dry etching process is beneficial to improving the etching selectivity, so that the damage to other film layers (such as the core layer 130) caused by the process of removing the side wall film 135 on the top of the core layer 130 and the surface of the layer to be etched 120 is reduced.
In particular, the anisotropic dry etching process may be an anisotropic plasma etching process.
In this embodiment, the etching selection ratio of the plasma etching process to the sidewall film 135 and the core layer 130 is greater than or equal to 5: 1, thereby ensuring that the loss of the core layer 130 is small, and when the side wall film 135 on the top surface of the core layer 130 is removed, the top of the core layer 130 can be stopped.
Referring to fig. 13, fig. 13a of fig. 13 is a plan view, and fig. 13b is a sectional view taken along a-a1 direction of fig. 13a, a blocking layer 145 is formed in a portion of the first groove 20, and the blocking layer 145 fills the first groove 20 along a second direction (shown as Y direction in fig. 13 a) perpendicular to the first direction.
The blocking layer 145 and the sidewall spacers 140 together serve as a mask for subsequent patterning of the layer to be etched 120. The blocking layer 145 fills the first groove 20 in the second direction, thereby breaking the first groove 20 in the first direction.
The material of the blocking layer 145 is a dielectric material. In this embodiment, the material of the blocking layer 145 includes silicon oxide. The silicon oxide, the silicon nitride and the amorphous silicon have higher etching selectivity, which is beneficial to reducing the influence of the subsequent process for removing the core layer 130 on the blocking layer 145, and ensuring the etching mask effect of the blocking layer 145 in the subsequent etching of the layer to be etched 120, and correspondingly improving the stability of pattern transmission and the pattern transfer precision.
In other embodiments, the material of the blocking layer may also be other materials with higher etching selectivity with the layer to be etched and the core layer, such as silicon nitride, according to the materials of the layer to be etched and the core layer.
In this embodiment, in the step of forming the blocking layer 145, the blocking layer 145 also covers part of the top of the core layer 130 on both sides of the first groove 20.
In this embodiment, the step of forming the blocking layer 145 includes: forming a mask layer (not shown) filling the first groove 20 on the core layer 130 and the sidewall spacers 140, wherein a mask opening (not shown) is formed in the mask layer, and the mask opening exposes a part of the bottom and sidewalls of the first groove 20; filling a blocking material layer (not shown) in the first groove 20 exposed by the mask opening and the mask opening; etching back a part of the thickness of the blocking material layer, wherein the remaining blocking material layer is used as the blocking layer 145; and removing the mask layer.
The mask layer is used for defining the pattern and the forming position of the blocking material layer, and the mask opening is used for providing a space position for forming the blocking material layer.
The mask layer is made of organic materials such as photoresist and spin-on carbon. The mask layer may be formed by a photolithography process such as coating, exposure, and development, which is not described herein again.
The blocking material layer is used to form a blocking layer.
In this embodiment, the process of forming the blocking material layer includes a chemical vapor deposition process. In other embodiments, other suitable deposition processes may be used to form the blocking material layer.
In this embodiment, the process of etching back the blocking material layer with a partial thickness includes a dry etching process.
Specifically, the dry etching process may be a plasma etching process. The plasma etching process has high etching accuracy and efficiency, and is favorable for realizing high etching selection ratio, thereby being favorable for reducing the probability of generating loss on the side wall 140 and the core layer 130 in the process of back etching the blocking material layer.
And removing the mask layer after the blocking material layer is etched back. Specifically, the mask layer may be removed by an ashing process, a wet stripping process, or the like.
The subsequent steps further comprise: the core layer 130 is removed.
With reference to fig. 14 to fig. 16, in this embodiment, the method for forming the semiconductor structure further includes: after forming the blocking layer 145, the blocking layer 145 on top of the core layer 130 is removed before removing the core layer 130.
By removing the blocking layer 145 on top of the core layer 130, thereby exposing the top of the core layer 130, provision is made for subsequent removal of the core layer 130 and preventing the blocking layer 145 on top of the core layer 130 from affecting the accuracy of the pattern transfer.
In this embodiment, the step of removing the blocking layer 145 on top of the core layer 130 includes:
as shown in fig. 14 and 15, a blocking layer 160 is formed to fill the first recess 20 and cover the blocking layer 145, and the blocking layer 160 exposes the blocking layer 145 on top of the core layer 130.
The blocking layer 160 is used as an etch mask for etching the blocking layer 145.
In this embodiment, the shielding layer 160 is also used as an etching mask for removing the core layer 130 subsequently.
The subsequent steps further comprise: the shielding layer 160 is removed. Therefore, the shielding layer 160 is a material that is easily removed.
In this embodiment, the material of the shielding layer 160 is an organic material. Specifically, the material of the shielding layer 160 may be an ODL (organic dielectric layer) material. The filling performance of the ODL is better, thereby improving the filling capability of the shielding layer 160 in the first groove 20. In other embodiments, the material of the shielding layer may also be SOC (Spin-on carbon) material or DUO (deep UV light absorbing oxide) material with better filling performance.
In this embodiment, the step of forming the shielding layer 160 includes: as shown in fig. 14, an initial masking layer 150 is formed filling the first recess 20 (shown in fig. 13), the initial masking layer 150 also covering the blocking layer 145; forming an anti-reflective coating 151 on the initial shielding layer 150 and a pattern layer 152 on the anti-reflective coating 151; as shown in fig. 15, the anti-reflective coating 151 and the initial shielding layer 150 are sequentially etched using the pattern layer 152 as a mask, and the remaining initial shielding layer 150 is used as the shielding layer 160.
In this embodiment, the anti-reflective coating 151 is used to reduce the reflection effect during exposure, thereby improving the pattern transfer accuracy. In this embodiment, the anti-reflective coating 151 is a Si-ARC layer, which is beneficial to increase the depth of field (DOF) of exposure during the photolithography process and improve the exposure uniformity, and the Si-ARC layer is rich in silicon, so that the hardness of the anti-reflective coating 151 is further improved, thereby further improving the pattern transfer accuracy.
In other embodiments, the anti-reflective coating may also be other suitable anti-reflective materials, such as: BARC (Bottom Anti-reflective coating) material.
In this embodiment, the pattern layer 152 is used as an etching mask for etching the anti-reflective coating 151 and the initial shielding layer 150. In this embodiment, the pattern layer 152 is made of a photoresist, and the pattern layer 152 may be formed through a photolithography process such as coating, exposing, and developing.
In this embodiment, a dry etching process is adopted, and the anti-reflective coating 151 and the initial shielding layer 150 are sequentially etched using the pattern layer 152 as a mask. The dry etching process has better profile controllability and is beneficial to improving the precision of pattern transfer. In particular, the dry etching process may be a plasma etching process.
In this embodiment, the pattern layer 152 is gradually consumed during the etching of the anti-reflective coating 151 and the initial shielding layer 150, so that the pattern layer 152 is removed after the shielding layer 160 is formed.
As shown in fig. 16, the blocking layer 145 exposed by the blocking layer 160 is removed.
In this embodiment, a dry etching process is used to remove the blocking layer 160 and expose the blocking layer 145. Specifically, the process of removing the blocking layer 145 exposed by the blocking layer 160 includes a plasma etching process.
In the step of removing the blocking layer 145 exposed by the blocking layer 160, an etching selection ratio of the blocking layer 145 to the sidewall 140 is greater than or equal to 5: 1. the etching selection ratio of the barrier layer 145 and the sidewall 140 is relatively large, so that the probability of damage to the sidewall 140 is small in the process of removing the blocking layer 145 exposed by the blocking layer 160, and the etching mask effect of the sidewall 140 in the subsequent patterning of the layer to be etched 120 is favorably ensured.
In this embodiment, during the process of removing the blocking layer 145 exposed by the blocking layer 160, the anti-reflective coating 151 on the blocking layer 160 is gradually consumed, so that after the blocking layer 145 exposed by the blocking layer 160 is removed, the anti-reflective coating 151 is removed.
After removing the blocking layer 145 exposed by the blocking layer 160, the method for forming the semiconductor structure further includes: the shielding layer 160 is removed.
In this embodiment, the process of removing the blocking layer 160 includes an ashing process.
Referring to fig. 17, fig. 17a in fig. 17 is a top view, and fig. 17b is a cross-sectional view taken along a-a1 in fig. 17a, after forming the blocking layer 145, the core layer 130 is removed to form a second recess 40, and the second recess 40 and the first recess 20 are isolated by the sidewall 140.
By removing the core layer 130, the layer to be etched 120 at the bottom of the core layer 130 is exposed, so as to prepare for subsequently etching the layer to be etched 120 at the bottom of the first groove 20 and the second groove 40.
The extending direction of the second groove 40 is also the first direction, and the plurality of second grooves 40 are arranged along the second direction.
In this embodiment, after forming the sidewall spacers 140 on the sidewalls of the core layer 130 and forming the first recess 20, removing the core layer 130 to form a second recess 40, wherein the second recess 40 and the first recess 20 are isolated by the sidewall 140, by forming the first groove 20 and the second groove 40 in different steps, the difficulty of forming the first groove 20 and the second groove 40 is reduced, the process window is increased (for example, the optical proximity effect is improved), the pattern precision of the first groove 20 and the second groove 40 is guaranteed, and first recess 20 and second recess 40 are separated by sidewall 140, it is also advantageous to control the thickness of sidewall 140, so that the minimum design interval between the first groove 20 and the second groove 40 is satisfied, and accordingly, after the layer to be etched 120 at the bottom of the first groove 20 and the second groove 40 is subsequently etched to form a target pattern, the minimum design interval is favorably met among the target patterns, and the pattern precision of the target patterns is improved.
In this embodiment, since the sidewall film 135 is not formed on the top of the core layer 130 and the blocking layer 145 is not formed on the top of the core layer 130, that is, in the process of removing the core layer 130, no blocking object is formed on the core layer 130, which is beneficial to increasing the process window for removing the core layer 130, so that the core layer 130 is easily removed.
In this embodiment, the process of removing the core layer 130 includes a plasma etching process. By selecting the plasma etching process, the realization of a larger etching selection ratio is facilitated, so that the damage to other film layers when the core layer 130 is removed is reduced, for example: the damage to the sidewall spacers 140 is small to ensure the etching mask effect of the sidewall spacers 140 in the subsequent patterning of the layer to be etched 120.
Specifically, in this embodiment, in the step of removing the core layer 130, the etching selection ratio of the core layer 130 to the blocking layer 145 is greater than or equal to 5: 1.
in this embodiment, after removing the blocking layer 145 exposed by the blocking layer 160 and before removing the blocking layer 160, the core layer 130 is removed.
By removing the core layer 130 before removing the shielding layer 160, the shielding layer 160 can continue to be used as a mask for removing the core layer 130, which is beneficial to improving the process integration degree and the process compatibility.
Accordingly, in this embodiment, the step of removing the core layer 130 includes: the core layer 130 is removed using the blocking layer 145 and the blocking layer 160 as masks.
Referring to fig. 18, the layer to be etched 120 at the bottom of the first groove 20 and the second groove 40 is etched using the sidewall 140 and the blocking layer 145 as masks, so as to form a target pattern.
In this embodiment, the sidewall 140 has a low loss probability in the foregoing steps, and no part of the sidewall film 135 remains, so that the pattern transfer precision is higher in the step of etching the layer to be etched 120 at the bottom of the first groove 20 and the second groove 40.
In this embodiment, the layer to be etched 120 is a metal hard mask material layer, so that the layer to be etched 120 at the bottom of the first groove 20 and the second groove 20 is etched by using the sidewall 140 and the blocking layer 145 as masks to form the metal hard mask layer 170.
The metal hard mask layer 170 is used as an etching mask for etching the metal interlayer dielectric layer 110.
In this embodiment, after the layer to be etched 120 at the bottom of the first groove 20 and the second groove 40 is etched, the metal hard mask layer 170 at the bottom of the blocking layer 145 and the sidewall 140 adjacent to the blocking layer 145 is used as a metal blocking layer 170a, and the metal blocking layer 170a does not occupy the space between the adjacent metal hard mask layers 170 in the second direction (as shown in the Y direction in fig. 17 a).
And then, the inter-metal dielectric layer 110 is etched by taking the metal blocking layer 170a as a mask to form a blocking structure.
Referring to fig. 19 in combination, fig. 19a in fig. 19 is a top view, and fig. 19b is a cross-sectional view taken along the direction aa1 in fig. 19a, in this embodiment, after forming the metal hard mask layer 170, the method for forming a semiconductor structure further includes: and etching the metal interlayer dielectric layer 110 by taking the metal hard mask layer 170 as a mask, and forming a plurality of interconnection grooves 60 in the metal interlayer dielectric layer 110.
The interconnect trench 60 is used to provide a spatial location for forming interconnect lines.
In this embodiment, the interconnection trenches 60 extend along a first direction, the plurality of interconnection trenches 60 are arranged along a second direction, and the plurality of interconnection trenches 60 are isolated by the remaining inter-metal dielectric layer 110.
In this embodiment, the metal blocking layer 170a is used as a mask to etch the metal interlayer dielectric layer 110, the metal interlayer dielectric layer 110 located at the bottom of the metal blocking layer 170a is used as a blocking structure 110a, and the blocking structure 110a blocks the same interconnection trench 60 along the first direction, so that the interconnection line formed in the interconnection trench 60 where the blocking structure 110a is located subsequently can be disconnected at the position of the blocking structure 110 a.
In the present embodiment, the blocking structure 110a does not occupy the space of the interconnection trench 60 in the second direction, thereby preventing an influence on the pattern of the interconnection trench 60 and the filling of the interconnection line in the interconnection trench 60.
Referring to fig. 20 in combination, fig. 20a in fig. 20 is a top view, and fig. 20b is a cross-sectional view taken along a-a1 of fig. 20a, wherein an interconnect line 180 is filled in the interconnect trench 60 (shown in fig. 19).
In this embodiment, the interconnection line 180 is a metal layer. In this embodiment, the interconnect 180 is made of copper. In other embodiments, the material of the interconnection line may also be a conductive material such as cobalt, tungsten, aluminum, or the like.
In this embodiment, the interconnection lines 180 are isolated from each other by the remaining intermetal dielectric layer 110.
Wherein the interconnect line 180 located in the interconnect trench 60 where the blocking structure 110a is located is disconnected by the blocking structure 110a at the position of the blocking structure 110 a.
In this embodiment, the pattern quality of the blocking structure 110a is better, so that the pattern quality of the interconnection line 180 is higher, the line edge roughness is lower, and the pattern quality of the interconnection line 180 broken at the position of the blocking structure 110a is higher, which is beneficial to improving the filling capability of the interconnection line 180 in the interconnection trench 60 and preventing the problem that the interconnection line 180 is broken at a position where the disconnection is not needed, and the embodiment of the present invention is beneficial to ensuring that the metal blocking layer 170a is used as an etching mask, thereby preventing the problem that the top of the blocking structure 110a is lower, and accordingly, preventing the problem that the interconnection line 180 is short-circuited (merge) at the position of the blocking structure 110 a.
In summary, the embodiment of the invention is beneficial to improving the electrical connection reliability of the semiconductor structure, so that the formed interconnection pattern meets the design requirement. In particular, the embodiment of the invention is beneficial to enabling the pattern of the interconnection line to meet the requirement of circuit design.
In this embodiment, the step of forming the interconnect line 180 includes: forming a conductive layer (not shown) filling the interconnection trench 60 on the inter-metal dielectric layer 110; and removing the conductive layer higher than the inter-metal dielectric layer 110, and filling the residual conductive layer in the interconnection groove 60 to be used as the interconnection line.
Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 16, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate; a layer to be etched 120 on the substrate; a core layer 130 separated from the layer to be etched 120; side walls 140 located on the side walls of the layers to be etched 120, wherein a plurality of first grooves 20 (shown in fig. 12) are defined by the side walls 140 and the layers to be etched 120 which are located adjacent to the side walls of the core layers 130, and the first grooves 20 extend along a first direction (shown in an X direction in fig. 12 a); a blocking layer 145 located in a portion of the first recess 20, wherein the blocking layer 145 fills the first recess 20 along a second direction (shown as a Y direction in fig. 13B), the second direction being perpendicular to the first direction, and the blocking layer 145 and the sidewall 140 are used as a mask for etching the layer to be etched 120.
In the semiconductor structure provided by the embodiment of the invention, the side wall 140 is only positioned on the side wall of the core layer 130, and the material (for example, a side wall film) of the side wall 140 is not arranged on the top of the core layer 130, so that even if the blocking layer 145 is positioned on part of the core layer 130, the blocking layer 145 does not cover the side wall film positioned on the core layer 130, and therefore, in the step of forming the blocking layer 145, the core layer 130 can be exposed by over-etching the blocking layer 145, and the subsequent steps further include removing the core layer 130, so that the core layer 130 is easily removed, the blocking layer 145 and the side wall 140 are ensured to be used as a mask for etching the layer to be etched 120, the precision of pattern transfer is further improved, and the formed target pattern meets the process requirements.
The substrate is used for providing a process platform for a process procedure.
In this embodiment, semiconductor devices such as transistors and capacitors may be formed in the substrate, and functional structures such as a resistor structure and a conductive structure may be formed in the substrate.
In this embodiment, the substrate includes an inter-metal dielectric layer 110, and the inter-metal dielectric layer 110 is used to achieve electrical isolation between interconnection lines in a back-end process.
The inter-metal dielectric layer 110 is used as a film layer to be patterned, and after the inter-metal dielectric layer 110 is subsequently patterned, an interconnection groove is formed and used for providing a space position for forming an interconnection line.
In this embodiment, the inter-metal dielectric layer 110 is made of an ultra-low k dielectric material. In particular, the ultra-low k dielectric material may be SiOCH.
The layer to be etched 120 is used as a film layer to be patterned to form a target pattern.
In this embodiment, the layer to be etched 120 is a metal hard mask material layer, and the layer to be etched 120 is located on the inter-metal dielectric layer 110.
And after the layer to be etched 120 is patterned subsequently, forming a metal hard mask layer on the metal hard mask material layer, wherein the metal hard mask layer is used as an etching mask for etching the metal interlayer dielectric layer 110 to form an interconnection trench. In this embodiment, the layer to be etched 120 is made of silicon nitride.
The core layer 130 is used for providing a supporting function for the formation of the sidewall 140.
In this embodiment, the material of the core layer 130 is amorphous silicon.
The sidewall spacers 140 are used as a mask for patterning the layer to be etched 120.
In this embodiment, the sidewall spacers 140 are made of titanium nitride.
In this embodiment, the sidewall 140 is only located on the sidewall of the core layer 130, which is beneficial to increase the process window for over-etching when forming the blocking layer 145.
The blocking layer 145 and the sidewall spacers 140 together serve as a mask for patterning the layer to be etched 120.
The blocking layer 145 fills the first groove 20 in the second direction, thereby breaking the first groove 20 in the first direction.
The material of the blocking layer 145 is a dielectric material. In this embodiment, the material of the blocking layer 145 includes silicon oxide. In other embodiments, the material of the blocking layer may also be other materials with higher etching selectivity with the layer to be etched and the core layer, such as silicon nitride, according to the materials of the layer to be etched and the core layer.
In this embodiment, the blocking layer 145 exposes the core layer 130, so that the blocking layer 145 is prevented from affecting subsequent removal of the core layer 130, which is beneficial to reducing the difficulty of subsequent removal of the core layer 130, and further, the core layer 130 is easily removed completely.
The semiconductor structure further includes: and the shielding layer 160 is filled in the first groove 20, the shielding layer 160 covers the top of the blocking layer 145, and the side wall of the shielding layer 160 along the first direction is flush with the side wall of the blocking layer 145.
The shielding layer 160 is used as a mask for subsequent removal of the core layer 130; and the blocking layer 145 exposes the core layer 130 because the blocking layer 145 on top of the core layer 130 was also previously removed, the blocking layer 160 also serves as a mask to remove the blocking layer 145 on top of the core layer 130.
In this embodiment, the material of the shielding layer 160 is an organic material. Specifically, the material of the shielding layer 160 may be an ODL material. The filling performance of the ODL is better, thereby improving the filling capability of the shielding layer 160 in the first groove 20.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a layer to be etched on the substrate;
forming a discrete core layer on the layer to be etched;
forming a side wall film on the top and the side wall of the core layer and the surface of the layer to be etched;
removing the side wall films positioned at the top of the core layer and on the surface of the layer to be etched, and reserving the residual side wall films positioned on the side wall of the core layer as side walls, wherein a plurality of first grooves are formed by the adjacent side walls positioned on the adjacent side walls of the core layer and the layer to be etched in a surrounding manner, and the first grooves extend along a first direction;
forming a blocking layer in a portion of the first groove, the blocking layer filling the first groove along a second direction, the second direction being perpendicular to the first direction;
after the blocking layer is formed, removing the core layer to form a second groove, wherein the second groove and the first groove are isolated by the side wall;
and etching the layers to be etched at the bottoms of the first groove and the second groove by taking the side walls and the blocking layer as masks to form a target pattern.
2. The method of claim 1, wherein the sidewall film on the top of the core layer and the surface of the layer to be etched is removed by an anisotropic dry etching process.
3. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the blocking layer, the blocking layer further covers a portion of the top of the core layer on both sides of the first recess;
the method for forming the semiconductor structure further comprises the following steps: after forming the blocking layer, the blocking layer on top of the core layer is removed before removing the core layer.
4. The method of forming a semiconductor structure of claim 3, wherein removing the blocking layer on top of the core layer comprises: forming a blocking layer which fills the first groove and covers the blocking layer, wherein the blocking layer exposes the blocking layer on the top of the core layer;
removing the blocking layer exposed by the shielding layer;
after the blocking layer exposed by the blocking layer is removed, the method for forming the semiconductor structure further comprises the following steps: and removing the shielding layer.
5. The method of claim 4, wherein the process of removing the blocking layer exposed by the blocking layer comprises a plasma etching process.
6. The method for forming the semiconductor structure according to claim 4, wherein in the step of removing the blocking layer exposed by the blocking layer, an etching selection ratio of the blocking layer to the side wall is greater than or equal to 5: 1.
7. the method according to claim 4, wherein the core layer is removed after removing the barrier layer exposed by the barrier layer and before removing the barrier layer;
the step of removing the core layer includes: and removing the core layer by taking the shielding layer and the blocking layer as masks.
8. The method according to claim 4, wherein the process for removing the blocking layer comprises an ashing process.
9. The method of forming a semiconductor structure of claim 1 or 3, wherein the step of forming the blocking layer comprises: forming a mask layer for filling the first groove on the core layer and the side wall, wherein a mask opening is formed in the mask layer, and the mask opening exposes the bottom and the side wall of part of the first groove;
filling a blocking material layer in the first groove exposed by the mask opening and the mask opening;
etching back part of the blocking material layer, wherein the rest blocking material layer is used as the blocking layer;
and removing the hard mask layer.
10. The method of claim 9, wherein the process of forming the blocking material layer comprises a chemical vapor deposition process.
11. The method of forming a semiconductor structure of claim 9, wherein the process of back-etching a portion of the thickness of the blocking material layer comprises a dry etching process.
12. The method of forming a semiconductor structure of claim 1, wherein the process of removing the core layer comprises a plasma etch process.
13. The method of forming a semiconductor structure of claim 1, wherein in the step of removing the core layer, an etch selectivity ratio of the core layer to the blocking layer is greater than or equal to 5: 1.
14. the method of forming a semiconductor structure of claim 1, wherein a material of the blocking layer comprises silicon oxide or silicon nitride.
15. The method of forming a semiconductor structure of claim 1, wherein the substrate comprises an inter-metal dielectric layer;
the layer to be etched is a metal hard mask material layer, and is positioned on the metal interlayer dielectric layer;
etching the layers to be etched at the bottoms of the first groove and the second groove by taking the side walls and the blocking layer as masks to form a metal hard mask layer;
after the metal hard mask layer is formed, the method for forming the semiconductor structure further comprises the following steps: and etching the metal interlayer dielectric layer by taking the metal hard mask layer as a mask, and forming a plurality of interconnection grooves in the metal interlayer dielectric layer.
16. A semiconductor structure, comprising:
a substrate;
a layer to be etched on the substrate;
the core layer is separated on the layer to be etched;
the side walls are positioned on the side walls of the layers to be etched, a plurality of first grooves are formed by the side walls adjacent to the side walls of the core layers and the layers to be etched in a surrounding mode, and the first grooves extend along a first direction;
and the blocking layer is positioned in part of the first groove, the blocking layer fills the first groove along a second direction, the second direction is vertical to the first direction, and the blocking layer and the side wall are used as masks for etching the layer to be etched.
17. The semiconductor structure of claim 16, wherein the blocking layer exposes the core layer.
18. The semiconductor structure of claim 17, wherein the semiconductor structure further comprises: the shielding layer is filled in the first groove, covers the top of the blocking layer, and is flush with the side wall of the blocking layer along the first direction.
19. The semiconductor structure of claim 16, wherein a material of the blocking layer comprises silicon oxide or silicon nitride.
20. The semiconductor structure of claim 16, wherein the substrate comprises an inter-metal dielectric layer;
the layer to be etched is a metal hard mask material layer, and the layer to be etched is located on the metal interlayer dielectric layer.
CN202010016189.9A 2020-01-08 2020-01-08 Semiconductor structure and forming method thereof Pending CN113097060A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103839769A (en) * 2012-11-20 2014-06-04 华邦电子股份有限公司 Method for forming patterns
US20180323067A1 (en) * 2017-05-05 2018-11-08 Globalfoundries Inc. Narrowed feature formation during a double patterning process
CN112928057A (en) * 2019-12-05 2021-06-08 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103839769A (en) * 2012-11-20 2014-06-04 华邦电子股份有限公司 Method for forming patterns
US20180323067A1 (en) * 2017-05-05 2018-11-08 Globalfoundries Inc. Narrowed feature formation during a double patterning process
CN112928057A (en) * 2019-12-05 2021-06-08 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

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