CN113096585B - Pixel driving device and driving method thereof - Google Patents
Pixel driving device and driving method thereof Download PDFInfo
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- CN113096585B CN113096585B CN202110400095.6A CN202110400095A CN113096585B CN 113096585 B CN113096585 B CN 113096585B CN 202110400095 A CN202110400095 A CN 202110400095A CN 113096585 B CN113096585 B CN 113096585B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
Abstract
A pixel driving device and a driving method thereof are provided, wherein the pixel driving device comprises a current source and a pulse width modulation circuit. The current source is used for generating current. The pulse width modulation circuit is used for resetting according to a reset signal or a previous first scanning signal in the first stage. The pulse width modulation circuit is used for generating a pulse width modulation signal according to the first scanning signal and the selection signal in the second stage and driving the current source according to the pulse width modulation signal so that the current source provides current to the light emitting element. The selection signal generates a pulse signal in the second stage according to one of the gray scales. The time point of the pulse signal generated in the second stage determines the working period of the pulse width modulation signal.
Description
Technical Field
The present disclosure relates to a display apparatus and method. In detail, the present disclosure relates to a pixel driving apparatus and a pixel driving method.
Background
In the structure of the conventional display, the data driving integrated circuit (integrated circuit, IC) is packaged between the glass substrate and the printed circuit board of the liquid crystal display by Chip On Film (COF) technology, so that data can be provided to the display panel by the data driving integrated circuit using the COF technology. However, the data driving integrated circuit using COF technology occupies a certain volume in the whole display and increases the production cost of the display. As can be seen, the data driving integrated circuit employing COF technology has a number of drawbacks, and those skilled in the art are required to develop other suitable data providing methods.
Disclosure of Invention
One aspect of the present disclosure relates to a pixel driving apparatus. The pixel driving device comprises a current source and a pulse width modulation circuit. The current source is used for generating current. The pulse width modulation circuit is used for resetting according to a reset signal or a previous first scanning signal in the first stage. The pulse width modulation circuit is used for generating a pulse width modulation signal according to the first scanning signal and the selection signal in the second stage and driving the current source according to the pulse width modulation signal so that the current source provides current to the light emitting element. The selection signal generates a pulse signal in the second stage according to one of the gray scales. The time point of the pulse signal generated in the second stage determines the working period of the pulse width modulation signal.
Another aspect of the present disclosure relates to a pixel driving method. The pixel driving method comprises the following steps: resetting the pulse width modulation circuit according to the reset signal or the previous first scanning signal in the first stage; and generating a pulse width modulation signal according to the first scanning signal and the selection signal in the second stage, and driving the current source according to the pulse width modulation signal so that the current source provides current to the light emitting element. The selection signal generates a pulse signal in the second stage according to one of the gray scales. The time point of the pulse signal generated in the second stage determines the working period of the pulse width modulation signal.
Drawings
The disclosure may be best understood with reference to the following paragraphs with reference to the embodiments and the following drawings:
fig. 1 is a schematic view of a part of a structure of a pixel driving device according to some embodiments of the present disclosure;
FIG. 2 is a flow chart illustrating steps of a pixel driving method according to some embodiments of the present disclosure;
FIG. 3 is a signal timing diagram illustrating a pixel driving method according to some embodiments of the present disclosure;
fig. 4 is a schematic view illustrating an element state of a pixel driving apparatus according to some embodiments of the present disclosure;
fig. 5 is a schematic view illustrating an element state of a pixel driving apparatus according to some embodiments of the present disclosure;
FIG. 6 is a partial block diagram of a pixel drive device shown in accordance with some embodiments of the present disclosure;
FIG. 7 is a signal timing diagram illustrating a pixel driving method according to some embodiments of the present disclosure;
fig. 8 is a schematic view illustrating an element state of a pixel driving apparatus according to some embodiments of the present disclosure;
fig. 9 is a schematic view illustrating an element state of a pixel driving device according to some embodiments of the present disclosure;
fig. 10 is a schematic view illustrating an element state of a pixel driving apparatus according to some embodiments of the present disclosure;
fig. 11 is a schematic view illustrating an element state of a pixel driving device according to some embodiments of the present disclosure;
fig. 12 is a schematic view showing an element state of a pixel driving device according to some embodiments of the present disclosure; and
fig. 13 is a schematic view illustrating an element state of a pixel driving device according to some embodiments of the present disclosure.
Reference numerals illustrate:
100: pixel driving device
110: pulse width modulation circuit
120: current source
VDD: power supply voltage (high potential)
VSS: power supply voltage (Low potential)
VREF1: first reference voltage
VREF2: second reference voltage
ST: signal signal
S1[ N ]: first scanning signal
Sel: selection signal
DT1: driving transistor
T1: first transistor
T2: second transistor
T3: third transistor
C1: first capacitor
N1: first node
L: light-emitting element
T4: fourth transistor
200: method of
210 to 220: step (a)
R < N >: reset signal
S1[ N-1], S1[ N ]: first scanning signal
Sel1 to Sel5: selection signal
I1: first stage
I2: second stage
Duty1 to Duty4: duty cycle of pulse width signal
P1 to P4: time point of generating pulse signal
600: pixel driving device
610: pulse width modulation circuit
620: current source
VDD: power supply voltage (high potential)
VSS: power supply voltage (Low potential)
VREF1: first reference voltage
VREF2: second reference voltage
ST: signal signal
S1[ N ]: first scanning signal
S2[ N ], S2[ N+1]: second scanning signal
Sel: selection signal
DT1: driving transistor
T1: first transistor
T2: second transistor
T3: third transistor
C1: first capacitor
N1: first node
L: light-emitting element
C2: second capacitor
N2 second node
T4: fourth transistor
T5: fifth transistor
T6: sixth transistor
T7: seventh transistor
T8: eighth transistor
T9: ninth transistor
R < N >: reset signal
S1[ N-1], S1[ N ]: first scanning signal
S2[ N-2], S2[ N-1], S2[ N ], S2[ N+1]: second scanning signal
Sel1 to Sel4: selection signal
I1: first stage
I11, I12, I13, I14: sub-stage
I2: second stage
I21, I22: sub-stage
Duty1 to Duty3: duty cycle of pulse width signal
P1 to P3: time point of generating pulse signal
Detailed Description
The following drawings and detailed description clearly illustrate the concepts of the present disclosure and, after understanding the embodiments of the present disclosure, anyone skilled in the art can make changes and modifications to the techniques taught by the present disclosure without departing from the spirit and scope of the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. Singular forms such as "a," "an," "the," and "the" as used herein also include plural forms.
As used herein, the terms "comprising," "including," "having," "containing," and the like are intended to be inclusive and mean an inclusion, but not limited to.
With respect to terms (terms) used herein, unless otherwise noted, it is generally intended that each term be used in the art, throughout this disclosure and in the ordinary meaning of the special context. Certain terms used to describe the disclosure are discussed below, or elsewhere in this specification, to provide additional guidance to those skilled in the art in describing the disclosure.
Fig. 1 is a schematic view of a part of a structure of a pixel driving device according to some embodiments of the present disclosure. As shown in fig. 1, in some embodiments, the pixel driving device 100 includes a pulse width modulation circuit 110 and a current source 120. In some embodiments, a display device includes a plurality of pixels. Each pixel includes at least one pixel driving device 100.
In some embodiments, referring to fig. 1, the pwm circuit 110 includes a first capacitor C1, a first transistor T1, a second transistor T2, a third transistor T3, a driving transistor DT1, and a light emitting element L. The first capacitor C1 includes a first terminal and a second terminal, which are shown as the first terminal above and to the right of the device. The first transistor T1 includes a first terminal, a second terminal and a control terminal. The first end and the second end of the first transistor T1 are connected in parallel to the first end and the second end of the first capacitor C1. The second terminal of the first capacitor C1 and the second terminal of the first transistor T1 receive the power supply voltage VDD (e.g., the system high voltage). The control terminal of the first transistor T1 is turned on according to the signal ST. The first node N1 is located at a first end of the first capacitor C1.
In addition, the second transistor T2 includes a first terminal, a second terminal and a control terminal. The first terminal of the second transistor T2 is electrically connected to the first terminal of the first capacitor C1 and the first terminal of the first transistor T1. The control terminal of the second transistor T2 is turned on according to the selection signal Se 1. The third transistor T3 includes a first terminal, a second terminal and a control terminal. The first end of the third transistor T3 is connected in series to the second end of the second transistor T2. The second terminal of the third transistor T3 receives the first reference voltage VREF1. The control terminal of the third transistor T3 is turned on according to the scan signal S1[ N ].
In addition, the driving transistor DT1 includes a first terminal, a second terminal, and a control terminal. The first terminal of the driving transistor DT1 is electrically connected to the current source 120. The second terminal of the driving transistor DT1 is electrically connected to the first terminal of the light emitting element L. The control terminal of the driving transistor DT1 and the first capacitor C1 are electrically connected to the first node N1. The second terminal of the light emitting element L receives the power supply voltage VSS (e.g., system low).
In some embodiments, referring to fig. 1, the current source 120 includes a fourth transistor T4. The fourth transistor T4 includes a first terminal, a second terminal and a control terminal. The first terminal of the fourth transistor T4 receives the power supply voltage VDD (e.g., the system high voltage). The second terminal of the fourth transistor T4 is electrically connected to the first terminal of the driving transistor DT1 in the pwm circuit 110. The control terminal of the fourth transistor T4 receives the second reference voltage VREF2.
Fig. 2 is a flow chart illustrating steps of a pixel driving method according to some embodiments of the present disclosure. As shown in fig. 2, in some embodiments, the pixel driving method 200 may be performed by the pixel driving apparatus 100 shown in fig. 1.
In addition, for easy understanding of the pixel driving method 200, please refer to fig. 3, fig. 4 and fig. 5 together, wherein fig. 3 is a signal timing diagram of the pixel driving method according to some embodiments of the disclosure. Fig. 4 is a schematic diagram illustrating the states of elements of the pixel driving device according to some embodiments of the present disclosure, which corresponds to the pixel driving device 100 of fig. 1. Fig. 5 is a schematic diagram illustrating the states of elements of the pixel driving device according to some embodiments of the present disclosure, which corresponds to the pixel driving device 100 of fig. 1.
In step 210, the pwm circuit is reset according to the reset signal or the first scan signal in the first stage.
In some embodiments, referring to fig. 2, 3 and 4, the pwm circuit 110 resets the pwm circuit 110 according to the signal ST in the first stage I1. In some embodiments, the signal ST may be a reset signal R [ N ] or a preceding first scan signal S1[ N-1].
For example, the first transistor T1 is turned on in the first stage I1 according to the reset signal R [ N ] or the first scan signal S1[ N-1] of the previous stage, and the power supply voltage VDD resets the first node N1 of the first capacitor C1 to a high level through the first transistor T1.
In step 220, a pwm signal is generated according to the first scan signal and the selection signal in the second stage, and the current source is driven according to the pwm signal, so that the current source provides current to the light emitting device.
In some embodiments, referring to fig. 2, 3 and 4, the pwm circuit 110 generates a pwm signal according to the first scan signal S1[ N ] and the selection signal Sel in the second stage I2, and drives the current source 120 according to the pwm signal, so that the current source 120 provides a current to the light emitting element L.
In some embodiments, referring to fig. 3, the selection signals Sel1 to Sel5 generate the pulse signal in the second stage I2 according to one of the gray scales. The pulse signal determines the duty cycle of the pwm signal at the time point of the second phase I2 generation.
Further, referring to fig. 3, the select signals Se11 to Se15 are arranged from top to bottom according to the gray scale size. As shown in fig. 3, the selection signal Se11 corresponds to a high gray level, the selection signal Se12 corresponds to a medium and high gray level, the selection signal Se13 corresponds to a medium and low gray level, the selection signal Sel4 corresponds to a low gray level, and the selection signal Se15 corresponds to a zero gray level. In some embodiments, the time point of the pulse signal generated in the second phase I2 is determined according to different selection signals, so as to determine different duty cycles of the pwm signal.
For example, referring to fig. 1 and 3, in the second stage I2, the second transistor T2 generates a pulse signal according to the selection signal Sel1, and determines the Duty cycle Duty1 of the pwm signal according to the time point P1 of the pulse signal generation. In some embodiments, the second transistor T2 can generate the corresponding pulse signals at the time points P2, P3 and P4 according to different selection signals, such as the selection signal Sel2, the selection signal Sel3 and the selection signal Sel4, in the second stage I2.
For example, referring to fig. 3 and 5, in the second stage I2, when the second transistor T2 is turned on according to the selection signal Sel1 and the third transistor T3 is turned on according to the first scan signal S1[ N ] to generate the pulse signal, the second transistor T2 of the pwm circuit 110 rewrites the potential of the first node N1 of the first capacitor C1 according to the time point P1 when the pulse signal is generated, and at this time, the first reference voltage VREF1 rewrites the original high potential of the first node N1 to the low potential through the second transistor T2 and the third transistor T3. Next, the rewritten first node N1 maintains a low potential to turn on the driving transistor DT1. Subsequently, the driving transistor DT1 of the pwm circuit 110 drives the current source 120 according to the pwm signal, and continuously causes the current source 120 to supply current to the light emitting element L. It should be noted that the second transistor T2 of the pwm circuit 110 may employ different selection signals to generate corresponding driving steps, and in this embodiment, the selection signal Sel1 is taken as an example for illustration. Since the driving steps of the second transistor T2 using the selection signals Sel2, sel3, sel4 and Sel5 are similar to the driving steps using the selection signal Sel1, the description is omitted for brevity.
Fig. 6 is a partial block diagram of a pixel driving device according to some embodiments of the present disclosure. As shown in fig. 6, in some embodiments, the pixel driving device 600 includes a pulse width modulation circuit 610 and a current source 620.
In some embodiments, referring to fig. 1 and 6, the pixel driving apparatus 600 corresponds to the pixel driving apparatus 100 of fig. 1 and additional electronic components are added to the pixel driving apparatus 100, thereby increasing the functions of the pixel driving apparatus.
In some embodiments, referring to fig. 1 and 6, the pwm circuit 610 further includes a ninth transistor T9 as compared to the pwm circuit 110. The ninth transistor T9 includes a first terminal, a second terminal and a control terminal. A second terminal of the ninth transistor T9 is electrically connected to a second terminal of the driving transistor DT1. The first end of the ninth transistor T9 is electrically connected to the control end of the ninth transistor T9, and is turned on according to the secondary second scan signal s2[ n+1 ]. The rest of the pwm circuit 610 is the same as the pwm circuit 110 of fig. 1, and is not described herein for brevity.
In some embodiments, referring to fig. 1 and 6, the current source 620 additionally includes a second capacitor C2, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8 compared to the current source 120. The rest of the structure of the current source 620 is the same as the current source 120 of fig. 1, and is not described herein for brevity.
Referring to fig. 6, the second capacitor C2 includes a first end and a second end. The first terminal of the second capacitor C2 is electrically connected to the control terminal of the fourth transistor T4. The fifth transistor T5 includes a first terminal, a second terminal and a control terminal. The first end of the fifth transistor T5 receives the first reference voltage VREF1, the second end of the fifth transistor T5 is electrically connected to the second end of the second capacitor C2, and the control end of the fifth transistor T5 is configured to receive the signal of the first node N1 of the pwm circuit 610 and is turned on according to the signal of the first node N1. The sixth transistor T6 includes a first terminal, a second terminal and a control terminal. The first terminal of the sixth transistor T6 is electrically connected to the second terminal of the second capacitor C2. The second terminal of the sixth transistor T6 receives the second reference voltage VREF2. The control terminal of the sixth transistor T6 is turned on according to the second scan signal S2[ N ]. The second node N2 is located at a first end of the second capacitor C2.
Furthermore, the seventh transistor T7 includes a first terminal, a second terminal and a control terminal. The first terminal of the seventh transistor T7 is electrically connected to the first terminal of the second capacitor C2. The second terminal of the seventh transistor T7 is electrically connected to the second terminal of the second transistor T2 and the first terminal of the third transistor T3 of the pwm circuit 610. The control terminal of the seventh transistor T7 is turned on according to the second scan signal S2[ N ]. The eighth transistor T8 includes a first terminal, a second terminal and a control terminal. The first terminal of the eighth transistor T8 is electrically connected to the second terminal of the fourth transistor. The second terminal of the eighth transistor T8 is electrically connected to the second terminal of the seventh transistor and to the second terminal of the second transistor T2 and the first terminal of the third transistor T3 of the pwm circuit 610. The control terminal of the eighth transistor T8 is turned on according to the second scan signal S2[ N ].
Fig. 7 is a signal timing diagram of a pixel driving method according to some embodiments of the present disclosure. As shown in fig. 7, in some embodiments, the pixel driving apparatus 600 of fig. 6 further includes electronic components to implement the function of the compensation circuit, and compared with the signal timing diagram of fig. 3, the signal timing diagram of fig. 7 is divided into a plurality of sub-stages I11, I12, I13 and I14 in the first stage I1, and the function of the compensation circuit is implemented by a driving method of the plurality of sub-stages. Fig. 8 to 13 are schematic views illustrating states of elements of a pixel driving apparatus according to some embodiments of the present disclosure, which correspond to the pixel driving apparatus 600 of fig. 6.
In some embodiments, first, fig. 8 is a schematic diagram illustrating the state of the pixel driving device 600 in the first sub-stage I11 of the first stage I1 in fig. 7. Next, the control terminal of the first transistor T1 of the pwm circuit 610 in fig. 8 is turned on according to the signal ST, and the power supply voltage VDD resets the first node N1 of the first capacitor C1 to a high level through the first transistor T1. In some embodiments, the signal ST received by the control terminal of the first transistor T1 in FIG. 8 can be different scan signals, such as the reset signal R [ N ] or the pre-stage first scan signal S1[ N-1] or the pre-stage second scan signal S2[ N-2] in FIG. 7.
In some embodiments, referring to fig. 2, 7 and 8, in the first sub-stage I11 of the first stage I1, the first transistor T1 of the pwm circuit 610 is turned on according to the signal ST, and the power supply voltage VDD resets the first node N1 of the first capacitor C1 to a high level through the first transistor T1. In some embodiments, the signal ST of FIG. 7 can be the reset signal R [ N ] or the pre-stage first scan signal S1[ N-1] or the pre-stage second scan signal S2[ N-2] of FIG. 8.
In some embodiments, first, fig. 9 is a schematic diagram illustrating the state of the pixel driving device 600 in the second sub-stage I12 of the first stage I1 in fig. 7. Next, the third transistor T3 of the pwm circuit 610 in fig. 9 is turned on according to the first scan signal S1[ N ], and the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 of the current source 620 are turned on according to the second scan signal S2[ N ] to reset the potential of the second node N2 of the second capacitor C2.
In some embodiments, first, fig. 10 is a schematic diagram illustrating the state of the pixel driving device 600 in the third sub-stage I13 of the first stage I1 in fig. 7. Next, in fig. 10, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 of the current source 620 are turned on according to the second scan signal S2[ N ] and compensate the second node N2 of the second capacitor C2 of the current source 620, compared to fig. 9, the third transistor T3 of the pwm circuit 610 at this stage is turned off.
In some embodiments, first, fig. 11 is a schematic diagram illustrating the state of the pixel driving device 600 in the fourth sub-stage I14 of the first stage I1 in fig. 7. Next, in fig. 11, the driving transistor DT1 of the pwm circuit 610 is turned off according to the potential of the first node N1, and the ninth transistor T9 of the pwm circuit 610 is turned on according to the secondary second scan signal S2[ N ] and resets the potential of the light emitting element L.
In some embodiments, first, fig. 12 is a schematic diagram illustrating the state of the pixel driving device 600 in the first sub-stage I21 of the second stage I2 in fig. 7. In fig. 12, all transistors of the pwm circuit 610 or all transistors of the current source 620 are not turned on, so that the first node N1 of the first capacitor C1, the second node N2 of the second capacitor C2 and the light emitting element L maintain the originally reset potential.
In some embodiments, first, fig. 13 is a schematic diagram illustrating the state of the pixel driving device 600 in the second sub-stage I22 of the second stage I2 in fig. 7. The second transistor T2 of the pwm circuit 610 in fig. 13 is turned on according to the selection signal Sel and the third transistor T3 generates a pwm signal according to the first scan signal S1N, and the driving transistor DT1 of the pwm circuit 610 of Zhong Chong drives the current source 620 according to the pwm signal, so that the current source 620 provides a current to the light emitting element L. In some embodiments, the second transistor T2 in fig. 13 can select the signal Sel1, the selection signal Sel2 and the selection signal Sel3 in fig. 7 according to different selection signals in the second sub-stage I22 to generate the corresponding pulse signal points P1, P2 and P3, thereby providing the pwm signals with different duty cycles.
In some embodiments, referring to fig. 6 and 7, the signal ST received by the first transistor T1 of the pwm circuit 610 can be different scan signals according to different circuit layouts of the pixel driving device 600. For example, if the pixel driving device 600 is a middle-sized circuit layout area and middle-sized current compensation is required, the first transistor T1 of the pulse width modulation circuit 610 is turned on according to the reset signal R [ N ]. In addition, if the pixel driving apparatus 600 is a small circuit layout area and requires large current compensation, the first transistor T1 of the pulse width modulation circuit 610 is turned on according to the first scan signal S1[ N-1] of the previous stage. In addition, if the pixel driving device 600 is a large circuit layout area and requires large current compensation, the first transistor T1 of the pulse width modulation circuit 610 is turned on according to the second scan signal S2[ N-2].
In some embodiments, referring to fig. 1 and 3, the pixel driving apparatus 100 is operated by the signals of the first stage I1 and the second stage I2, i.e. updated by one pixel frame number (Frame time or Frames per second).
In some embodiments, referring to fig. 6 and 7, the pixel driving apparatus 600 is operated by the signals of the first stage I1 and the second stage I2, i.e. the pixel frame number is updated once.
In some embodiments, the current of the pixel driving apparatus 100 or 600 after one pixel frame number update is determined according to the first reference voltage VREF1 and the second reference voltage VREF2.
According to the foregoing embodiments, the present disclosure provides a pixel driving apparatus. The display adopting the pixel driving device does not need to additionally arrange a data driving integrated Circuit (COF) technology, so the display adopting the pixel driving device can reduce the production cost.
Although the present disclosure has been disclosed above with reference to specific examples, the present disclosure does not preclude other possible implementations. Accordingly, the scope of the disclosure is defined by the appended claims rather than by the foregoing description.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit or scope of the disclosure. All modifications and variations of the disclosure based on the above embodiments are also within the scope of the disclosure.
Claims (10)
1. A pixel driving device, comprising:
a current source for generating a current; and
the pulse width modulation circuit is used for resetting according to a reset signal or a first scanning signal of a previous stage in a first stage, wherein the pulse width modulation circuit is used for generating a pulse width modulation signal according to a first scanning signal and a selection signal in a second stage, and driving the current source according to the pulse width modulation signal so that the current source provides the current to a light emitting element, wherein the selection signal generates a pulse signal in the second stage according to one of a plurality of gray scales, and the pulse signal determines a working period of the pulse width modulation signal at a time point generated in the second stage.
2. The pixel driving device according to claim 1, wherein the pulse width modulation circuit comprises:
a first capacitor including a first end and a second end;
the first transistor comprises a first end, a second end and a control end, wherein the first end and the second end of the first transistor are connected in parallel and are electrically connected with the first end and the second end of the first capacitor, and the control end of the first transistor is used for resetting the first capacitor to a high potential according to the reset signal or the front-stage first scanning signal in the first stage;
the second transistor comprises a first end, a second end and a control end, wherein the first end of the second transistor is electrically connected with the first end of the first capacitor, the control end of the second transistor is used for conducting according to the pulse signal of the selection signal in the second stage, and the high potential of the first capacitor is rewritten into a low potential at the time point of the second stage to generate the pulse width modulation signal;
the third transistor comprises a first end, a second end and a control end, wherein the first end of the third transistor is connected in series and electrically connected with the second end of the second transistor, the second end of the third transistor is used for receiving a first reference voltage, and the control end of the third transistor is used for conducting the second stage according to the first scanning signal; and
the driving transistor comprises a first end, a second end and a control end, wherein the first end of the driving transistor is electrically connected with the current source, the second end of the driving transistor is electrically connected with the light-emitting element, the control end of the driving transistor is electrically connected with the first end of the first capacitor and is used for driving the current source according to the pulse width modulation signal, so that the current source provides the current to the light-emitting element.
3. A pixel driving apparatus according to claim 2, wherein the current source comprises:
the second end of the fourth transistor is electrically connected with the first end of the driving transistor of the pulse width modulation circuit, the first end of the fourth transistor is used for receiving a power supply voltage, and the control end of the fourth transistor is used for receiving the first reference voltage.
4. A pixel driving apparatus according to claim 3, wherein the current source further comprises:
a second capacitor including a first end and a second end, wherein the first end of the second capacitor is electrically connected to the control end of the fourth transistor;
a fifth transistor, comprising a first end, a second end and a control end, wherein the first end of the fifth transistor is used for receiving the first reference voltage, the second end of the fifth transistor is electrically connected with the second end of the second capacitor, the control end of the fifth transistor is electrically connected with the first capacitor of the pulse width modulation circuit and is used for conducting according to the low potential of the first capacitor of the pulse width modulation circuit in the second stage;
a sixth transistor, including a first end, a second end and a control end, wherein the first end of the sixth transistor is electrically connected to the second end of the second capacitor, the second end of the sixth transistor is used for receiving a second reference voltage, and the control end of the sixth transistor is used for being conducted according to a second scanning signal in the first stage;
a seventh transistor, comprising a first end, a second end and a control end, wherein the first end of the seventh transistor is electrically connected to the pwm circuit, the second end of the seventh transistor is electrically connected to the first end of the second capacitor, and the control end of the seventh transistor is used for conducting according to the second scan signal in the first stage; and
the eighth transistor comprises a first end, a second end and a control end, wherein the first end of the eighth transistor is electrically connected with the second end of the first transistor, the second end of the eighth transistor is electrically connected with the first end of the fourth transistor and is electrically connected with the pulse width modulation circuit, and the control end of the eighth transistor is used for being conducted according to the second scanning signal in the first stage.
5. The pixel driving device according to claim 4, wherein the pulse width modulation circuit further comprises:
the second end of the ninth transistor is electrically connected with the second end of the driving transistor, the first end of the ninth transistor is electrically connected with the control end of the ninth transistor, and the control end of the ninth transistor is used for resetting the light emitting element according to a secondary second scanning signal in the first stage.
6. A pixel driving method, comprising:
resetting a pulse width modulation circuit according to a reset signal or a previous stage first scanning signal in a first stage; and
generating a pulse width modulation signal according to a first scanning signal and a selection signal in a second stage, and driving a current source according to the pulse width modulation signal so that the current source provides a current to a light emitting element, wherein the selection signal generates a pulse signal in the second stage according to one of a plurality of gray scales, and the pulse signal determines a working period of the pulse width modulation signal at a time point generated in the second stage.
7. The method of claim 6, wherein resetting the pwm circuit according to the reset signal or the pre-stage first scan signal in the first stage comprises:
a first capacitor of the PWM circuit is reset to a high voltage level.
8. The method of claim 7, wherein generating the pwm signal according to the first scan signal and the selection signal in the second stage comprises:
the pulse signal according to the selection signal turns on the pulse width modulation circuit, and rewrites the high potential of the first capacitor of the pulse width modulation circuit to a low potential at the time point of the second stage to generate the pulse width modulation signal.
9. The pixel driving method according to claim 6, further comprising:
resetting a second capacitor of a current source according to a second scanning signal in the first stage; and
the current source is compensated according to the second scanning signal in the first stage.
10. The pixel driving method according to claim 9, further comprising:
the light emitting element is reset according to the second scanning signal in the first stage.
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| TW109140877A TWI765423B (en) | 2020-11-20 | 2020-11-20 | Pixel driving device and driving method thereof |
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| TW202221687A (en) | 2022-06-01 |
| TWI765423B (en) | 2022-05-21 |
| CN113096585A (en) | 2021-07-09 |
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