CN111179830B

CN111179830B - Shift register, display device and driving method thereof

Info

Publication number: CN111179830B
Application number: CN202010063718.0A
Authority: CN
Inventors: 董哲维; 林炜力
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2019-07-16
Filing date: 2020-01-20
Publication date: 2021-07-20
Anticipated expiration: 2040-01-20
Also published as: TW202105342A; CN111179830A; TWI699744B

Abstract

A driving method for a display device. The display device comprises a shift register and a control circuit. The control circuit is used for providing a trigger signal, a first voltage, a second voltage, a third voltage, m high-frequency clock pulse signals and a low-frequency clock pulse signal to the shift register. The driving method comprises the following steps: when the control circuit judges that the power input is higher than a first preset voltage, the first voltage, the second voltage, the third voltage, the m high-frequency clock pulse signals and the low-frequency clock pulse signals are maintained at a logic low potential until the trigger signal is switched from the logic high potential to the logic low potential so as to reset the voltages of a plurality of internal nodes of the shift register; the trigger signal, the m high-frequency clock pulse signals, the low-frequency clock pulse signal and the first voltage are periodically switched between a logic high potential and a logic low potential by using the control circuit so as to update the display picture of the display device.

Description

Shift register, display device and driving method thereof

Technical Field

The present invention relates to a shift register, a display device and a driving method thereof, and more particularly, to a driving method for removing residual charges in a display device.

Background

In order to meet the demand of the consumer market for narrow-bezel displays, the conventional driving IC is replaced by a gate driver fabricated on a glass substrate. When the gate driver completes the frame update of one frame, the gate driver temporarily stops the shift register operation. However, the conventional driving method does not clear the residual charges in the gate driver and the gate lines after the display frame of each frame is updated, so that the internal components of the gate driver and the display may be degraded due to long-term bias.

Disclosure of Invention

In order to solve the above technical problem, the present invention provides a shift register, which includes n stages of shift register units, where n is a positive integer. Each of the n-stage shift register units includes an output circuit and a voltage stabilizing and resetting circuit. The output circuit comprises a first node, a first output end and a second output end, is used for transmitting a first voltage to the first node and is used for outputting a corresponding one of m high-frequency clock pulse signals at the first output end and the second output end according to the voltage of the first node, and m is a positive integer. The voltage stabilizing and resetting circuit is used for transmitting the second voltage to the first node according to the low-frequency clock pulse signal and transmitting the second voltage and the third voltage to the first output end and the second output end respectively according to the trigger signal. The shift register is coupled to the control circuit. When the control circuit judges that the power input rises to be higher than the first preset voltage, the trigger signal is switched to a logic high potential, and the m high-frequency clock pulse signals, the low-frequency clock pulse signals, the first voltage, the second voltage and the third voltage are maintained at a logic low potential until the trigger signal is switched from the logic high potential to the logic low potential so as to reset the voltage of the first node.

In order to better achieve the above object, the present invention provides a driving method, which is suitable for a display device. The display device includes a shift register and a control circuit. The control circuit is used for providing a trigger signal, a first voltage, a second voltage, a third voltage, m high-frequency clock pulse signals and a low-frequency clock pulse signal to the shift register. The driving method includes the following steps: when the control circuit judges that the power input is higher than a first preset voltage, the control circuit switches the trigger signal to a logic high potential, and maintains the first voltage, the second voltage, the third voltage, the m high-frequency clock pulse signals and the low-frequency clock pulse signal at a logic low potential until the trigger signal is switched from the logic high potential to the logic low potential so as to reset the voltages of a plurality of internal nodes of the shift register; the trigger signal, the m high-frequency clock pulse signals, the low-frequency clock pulse signal and the first voltage are periodically switched between a logic high potential and a logic low potential by using the control circuit so as to update the display picture of the display device.

In order to better achieve the above object, the present invention provides a display device including a control circuit and a shift register. The shift register is used for receiving a trigger signal, a first voltage, a second voltage, a third voltage, m high-frequency clock pulse signals and a low-frequency clock pulse signal from the control circuit, and comprises n stages of shift register units, wherein n is a positive integer. Each of the n-stage shift register units includes an output circuit and a voltage stabilizing and resetting circuit. The output circuit comprises a first node, a first output end and a second output end, is used for transmitting a first voltage to the first node and is used for outputting a corresponding one of m high-frequency clock pulse signals at the first output end and the second output end according to the voltage of the first node, and m is a positive integer. The voltage stabilizing and resetting circuit is used for transmitting the second voltage to the first node according to the low-frequency clock pulse signal and transmitting the second voltage and the third voltage to the first output end and the second output end respectively according to the trigger signal. The shift register is coupled to the control circuit. When the control circuit judges that the power input rises to be higher than the first preset voltage, the trigger signal is switched to a logic high potential, and the m high-frequency clock pulse signals, the low-frequency clock pulse signals, the first voltage, the second voltage and the third voltage are maintained at a logic low potential until the trigger signal is switched from the logic high potential to the logic low potential so as to reset the voltage of the first node.

The shift register, the driving method and the display device can prevent the internal elements of the shift register and the display device from being aged due to long-time bias.

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

Drawings

Fig. 1 is a simplified functional block diagram of a display device according to an embodiment of the invention.

FIG. 2 is a simplified functional block diagram of a shift register according to an embodiment of the present invention.

FIG. 3 is a block diagram of a shift register unit according to an embodiment of the present invention.

FIG. 4 is a block diagram of a shift register unit according to another embodiment of the present invention.

Fig. 5 is a simplified functional block diagram of the control circuit of fig. 1.

Fig. 6 is a flowchart of a driving method according to an embodiment of the invention.

Fig. 7 is a waveform diagram illustrating a display operation of the display device.

FIG. 8 is a waveform diagram of a portion of signals input to the shift register during a frame time.

Fig. 9 is a flowchart of a driving method according to another embodiment of the invention.

Fig. 10 and 11 are waveform diagrams illustrating the display device of fig. 1 exposed to different kinds of power-off events.

Reference numerals

100: display device

110: control circuit

112: sequential control circuit

114: level shifter

116: power unit

118: diode with a high-voltage source

120: source driver

130: gate driver

140: pixel

DL 1-DLn: data line

GL 1-GLn: multiple gate lines

200: shift register

210[1] to 210[ n ], 300, 400: shift register unit

VGH: first voltage

And VQ: second voltage

VG: third voltage

ST: trigger signal

HC 1-HCm: high frequency clock pulse signal

LC1, LC 2: low frequency clock pulse signal

G [1] -G [ n ]: grid signal

S [1] -S [ n ]: shift signal

310: output circuit

320: voltage stabilizing and resetting circuit

322: reset unit

324: pull-down unit

326a, 326 b: voltage stabilizing unit

T1-T16: transistor with a metal gate electrode

C1: capacitor with a capacitor element

CS: capacitor with a capacitor element

O1: a first output terminal

O2: second output terminal

N1, N1[ m-2 ]: first node

N2: second node

N3: third node

N4: fourth node

PW1, PW 2: electric power input

DDS: data driving control signal

CIP: clock pulse control signal

600. 900: driving method

S602 to S608, S910 to S916: step (ii) of

E1, E2: time period

F1, F2, F3, F4: time period

Detailed Description

The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:

fig. 1 is a simplified functional block diagram of a display device 100 according to an embodiment of the invention. The display device 100 includes a control circuit 110, a source driver 120, a gate driver 130, a plurality of data lines DL 1-DLn, a plurality of gate lines GL 1-GLn, and a plurality of pixels 140. The control circuit 110 is used for providing a data driving control signal to the source driver 120, so that the source driver 120 generates a plurality of data signals. The control circuit 110 is further configured to provide a plurality of clock signals and a plurality of reference voltages to the gate driver 130, so that the gate driver 130 generates a plurality of gate signals.

The plurality of pixels 140 are disposed at a plurality of intersections of the data lines DL1 to DLn and the gate lines GL1 to GLn, respectively. Each pixel 140 receives a data signal and a gate signal via a corresponding one of the data lines DL 1-DLn and a corresponding one of the gate lines GL 1-GLn, respectively, for data writing, internal element characteristic compensation, and/or light emission.

In practice, the display device 100 may be a liquid crystal display, an Organic Light-Emitting Diode (OLED) display, or a Micro LED (Micro LED) display. For simplicity and ease of illustration, other elements and connections in the display device 100 are not shown in fig. 1.

FIG. 2 is a simplified functional block diagram of a shift register 200 according to an embodiment of the present invention. The shift register 200 can be disposed in the gate driver 130 of FIG. 1 for sequentially outputting a plurality of gate signals G [1] G [ n ] to the gate lines GL1 GLn according to the high frequency clock signals HC 1-HCm, the low frequency clock signals LC1 and LC2, the trigger signal ST, the first voltage VGH, the second voltage VQ, and the third voltage VG, and for sequentially outputting a plurality of shift signals S [1] S [ n ] to trigger the shift register operation in the shift register 200.

In the present embodiment, the high frequency clock signals HC1 to HC HCm have the same frequency but different phases, and m and n are positive integers, where m is smaller than n.

Shift register 200 includes n stages of shift register cells 210[1] to 210[ n ], each of shift register cells 210[1] to 210[ n ] for outputting a corresponding one of gate signals G [1] to G [ n ] and a corresponding one of shift signals S [1] to S [ n ]. The shift register units 210[1] to 210[ n ] belong to m phases, and the shift register units in the same phase are coupled in series. Therefore, the gate signals G [1] to G [ n ] and the shift signals S [1] to S [ n ] are also assigned to m phases. In addition, pulses of gate signals of the same phase do not overlap each other, but pulses of gate signals of different phases may overlap each other.

In the present embodiment, the gate driving units of the same phase are coupled across the m stages of gate driving units, and sequentially trigger the shift register operations of each other. For example, the 1 st stage shift register unit 210[1] outputs the shift signal S [1] to the shift register unit 210[ m +1] to trigger the shift register unit 210[ m +1] to perform the shift register operation. For another example, the shift register unit 210[2] of the 2 nd stage outputs the shift signal S [2] to the shift register unit 210[ m +2] to trigger the shift register unit 210[ m +2 ]. In this way, the m-th stage 210[ m ] outputs the shift signal S [ m ] to the shift register unit 210[ m + m ].

In addition, the shift register operation of the 1 ST stage shift register unit (e.g., the shift register units 210[1] to 210[ m ]) of each phase is triggered by the trigger signal ST.

FIG. 3 is a simplified functional block diagram of a shift register unit 300 according to an embodiment of the present invention. Shift register cell 300 can be used to implement shift register cells 210[1] 210[ m ] of FIG. 2. for illustrative purposes, FIG. 3 shows the m-th stage of shift register cells (e.g., shift register cell 210[ m ]). The shift register unit 300 includes an output circuit 310 and a voltage stabilizing and resetting circuit 320. The output circuit 310 includes a first node N1, a first output terminal O1, and a second output terminal O2, for transmitting a first voltage VGH to the first node N1 according to the trigger signal ST, and for outputting a corresponding one of the high frequency clock signals HC 1-HCm (e.g., the high frequency clock signal HCm) at the first output terminal O1 and the second output terminal O2 according to the voltage at the first node N1.

The voltages of the first output terminal O1 and the second output terminal O2 are respectively used as a corresponding one of the shift signals S [1] S [ m ] and a corresponding one of the gate signals G [1] G [ m ]. For example, if the shift register unit 300 is the shift register unit 210[1], the shift register unit 300 outputs the shift signal S [1] and the gate signal G [1 ]. For another example, if the shift register unit 300 is the shift register unit 210[2], the shift register unit 300 outputs the shift signal S [2] and the gate signal G [2 ]. By analogy, if the shift register unit 300 is the shift register unit 210[ m ], the shift register unit 300 outputs the shift signal S [ m ] and the gate signal G [ m ].

The output circuit 310 includes transistors T1-T3 and a capacitor C1. The transistor T1 has a first terminal for receiving the first voltage VGH, a second terminal coupled to the first node N1, and a control terminal for receiving the trigger signal ST. The capacitor C1 is coupled between the first node N1 and the second output terminal O2. The first terminal of the transistor T2 and the first terminal of the transistor T3 are used to receive a corresponding one of the high frequency clock pulse signals HC1 to HCm. For example, if the shift register cell 300 is the shift register cell 210[1], the first terminal of the transistor T2 and the first terminal of the transistor T3 are used for receiving the high frequency clock signal HC 1. For another example, if the shift register cell 300 is the shift register cell 210[2], the first terminal of the transistor T2 and the first terminal of the transistor T3 are used for receiving the high frequency clock signal HC 2. Similarly, if the shift register cell 300 is the shift register cell 210 m, the first terminal of the transistor T2 and the first terminal of the transistor T3 are used for receiving the high frequency clock signal HCm.

The second terminal of the transistor T2 is coupled to the first output terminal O1, and the control terminal is coupled to the first node N1. The second terminal of the transistor T3 is coupled to the second output terminal O2, and the control terminal is coupled to the first node N1.

The regulator and reset circuit 320 includes a reset unit 322, a pull-down unit 324, a regulator unit 326a, and a regulator unit 326 b. The reset unit 322 includes transistors T4-T5, and is used for resetting the voltages of the first output terminal O1 and the second output terminal O2 according to the trigger signal ST, and further resetting the voltage of the gate line coupled to the second output terminal O2. The transistor T4 has a first terminal coupled to the first output terminal O1, a second terminal for receiving the second voltage VQ, and a control terminal for receiving the trigger signal ST. The transistor T5 has a first terminal coupled to the second output terminal O2, a second terminal for receiving the third voltage VG, and a control terminal for receiving the trigger signal ST.

In the present embodiment, the first voltage VGH has a Logic High Level (Logic High Level), and the second voltage VQ and the third voltage VG have a Logic Low Level (Logic Low Level).

In one embodiment, the second voltage VQ is higher than the third voltage VG. That is, the logic low level of the second voltage VQ is higher than the logic low level of the third voltage VG.

The pull-down unit 324 is used for transferring the second voltage VQ to the first node N1 according to the shift signal (e.g., the shift signal S [ m + m ]) of the next m stages to turn off the transistor T2 and the transistor T3. The pull-down unit 324 includes a transistor T6, a first terminal of the transistor T6 is coupled to the first node N1, a second terminal of the transistor T6 is configured to receive the second voltage VQ, and a control terminal of the transistor T6 is configured to receive the shift signal of the next m stages. For example, if the shift register unit 300 is the shift register unit 210[1], the control terminal of the transistor T6 is for receiving the shift signal S [1+ m ]. For another example, if the shift register unit 300 is the shift register unit 210[2], the control terminal of the transistor T6 is used for receiving the shift signal S [2+ m ]. Similarly, if the shift register unit 300 is the shift register unit 210[ m ], the control terminal of the transistor T6 is for receiving the shift signal S [ m + m ].

The voltage stabilizing unit 326a includes transistors T7-T15 for periodically transmitting the second voltage VQ to the first output terminal O1 and the first node N1 according to the low frequency clock signal LC1, and periodically transmitting the third voltage VG to the second output terminal O2. The transistor T7 has a first terminal coupled to the first output terminal O1 and a second terminal for receiving the second voltage VG. The transistor T8 has a first terminal coupled to the second output terminal O2, and a second terminal for receiving the third voltage VG. The transistor T9 has a first terminal coupled to the first node N1 and a second terminal for receiving the second voltage VQ. The control terminals of the transistors T7-T9 are all coupled to the second node N2.

The transistor T10 has a first terminal for receiving the low frequency clock signal LC1, a second terminal coupled to the second node N2, and a control terminal coupled to the third node N3. The transistor T11 has a first terminal coupled to the second node N2, and a control terminal coupled to a first node (e.g., the first node N1[ m-2]) of the shift register unit of the previous stage 2. The first terminal of the transistor T12 is coupled to the third node N3, and the control terminal is coupled to the first node of the shift register unit of the previous stage 2. The transistor T13 has a first terminal coupled to the second node N2 and a control terminal coupled to the first node N1. The transistor T14 has a first terminal coupled to the third node N3 and a control terminal coupled to the first node N1. The second terminals of the transistors T11-T14 are all used for receiving the second voltage VQ. The transistor T15 has a first terminal and a control terminal for receiving the low frequency clock signal LC1, and a second terminal coupled to the third node N3. When the low-frequency clock signal LC1 has a logic high level, the transistors T7-T10 and T15 are turned on, thereby stabilizing the voltages at the first node N1, the first output terminal O1 and the second output terminal O2.

The voltage regulator unit 326b is similar to the voltage regulator unit 326a, except that the first terminal of the transistor T10 and the first and control terminals of the transistor T15 of the voltage regulator unit 326b are for receiving the low frequency clock signal LC 2. The low frequency clock pulse signals LC1 and LC2 are opposite signals to each other. That is, when the low frequency clock signal LC1 has a logic high level, the low frequency clock signal LC2 has a logic low level, and when the low frequency clock signal LC1 has a logic low level, the low frequency clock signal LC2 has a logic high level.

In the present embodiment, the high frequency clock pulse signals HC 1-HCm, the low frequency clock pulse signal LC1, the low frequency clock pulse signal LC2, the trigger signal ST, the first voltage VGH, the second voltage VQ, and the third voltage VG may be provided by the control circuit 110 of fig. 1.

In a certain embodiment, one period of the low frequency clock pulse signals LC1 and LC2 contains tens to hundreds of frame times (frame times). Therefore, by alternately using the two sets of

voltage regulators

326a and 326b, the aging of the components of the

voltage regulators

326a and 326b can be reduced.

FIG. 4 is a simplified functional block diagram of a shift register unit 400 according to an embodiment of the present invention. Shift register cell 400 can be used to implement shift register cells 210[ m +1] 210[ n ] of FIG. 2. for illustrative purposes, FIG. 4 shows the nth stage of shift register cell (e.g., shift register cell 210[ n ]). The shift register unit 400 is similar to the shift register unit 300, except that the reset unit 322 of the shift register unit 400 further includes a transistor T16, and the control terminal of the transistor T1 of the shift register unit 400 is used for receiving the shift signal (e.g., the shift signal [ n-m ]) of the previous m stages. The transistor T16 has a first terminal coupled to the first node N1, a second terminal for receiving the second voltage VQ, and a control terminal for receiving the trigger signal ST.

Fig. 5 is a simplified functional block diagram of the control circuit 110 of fig. 1. The control circuit 110 includes a timing control circuit 112, a level shifter (level shifter)114, a power unit 116, a diode 118, and a capacitance CS. The timing control circuit 112 is used for providing a data driving control signal DDS to the source driver 120 of fig. 1. The timing control circuit 112 is also used to provide a power input PW1 and a clock pulse control signal CIP to the level shifter 114.

The level shifter 114 generates signals required for the operation of the shift register 200 of FIG. 2 according to the power input PW1 and the clock control signal CIP. For example, the level shifter 114 may shift the voltage of the power input PW1, and then output the first voltage VGH, the second voltage VQ, and the third voltage VG to the shift register 200 at different potentials. For another example, the level shifter 114 is also used for shifting the voltage of one or more clock signals in the clock control signal CIP, and further outputs the high frequency clock signals HC 1-HCm, the low frequency clock signals LC1 and LC2, and the trigger signal ST to the shift register 200.

The power unit 116 is coupled to the level shifter 114 through a diode 118, and the capacitor CS is coupled to a fourth node N4 between the level shifter 114 and the diode 118. The power unit 116 is used to provide a power input PW2 through diode 118 to the fourth node N4. When the display device 100 is in the power-off event, the level shifter 114 switches to maintain at least a portion of the output signals at a logic high level by the voltage of the fourth node N4, thereby draining the charges on the gate lines GL1 GLn and the charges on the internal nodes of the shift register 200. Therefore, the aging of the internal components of the display device 100 due to long-time bias voltage can be avoided, and the display device 100 can be prevented from being actuated by mistake when being restarted. The aforementioned power-off event includes a user pressing a power-off button, a user removing a power plug, and power supply due to component failure.

In practice, the level shifter 114 may include one or more amplifiers and one or more switching circuits to implement the comparison and switching operations.

In one embodiment, the timing control circuit 112, the level shifter 114, the power unit 116, the diode 118, and the capacitor CS may be fabricated on the same glass substrate, and may be fabricated on the same chip or different chips. In another embodiment, the power unit 116, the diode 118, and/or the capacitor CS are fabricated on an additional flexible printed circuit board, and the timing control circuit 112 and the level shifter 114 are fabricated on a glass substrate.

Fig. 6 is a flow chart of a driving method 600 according to an embodiment of the invention. The driving method 600 is applied to the display device 100 to realize the operation of the control circuit 110. In step S602, the level shifter 114 determines whether the voltage of the power input PW1 rises above a first predetermined voltage (e.g., 2.2V). If not, the display device 100 proceeds to step S604 to maintain the first voltage VGH, the second voltage VQ, the third voltage VG, the high frequency clock signals HC 1-HCm, the low frequency clock signals LC1 and LC2, and the trigger signal ST at a logic low level. If so, it means that the user may press the power-on button of the display device 100, and the display device 100 proceeds to step S606. In step S604 of an embodiment, the trigger signal ST is switched to a logic high level and maintained at the logic high level for a predetermined time period, and then switched back to the logic low level to reset the voltages of the internal nodes of the shift register 200, such as the voltages of the first node N1, the first output terminal O1, and the second output terminal O2 of the

shift register units

300 and 400, and further reset the voltages of the gate lines GL 1-GLn.

Fig. 7 is a waveform diagram illustrating a display operation of the display device 100. The step S606 will be further described with reference to FIGS. 2-7. In step S606, the display device 100 resets the voltages of the plurality of internal nodes of the shift register 200, such as the voltages of the first node N1, the first output terminal O1, and the second output terminal O2 of the

shift register units

300 and 400, and further resets the voltages of the gate lines GL 1-GLn. When the voltage of the power input PW1 rises to be higher than the first predetermined voltage, the control circuit 110 switches the trigger signal ST from the logic low level to the logic high level in the time period E1. In addition, the control circuit 110 maintains the first voltage VGH, the second voltage VQ, the third voltage VG, the high-frequency clock signals HC 1-HCm, and the low-frequency clock signals LC1 and LC2 at the logic low level in the period E1 until the trigger signal ST is switched from the logic high level to the logic low level.

Therefore, in the period E1, the transistors T1, T4, and T5 of the shift register units 210[1] -210 [ m ] of FIG. 2 are turned on, and the transistors T4, T5, and T16 of the shift register units 210[ m +1] -210 [ N ] are turned on, so as to reset the voltages of the first node N1, the first output terminal O1, and the second output terminal O2 of the shift register units 210[1] -210 [ N ] to a logic low level.

Then, the display device 100 executes step S608 to periodically switch the trigger signal ST, the high frequency clock signals HC 1-HCm, the low frequency clock signals LC1 and LC2, and the first voltage VGH between the logic high level and the logic low level in the period E2. Therefore, the shift register units 210[1] 210[ n ] sequentially output the gate signals G [1] G [ n ] and the shift signals S [1] S [ n ] to update the display screen of the display device 100.

Fig. 8 is a waveform diagram of a portion of signals input to the shift register 200 in one frame time. The step S608 will be further described with reference to fig. 2-5 and fig. 8, and fig. 8 only shows one high frequency clock signal HCm for the convenience of description. As shown in FIG. 8, one frame time includes periods F1 and F2, and the display device 100 updates the display during period F1 and maintains the same display during period F2. In the period F1, the control circuit 110 maintains the first voltage VGH at a logic high level and periodically switches the high frequency clock signals HC 1-HCm between a logic high level and a logic low level. In addition, the control circuit 110 provides a pulse P1 with a logic high level by using the trigger signal ST.

Therefore, when the trigger signal ST has a logic high level, the transistors T1 of the shift register units 210[1] to 210[ m ] are turned on to set the voltage of the first node N1 to a logic high level. Then, when the high frequency clock pulse signals HC 1-HCm have logic high level, the transistors T2 and T3 of the shift register cells 210[1] to 210[ m ] are turned on, and the high frequency clock pulse signals HC 1-HCm are outputted as the gate signals G [1] to G [ m ] and as the shift signals S [1] to S [ m ].

In the period F2, the control circuit 100 maintains the first voltage VGH and the high frequency clock signals HC 1-HCm at logic low level. The control circuit 100 also provides a pulse P2 having a logic high potential using the trigger signal ST.

Therefore, the transistors T1, T4, and T5 of the shift register units 210[1] -210 [ m ] are turned on, and the transistors T4, T5, and T16 of the shift register units 210[ m +1] -210 [ N ] are turned on, so that the first node N1, the first output O1, and the second output O2 of the shift register units 210[1] -210 [ N ] are all set to a logic low level.

As can be seen from the above description, when the display device 100 is going to perform a display operation (e.g., the period E1 in FIG. 7), the display device 100 resets the voltage at the internal node to turn off the transistors T11-T14 of the

voltage regulator units

326a and 326 b. Therefore, when the low frequency clock signals LC1 and LC2 start to change periodically, the transistors T11 to T14 are not erroneously turned on, and short-circuit current between the low frequency clock signals LC1 and LC2 and the second voltage VQ can be prevented.

In addition, when the shift register 200 completes the updating of one frame and the shift register operation is temporarily not needed (e.g., the period F2 in fig. 8), the display apparatus 100 sets the internal node of the shift register 200 to the logic low level, thereby preventing the internal components of the shift register 200 from aging due to long-time bias.

Fig. 9 is a flow chart of a driving method 900 according to an embodiment of the invention. Fig. 10 and 11 are waveforms illustrating the situation that the display device 100 is exposed to different kinds of power-off events. The driving method 900 is similar to the driving method 600, except that the driving method 900 further includes steps S914 to S916 to prevent the redundant charges from remaining in the shift register 200 after the aforementioned power-down event. In step S910, the level shifter 114 determines whether the power input PW1 falls below the first predetermined voltage (e.g., 2.2V). If not, the display device 100 performs the step S608 again. If so, indicating that the display device 100 may face a power-off event, the level shifter 114 switches to supply power from the capacitor CS, and the display device 100 then performs step S912.

In step S912, the level shifter 114 further determines whether the power input PW1 falls below a second predetermined voltage (e.g., 1V). If not, it means that the display apparatus 100 may still obtain stable power supply when the external power is not removed in the power-off event (e.g., the power-off button is triggered but the plug is not unplugged), and therefore the display apparatus 100 then performs step S914. If so, it represents that the display apparatus 100 may face the event type of the power failure event in which the external power source is removed or the components are severely failed, and thus the stable power supply cannot be obtained, so the display apparatus 100 then performs step S916.

As shown in fig. 10, in step S914, the control circuit 110 switches the high frequency clock pulse signals HC 1-HCm, the trigger signal ST, the first voltage VGH, the second voltage VQ, the third voltage VG, and the low frequency clock pulse signals LC1 and LC2 to the logic high level (period E3). In addition, the trigger signal ST is maintained at a logic high level until the control circuit 110 switches the high frequency clock signals HC 1-HCm, the first voltage VGH, the second voltage VQ, the third voltage VG, and the low frequency clock signals LC1 and LC2 to a logic low level, and then the control circuit 110 switches the trigger signal ST to a logic low level (time period E4).

In time period E3, the transistors T1T 15 of the shift register cells 210[1] 210[ m ] are turned on, and the transistors T1T 16 of the shift register cells 210[ m +1] 210[ n ] are turned on. Therefore, the gate signals G [1] G [ n ] all have logic high level to drain the internal charge of the pixel 140.

In period E4, the transistors T4 and T5 of the shift register cells 210[1] -210 [ m ] are turned on, and the transistors T4, T5 and T16 of the shift register cells 210[ m +1] -210 [ n ] are turned on. Therefore, the voltages at the first node N1, the first output terminal O1, and the second output terminal O2 of the shift register cells 210[1] to 210[ N ] are set to logic low levels to drain the gate line charge and the charge at the internal node of the shift register 200.

In the period E4 of an embodiment, the first voltage VGH and the high frequency clock pulse signals HC 1-HCm are switched to the logic low level after the second voltage VQ, the third voltage VG, and the low frequency clock pulse signals LC1 and LC2 are switched to the logic low level. Accordingly, the charges of the second node N2 and the third node N3 of the

voltage stabilizing units

326a and 326b are also drained.

As shown in fig. 11, in step S916, the control circuit 110 at least switches the third voltage VG, the trigger signal ST, and the high-frequency clock signals HC 1-HCm to the logic high level (period E5). In addition, the trigger signal ST is maintained at the logic high level until the control circuit 110 switches the high-frequency clock signals HC 1-HCm and the third voltage VG to the logic low level, and then the control circuit 110 switches the trigger signal ST to the logic low level (time period E6).

In time period E5, at least transistors T1T 5 of the shift register cells 210[1] 210[ m ] are turned on, and at least transistors T1T 5 and T16 of the shift register cells 210[ m +1] 210[ n ] are turned on. Therefore, the gate signals G [1] G [ n ] all have logic high level to drain the internal charge of the pixel 140.

The operation of the register units 210[1] to 210[ n ] in the time periods E6 and F4 is similar, and for brevity, the description is not repeated here.

As can be seen from the above, when the display device 100 encounters different kinds of power-off events, the display device 100 can drain the residual charges inside the panel, thereby preventing the internal components from aging due to long-term bias.

The execution sequence of the processes in the above flowcharts is only an exemplary embodiment, and is not limited to the actual implementation of the present invention. For example, in each of the flowcharts described above, step S710 may be performed in parallel with steps S602 to S608.

In some embodiments, the transistors in the

shift register cells

300 and 400 are low temperature polysilicon transistors, or other transistors that are less susceptible to aging. Therefore, the

shift register units

300 and 400 may include only one of the

voltage stabilizing units

326a and 326b, i.e. the shift register 200 may perform the voltage stabilizing operation according to only one low frequency clock signal. In this case, when the display device 100 including the shift register 200 performs the aforementioned driving methods 600 and 900, only the voltage potential of the corresponding one of the low frequency clock pulse signals may be adjusted.

Certain terms are used throughout the description and following claims to refer to particular components. However, those of ordinary skill in the art will appreciate that the various elements may be referred to by different names. The description and claims do not intend to distinguish between components that differ in name but not function. In the description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Further, "coupled" herein includes any direct and indirect connection. Therefore, if a first element is coupled to a second element, the first element may be directly connected to the second element through an electrical connection or a signal connection such as wireless transmission or optical transmission, or may be indirectly connected to the second element through another element or a connection means.

As used herein, the description of "and/or" includes any combination of one or more of the items listed. In addition, any reference to singular is intended to include the plural unless the specification specifically states otherwise.

The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A shift register, comprising:

n stages of shift register units, where n is a positive integer, each of the n stages of shift register units includes:

an output circuit, including a first node, a first output terminal, and a second output terminal, for transmitting a first voltage to the first node, and for outputting a corresponding one of m high frequency clock pulse signals at the first output terminal and the second output terminal according to the voltage of the first node, where m is a positive integer;

a voltage stabilizing and resetting circuit for transmitting a second voltage to the first node according to a low frequency clock signal, and transmitting the second voltage and a third voltage to the first output terminal and the second output terminal respectively according to a trigger signal;

the shift register is coupled to a control circuit, when the control circuit determines that a power input rises above a first preset voltage, the trigger signal is switched to a logic high potential, and the m high-frequency clock pulse signals, the low-frequency clock pulse signal, the first voltage, the second voltage and the third voltage are maintained at a logic low potential until the trigger signal is switched from the logic high potential to the logic low potential, so as to reset the voltage of the first node;

when the control circuit determines that the power input is reduced to be lower than the first preset voltage, the m high-frequency clock pulse signals, the trigger signal and the third voltage are switched to the logic high potential, and the trigger signal is switched to the logic low potential until the m high-frequency clock pulse signals and the third voltage are switched to a logic low potential from the logic high potential.

2. The shift register as claimed in claim 1, wherein the output circuit of each of the 1 st to m th shift register cells of the n-th shift register cells is configured to transmit the first voltage to the first node according to the trigger signal.

3. The shift register of claim 2, wherein the n-stage shift register units are configured to output a plurality of shift signals, and the output circuit of each shift register unit outputs a corresponding one of the plurality of shift signals through the first output terminal,

the output circuits of the m +1 th to n th shift register units in the n-stage shift register unit are respectively used for transmitting the first voltage to the respective first nodes according to the corresponding one of the shift signals.

4. The shift register of claim 1, wherein the reset circuit of each of the n-stage shift register units comprises:

a first transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first transistor is coupled to the first output terminal, the second terminal of the first transistor is configured to receive the second voltage, and the control terminal of the first transistor is configured to receive the trigger signal; and

a second transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second transistor is coupled to the second output terminal, the second terminal of the second transistor is configured to receive the third voltage, and the control terminal of the second transistor is configured to receive the trigger signal.

5. The shift register as claimed in claim 4, wherein the reset circuit of each of the m +1 th through n-th stages of the n stages of shift register units further comprises a third transistor, the third transistor comprises a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor is coupled to the first node, the second terminal of the third transistor is for receiving the second voltage, and the control terminal of the third transistor is for receiving the trigger signal.

6. A driving method is applicable to a display device, the display device comprises a shift register and a control circuit, the control circuit is used for providing a trigger signal, a first voltage, a second voltage, a third voltage, m high-frequency clock pulse signals and a low-frequency clock pulse signal to the shift register, and the driving method comprises the following steps:

when the control circuit judges that a power input is higher than a first preset voltage, the control circuit switches the trigger signal to a logic high potential, and maintains the first voltage, the second voltage, the third voltage, the m high-frequency clock pulse signals and the low-frequency clock pulse signal at a logic low potential until the trigger signal is switched from the logic high potential to the logic low potential so as to reset the voltages of a plurality of internal nodes of the shift register; and

the control circuit is used for periodically switching the trigger signal, the m high-frequency clock pulse signals, the low-frequency clock pulse signals and the first voltage between the logic high potential and the logic low potential so as to update a display picture of the display device;

when the control circuit judges that a power input is lower than the first preset voltage, the control circuit switches the m high-frequency clock pulse signals, the trigger signal and the third voltage to the logic high potential, wherein the trigger signal is switched to the logic low potential until the m high-frequency clock pulse signals and the third voltage are switched from the logic high potential to the logic low potential.

7. The driving method as claimed in claim 6, wherein the step of the control circuit switching the m high frequency clock signals, the trigger signal, and the third voltage to the logic high level comprises:

if the power input is lower than the first preset voltage and higher than a second preset voltage, the control circuit switches the m high-frequency clock pulse signals, the trigger signal, the first voltage, the second voltage, the third voltage and the low-frequency clock pulse signal to the logic high potential, wherein the trigger signal is switched to the logic low potential until the m high-frequency clock pulse signals, the first voltage, the second voltage, the third voltage and the low-frequency clock pulse signal are switched to the logic low potential; and

if the power input is lower than the second preset voltage, the control circuit switches the m high-frequency clock pulse signals, the trigger signal and the third voltage to the logic high potential, wherein the trigger signal is switched to the logic low potential until the m high-frequency clock pulse signals and the third voltage are switched from the logic high potential to the logic low potential.

8. The method of claim 6, wherein the step of periodically switching the trigger signal, the m high frequency clock signals, and the low frequency clock signal between the logic high voltage level and the logic low voltage level by the control circuit comprises:

in a frame, when the first voltage has the logic high potential, the trigger signal is utilized to provide a first pulse so that the shift register sequentially outputs a plurality of grid signals; and

in the frame, when the first voltage has the logic low level, a second pulse is provided by the trigger signal to reset the shift register.

9. A display device, comprising:

a control circuit;

a shift register for the control circuit to receive a trigger signal, a first voltage, a second voltage, a third voltage, m high frequency clock pulse signals, and a low frequency clock pulse signal, and comprising n stages of shift register units, wherein n is a positive integer, and each of the n stages of shift register units comprises:

an output circuit, including a first node, a first output terminal, and a second output terminal, for transmitting a first voltage to the first node, and for outputting a corresponding one of the m high frequency clock pulse signals at the first output terminal and the second output terminal according to the voltage of the first node, wherein m is a positive integer;