CN110827780B - Gate driving unit, gate scanning driving circuit and liquid crystal display device - Google Patents
Gate driving unit, gate scanning driving circuit and liquid crystal display device Download PDFInfo
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- CN110827780B CN110827780B CN201911164187.8A CN201911164187A CN110827780B CN 110827780 B CN110827780 B CN 110827780B CN 201911164187 A CN201911164187 A CN 201911164187A CN 110827780 B CN110827780 B CN 110827780B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
Abstract
The embodiment of the invention provides a grid driving unit, a grid scanning driving circuit and a liquid crystal display device, wherein the grid driving unit comprises a pull-up input module, a pull-up module, a pull-down module, a first single-pole maintenance control module and a first maintenance module; the first single-pole maintaining control module is used for receiving a first low-frequency clock signal and setting the input end of the first maintaining signal to be at a first level when the first low-frequency clock signal is at the first level; and the first maintaining module is used for enabling the pull-up control node after being pulled down to a second level by the pull-down module, and conducting the pull-up control node and the driving signal output end with the second level input end when the first maintaining signal input end of the first maintaining module is at a first level. According to the embodiment of the invention, the maintaining control module is set as the unipolar control module, so that the use of a high-voltage signal line VGH and a zero clearing module can be omitted, the circuit is simplified, and the cost is reduced.
Description
Technical Field
The embodiment of the invention relates to the technical field of liquid crystal display, in particular to a gate driving unit, a gate scanning driving circuit and a liquid crystal display device.
Background
With the development of liquid crystal display technology, consumers have an increasing demand for narrow-frame screens, and in order to narrow a frame, an external Gate scanning driving circuit can be manufactured On an Array substrate by using a Gate On Array (GOA) technology, so that spaces of a Gate driving chip and a circuit board are saved.
In the conventional GOA technology, as shown in fig. 1, a circuit structure of 21T1C (21 tfts and 1 capacitor) is usually adopted to generate the gate driving signal.
However, the gate scan driving circuit adopts the high-level signal routing VGH to realize the input and maintenance of the signal, and the zero clearing modules (M2, M4 and M12) are arranged for matching with the use of the VGH to clear, which shows that the gate scan driving circuit has many devices, and the cost is high due to the large number of routing, the risk of device failure is large, and the line failure is easy to cause.
Disclosure of Invention
The embodiment of the invention provides a gate driving unit, a gate scanning driving circuit and a liquid crystal display device, which are used for simplifying a circuit structure, reducing the number of routing wires and reducing the cost, and therefore the problems of high cost, high device failure risk and easiness in causing poor circuit caused by the adoption of a high-voltage line VGH in the prior art are solved.
In a first aspect, an embodiment of the present invention provides a gate driving unit, including: the device comprises a pull-up input module, a pull-up module, a pull-down module, a first single-pole maintenance control module and a first maintenance module;
the pull-up input module is connected with the drive signal input end and the pull-up control node, and is used for receiving a superior drive signal and setting the pull-up control node to be a first level when the superior drive signal is at the first level;
the pull-up module is connected with the pull-up control node, the clock signal input end and the driving signal output end and is used for conducting the clock signal input end and the driving signal output end when the pull-up control node is at a first level;
the pull-down module is connected with the pull-up control node, the drive signal output end, the lower drive signal input end and the second level input end, and is used for receiving a lower drive signal and conducting the pull-up control node and the drive signal output end with the second level input end when the lower drive signal is at a first level;
the first single-pole maintaining control module is connected with a first maintaining signal input end and a first low-frequency clock signal input end of the first maintaining module, and is used for receiving a first low-frequency clock signal and setting the first maintaining signal input end to be at a first level when the first low-frequency clock signal is at the first level;
the first maintenance module is connected to the pull-up control node, the driving signal output end and the second level input end, and configured to enable the pull-up control node after being pulled down to the second level by the pull-down module, and conduct both the pull-up control node and the driving signal output end with the second level input end when the first maintenance signal input end of the first maintenance module is at the first level.
In one possible design, the first unipolar sustain control module includes: a third transistor and a fifth transistor;
the grid electrode and the source electrode of the third transistor are both connected with the first low-frequency clock signal input end, and the drain electrode of the third transistor is connected with the grid electrode of the fifth transistor;
and the source electrode of the fifth transistor is connected with the first low-frequency clock signal input end, and the drain electrode of the fifth transistor is connected with the first maintenance signal input end of the first maintenance module.
In one possible design, the first maintenance module includes: a sixth transistor, a seventh transistor, and an eighth transistor;
a grid electrode of the sixth transistor is connected with the pull-up control node, a source electrode of the sixth transistor is connected with a first maintenance signal input end of the first maintenance module, and a drain electrode of the sixth transistor is connected with the second level input end;
a gate of the seventh transistor is connected to the first unipolar sustain control module, a source of the seventh transistor is connected to the pull-up control node, and a drain of the seventh transistor is connected to the second level input terminal;
and the grid electrode of the eighth transistor is connected with the first unipolar maintaining control module, the source electrode of the eighth transistor is connected with the driving signal output end, and the drain electrode of the eighth transistor is connected with the second level input end.
In one possible design, in the first unipolar sustain control module, a drain of a third transistor is connected to a second sustain signal input terminal of the first sustain module; the first maintenance module further comprises: a ninth transistor;
the gate of the ninth transistor is connected to the pull-up control node, the source of the ninth transistor is connected to the second sustain signal input terminal of the first sustain module, and the drain of the ninth transistor is connected to the second level input terminal.
In one possible design, the pull-down module includes: a second transistor;
and the grid electrode of the second transistor is connected with the lower-level driving signal input end, the source electrode of the second transistor is connected with the pull-up control node, and the drain electrode of the second transistor is connected with the second level input end.
In one possible design, the pull-down module further includes: a fourth transistor;
and the grid electrode of the fourth transistor is connected with the lower-level driving signal input end, the source electrode of the fourth transistor is connected with the driving signal output end, and the drain electrode of the fourth transistor is connected with the second level input end.
In one possible design, the pull-up input module includes: a first transistor;
and the grid electrode and the source electrode of the first transistor are both connected with the driving signal input end, and the drain electrode of the first transistor is connected with the pull-up control node.
In one possible design, the cell further includes: the second unipolar maintenance control module is the same in structure as the first unipolar maintenance control module, and the second maintenance module is arranged symmetrically to the first maintenance module;
the second single-pole maintaining control module is connected with a first maintaining signal input end and a second low-frequency clock signal input end of the second maintaining module, and is used for receiving a second low-frequency clock signal and setting the first maintaining signal input end to be at a first level when the second low-frequency clock signal is at the first level;
the second maintenance module is connected to the pull-up control node, the driving signal output end and the second level input end, and configured to enable the pull-up control node after being pulled down to a second level by the pull-down module, and connect both the pull-up control node and the driving signal output end to the second level input end when the first maintenance signal input end is at a first level;
wherein the first low frequency clock signal and the second low frequency clock signal are opposite clock signals.
In one possible design, the pull-up module includes: a tenth transistor and a first capacitor;
and the grid electrode of the tenth transistor is connected with the pull-up control node, the source electrode of the tenth transistor is connected with the clock signal input end, and the drain electrode of the tenth transistor is connected with the driving signal output end.
One end of the first capacitor is connected with the pull-up control node, and the other end of the first capacitor is connected with the driving signal output end.
In a second aspect, an embodiment of the present invention provides a gate scan driving circuit, including: a plurality of cascaded gate drive units; the gate driving unit is the gate driving unit according to the first aspect and various possible designs of the first aspect.
In a third aspect, an embodiment of the present invention provides a liquid crystal display device, including: the liquid crystal display device comprises a liquid crystal display substrate, a source electrode driving circuit arranged on the liquid crystal display substrate and a grid electrode scanning driving circuit designed according to the first aspect and the first aspects.
According to the gate driving unit, the gate scanning driving circuit and the liquid crystal display device provided by the embodiment, the gate driving unit directly controls the maintenance module to work through the LC signal by setting the maintenance control module as the unipolar control module, so that the use of a high-voltage signal line VGH and the use of a zero clearing module are omitted, the circuit can be simplified, the wiring is reduced, and the cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a circuit diagram of a gate driving unit in the prior art;
fig. 2 is a circuit diagram of a gate driving unit according to an embodiment of the invention;
fig. 3 is a circuit diagram of a gate driving unit according to another embodiment of the invention;
fig. 4 is a circuit diagram of a gate driving unit according to another embodiment of the invention;
fig. 5 is a circuit diagram of a gate driving unit according to another embodiment of the invention;
fig. 6 is a schematic structural diagram of a gate scan driving circuit according to an embodiment of the present invention;
fig. 7 is a schematic diagram of driving signals of a gate scan driving circuit according to another embodiment of the invention;
fig. 8 is a schematic structural diagram of a liquid crystal display device according to still another embodiment of the invention.
Reference numerals:
11: a pull-up input module; 12: a pull-up module; 20: a pull-down module; 31: a first unipolar sustain control module; 32: a first maintenance module; 33: a second unipolar sustain control module; 34: a second maintenance module; m1: a first transistor; m2: a second transistor; m3: a third transistor; m4: a fourth transistor; m5: a fifth transistor; m6: a sixth transistor; m7: a seventh transistor; m8: an eighth transistor; m9: a ninth transistor; m10: a tenth transistor; m3': a thirteenth transistor; m5': a fifteenth transistor; m6': a sixteenth transistor; m7': a seventeenth transistor; m8': an eighteenth transistor; m9': a nineteenth transistor; PU (polyurethane): a pull-up control node; LC 1: a first low frequency clock signal; LC 2: a second low frequency clock signal; gn-b: a drive signal input; gn: a drive signal output terminal; gn + m: a lower drive signal input; VSS: a second level.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a circuit diagram of a gate driving unit in the prior art. As shown in fig. 1, the gate driving unit employs a circuit of 21T1C (21 tfts and 1 capacitor). It includes: pull-up subunits (M1 and M10), pull-down subunits (M9), sustain subunits (M3A, M5A, M6A, M7A, M8A, M13A, M14A, M3B, M5B, M6B, M7B, M8B, M13B, and M14B), clear subunits (M2 and M12), and rank pass subunits (M11, M4, M14A, and M14B).
In a specific working process, when an upper-level driving signal input by a driving signal input end is in a high level, M1 in the pull-up subunit is conducted, a gate high voltage VGH charges a QA node, M10 in the pull-up subunit is conducted when the QA node is in the high level, a clock signal CKm is output as a current-level driving signal Gn, M11 in the current-level transmission subunit is conducted, a clock signal CKm is output as a current-level transmission signal Tn, M6A, M6B, M7A and M7B in the subunit are maintained to be conducted, and the subunit is not enabled; when the lower level driving signal is high level, M9 in the pull-down subunit is turned on, the QA node is turned on with the VSS input terminal, the VSS input terminal inputs low level voltage, the level of the QA node is pulled low, M10 is turned off, the output of the present level driving signal Gn is ended, and at the same time, M6A and M6B in the holding subunit are turned off; when the upper-level driving signal input by the driving signal input terminal is at a low level, M7A and M7B are turned off, if LC1 is at a high level, M5A is turned on, and M13A, M8A and M14A are turned on under the action of VGH (correspondingly, if LC2 is at a high level, M5B is turned on, and M13B, M8B and M14B are turned on under the action of VGH), and the QA node and the QB node are pulled low. Before the next frame is started after one frame is finished, when the clear signal CLR is in a high level, M2, M4 and M12 are started to respectively discharge the QA node, the QD node and the QB node, so that the clear function is realized.
Therefore, the conventional gate driving unit with the 21T1C structure has many devices and a large risk of causing poor devices, and the driving unit also adopts two high-level signal routing lines VGH to respectively act on the pull-up subunit and the maintaining subunit, so that the problem of poor burn caused by heat generation due to high concentration of high level signals is easily caused, and a special zero clearing module is required to clear due to the addition of the VGH, so that the occupied area of the device is increased.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Fig. 2 is a circuit diagram of a gate driving unit according to an embodiment of the invention. As shown in fig. 2, the gate driving unit includes: a pull-up input module 11, a pull-up module 12, a pull-down module 20, a first unipolar sustain control module 31, and a first sustain module 32.
And the pull-up input module 11 is connected to the driving signal input terminal Gn-b and the pull-up control node PU, and configured to receive a higher-level driving signal and set the pull-up control node PU to a first level when the higher-level driving signal is at the first level.
And the pull-up module 12 is connected to the pull-up control node PU, the clock signal input terminal CKm and the driving signal output terminal Gn, and configured to connect the clock signal input terminal CKm to the driving signal output terminal when the pull-up control node PU is at the first level.
And the pull-down module 20 is connected to the pull-up control node PU, the driving signal output terminal Gn, the lower driving signal input terminal Gn + m, and the second level input terminal VSS, and configured to receive the lower driving signal, and when the lower driving signal is at the first level, respectively connect the pull-up control node PU and the driving signal output terminal Gn to the second level input terminal VSS.
The first unipolar sustain control module 31 is connected to the first sustain signal input terminal of the first sustain module 32 and the first low frequency clock signal input terminal LC1, and is configured to receive the first low frequency clock signal LC1 and set the first sustain signal input terminal to the first level when the first low frequency clock signal LC1 is at the first level.
The first maintaining module 32 is connected to the pull-up control node PU, the driving signal output terminal Gn, the second level input terminal VSS and the first single-pole maintaining control module 31, and configured to enable the pull-up control node PU after being pulled down to the second level by the pull-down module 20, and conduct both the pull-up control node PU and the driving signal output terminal Gn to the second level input terminal VSS when the first maintaining signal input terminal of the first maintaining module 32 is at the first level.
In practical application, the upper driving signal received by the pull-up control module may be an upper scanning signal Gn-bOr a superior level transmission signal Tn-b. This embodiment is not to this endThe limitation is made based on the actual circuit requirement.
The pull-up module 12 is configured to generate a current-stage driving signal, output the current-stage driving signal to a current-stage scanning signal line, and further output the current-stage driving signal to a pixel display area for driving a scanning line.
Optionally, in this embodiment, the second level is a low level, and the first level is a high level.
The first unipolar sustain control block 31 is a unidirectional control block, and may be formed of one transistor or a plurality of transistors. The present embodiment is not limited to this embodiment, particularly based on the actual circuit requirement. Specifically, after the pull-down module 20 pulls down the pull-up control node PU, the first maintenance module 32 is enabled, the first single-pole maintenance control module 31 generates a maintenance signal according to the first low-frequency clock signal LC1, and inputs the maintenance signal into the first input end of the first maintenance module 32, so that the first maintenance module 32 maintains the pull-up control node PU and the driving signal output terminal Gn at the second level, so as to avoid the driving signal output terminal Gn from being interfered by abnormal signals, and improve the reliability of the gate driving unit.
According to the gate driving unit provided by the embodiment, the maintaining control module is set to be the unipolar control module, and the operation of the maintaining module is directly controlled by the LC signal, so that the use of a high-voltage signal line VGH and a zero clearing module are omitted, the circuit can be simplified, the wiring is reduced, and the cost is reduced.
Fig. 3 is a circuit diagram of a gate driving unit according to another embodiment of the invention. In addition to the above embodiments, the present embodiment describes the specific structure of the first unipolar sustain control module 31 and the first sustain module 32 in detail, and as shown in fig. 3, the first unipolar sustain control module 31 includes: a third transistor M3 and a fifth transistor M5; the gate and the source of the third transistor M3 are both connected to the input end of the first low-frequency clock signal LC1, and the drain is connected to the gate of the fifth transistor M5; the source of the fifth transistor M5 is connected to the input terminal of the first low frequency clock signal LC1, and the drain is connected to the first sustain signal input terminal of the first sustain module 32. The first unipolar sustain control module 31 employs the dual device unipolar control devices (M3 and M5), so that the risk of failure of the control devices can be prevented, and it can be prevented that when the LC1 is at a low level (when the pull-down module 20 inputs a high level), a reverse relatively high level backtracking of the first unipolar sustain control module 31 is formed to cause a parasitic charge (parasitic capacitance) of the first unipolar sustain control module 31, and then the first unipolar sustain control module is turned on (with respect to the VSS signal) when the driving signal output terminal Gn outputs a high level, so that the output of Gn is pulled down.
The first maintenance module 32 includes: a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8.
The sixth transistor M6 has a gate connected to the pull-up control node PU, a source connected to the first unipolar sustain control module 31, and a drain connected to the second level input terminal VSS, for enabling the first sustain module 32 after the pull-up control node PU is pulled down by the pull-down module 20.
The seventh transistor M7 has a gate connected to the first unipolar sustain control module 31, a source connected to the pull-up control node PU, and a drain connected to the second level input terminal VSS, and is configured to maintain the pull-up control node PU at a low level when the LC1 is at a high level, so as to avoid interference from an abnormal signal, and thus the pull-up control signal operates abnormally.
The eighth transistor M8 has a gate connected to the first unipolar sustain control module 31, a source connected to the driving signal output terminal Gn, and a drain connected to the second level input terminal VSS, and is configured to maintain the driving signal output terminal Gn at a low level when the LC1 is at a high level, so as to prevent the driving signal output terminal Gn from being influenced by the interference signal and operating abnormally.
It is understood that, in the present embodiment, the first maintaining module 32 includes a seventh transistor M7 maintaining the pull-up control node PU and an eighth transistor M8 maintaining the driving signal output terminal Gn. Optionally, in other embodiments, the seventh transistor M7 or the eighth transistor M8 may be eliminated according to actual circuit requirements, so as to further simplify the circuit and reduce the occupied area.
As shown in fig. 3, optionally, the pull-down module 20 includes: a second transistor M2; the gate of the second transistor M2 is connected to the lower-level driving signal input terminal Gn + M, the source is connected to the pull-up control node PU, and the drain is connected to the second level input terminal VSS, for receiving the lower-level driving signal and pulling down the potential of the pull-up control node PU to a low level when the lower-level driving signal is at a high level.
As shown in fig. 3, optionally, the pull-down module 20 further includes: a fourth transistor M4; the fourth transistor M4 has a gate connected to the next-stage driving signal input terminal Gn + M, a source connected to the driving signal output terminal Gn, and a drain connected to the second level input terminal VSS, and is configured to pull down the potential of the driving signal output terminal Gn to a low level when the next-stage driving signal is at a high level.
As shown in fig. 3, the pull-up input module 11 optionally includes: a first transistor M1; the gate and the source of the first transistor M1 are both connected to the driving signal input terminal Gn-b, and the drain is connected to the pull-up control node PU, for receiving a higher level driving signal and pulling up the potential of the pull-up control node PU to a high level when the higher level driving signal is at a high level.
As shown in fig. 3, optionally, the pull-up module 12 includes: a tenth transistor M10; the gate of the tenth transistor M10 is connected to the pull-up control node PU, the source is connected to the clock signal input terminal CKm, and the drain is connected to the driving signal output terminal Gn, for conducting when the pull-up control node PU is at a high level, so that the clock signal CKm is output through the driving signal output terminal Gn.
As shown in fig. 3, optionally, the drawing-up module 12 further includes: a first capacitor; one end of the first capacitor is connected with the pull-up control node PU, and the other end of the first capacitor is connected with the driving signal output end Gn and used for lifting the potential of the pull-up control node PU during the output period of the driving signal.
In a specific working process, when a superior driving signal input by the driving signal input terminal Gn-b is at a high level, the first transistor M1 in the pull-up control module is turned on, the superior driving signal charges the pull-up control node PU, the tenth transistor M10 in the pull-up module 12 is turned on when the pull-up control node PU is at a high level, the clock signal CKm is output as the driving signal Gn of the current level, meanwhile, the sixth transistor M6 in the first maintenance module 32 is turned on, and the first maintenance module 32 is not enabled; when the lower-level driving signal is at a high level, the second transistor M2 and the fourth transistor M4 in the pull-down module 20 are turned on, the pull-up control node PU is turned on with the second level input terminal VSS, the level of the pull-up control node PU is pulled down, the tenth transistor M10 in the pull-up module 12 is turned off, the driving signal output terminal Gn is turned on with the second level input terminal VSS, the driving signal output terminal Gn is pulled down, the output of the present-level driving signal Gn is ended, meanwhile, the sixth transistor M6 in the first maintenance module 32 is turned off, and the first maintenance module 32 is enabled; when the upper driving signal inputted from the driving signal input terminal Gn-b is at a low level, if the LC1 is at a high level, the third transistor M3 is turned on to control the fifth transistor M5 to be turned on, the LC1 is inputted to the gate of the seventh transistor M7 to turn on the seventh transistor M7 and the eighth transistor M8, so that the pull-up control node PU and the driving signal output terminal Gn are respectively turned on to the second level input terminal VSS, and the pull-up control node PU and the driving signal output terminal Gn are maintained at a low level.
The gate driving unit provided in this embodiment can prevent the risk of failure of the control device by using the dual-device unipolar control for the first unipolar sustain control module 31, and can prevent the parasitic charges (parasitic capacitances) of the first unipolar sustain control module 31 caused by backward relatively high level backtracking of the first unipolar sustain control module 31 when the LC1 is at the low level (when the pull-down module 20 inputs the high level at this time), and then the gate driving unit is turned on (with respect to the VSS signal) when the driving signal output terminal Gn outputs the high level, so as to pull down the output of Gn. In addition, in the embodiment, the pull-down module 20 pulls down the pull-up control node PU and the driving signal output terminal Gn at the same time, so that the risk of abnormal turn-on can be reduced.
Fig. 4 is a circuit diagram of a gate driving unit according to another embodiment of the invention. On the basis of the above-mentioned embodiment, for example, on the basis of the embodiment shown in fig. 3, in this embodiment, a symmetrical circuit of the first maintenance control module and the first maintenance module 32 is added, so as to reduce the risk of failure of each device in the maintenance module, as shown in fig. 4, the gate driving unit further includes: a second unipolar sustain control module 33 symmetrical to the first unipolar sustain control module 31, and a second sustain module 34 symmetrical to the first sustain module 32.
The second unipolar sustain control module 33 is connected to the first sustain signal input terminal of the second sustain module 34 and the second low frequency clock signal LC2 input terminal, and is configured to receive the second low frequency clock signal LC2, and set the first sustain signal input terminal to the first level when the second low frequency clock signal LC2 is at the first level.
The second maintaining module 34 is connected to the pull-up control node PU, the driving signal output terminal Gn, and the second level input terminal VSS, and is configured to enable the pull-up control node PU after being pulled down to the second level by the pull-down module 20, and conduct both the pull-up control node PU and the driving signal output terminal Gn to the second level input terminal VSS when the first maintaining signal input terminal is at the first level.
Wherein the first low frequency clock signal LC1 and the second low frequency clock signal LC2 are opposite clock signals.
Optionally, the second unipolar maintenance control module 33 includes: a thirteenth transistor M3 'and a fifteenth transistor M5'. The gate and the source of the thirteenth transistor M3 'are both connected to the input terminal of the second low frequency clock signal LC2, and the drain is connected to the gate of the fifteenth transistor M5'.
The source of the fifteenth transistor M5' is connected to the input terminal of the second low-frequency clock signal LC2, and the drain is connected to the first sustain signal input terminal of the second sustain module 34.
The second maintenance module 34 includes: a sixteenth transistor M6', a seventeenth transistor M7', and an eighteenth transistor M8 '; a gate of the sixteenth transistor M6' is connected to the pull-up control node PU, a source thereof is connected to the first sustain signal input terminal of the second sustain module 34, and a drain thereof is connected to the second level input terminal VSS; a gate of the seventeenth transistor M7' is connected to the first sustain signal input terminal of the second sustain module 34, a source thereof is connected to the pull-up control node PU, and a drain thereof is connected to the second level input terminal VSS; the gate of the eighteenth transistor M8' is connected to the first sustain signal input terminal of the second sustain module 34, the source thereof is connected to the driving signal output terminal Gn, and the drain thereof is connected to the second level input terminal VSS.
It is understood that the second unipolar sustain module and the first unipolar sustain control module 31 have the same circuit structure, and the operation principle thereof can be referred to the description of the first unipolar sustain control module 31 in the above embodiments, and will not be described herein again. The second maintenance module 34 and the first maintenance module 32 also have the same circuit structure, and the working principle thereof can also refer to the description of the first maintenance module 32 in the above embodiment, which is not described herein again.
In this embodiment, by providing the first unipolar sustain control module 31 and the second unipolar sustain control module 33 which are symmetrical, and the first sustain module 32 and the second sustain module 34 which are symmetrical, the pull-up control node PU and the driving signal output terminal Gn can be maintained at low levels during the period of non-operation of Gn under the alternate action of the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2 which are opposite signals, so as to prevent the device from being biased for a long time, the semiconductor from being polarized, causing the characteristic drift of the device, the leakage current from increasing, further causing the device to fail, and increasing the reliability risk.
Fig. 5 is a circuit diagram of a gate driving unit according to another embodiment of the invention. In addition to the above-mentioned practical advantages, for example, in the embodiment shown in fig. 4, in the present embodiment, the sustain module is modified, and a ninth transistor M9 is added to the first sustain module 32, as shown in fig. 5, in the first unipolar sustain control module 31, the drain of the third transistor M3 is connected to the second sustain signal input terminal of the first sustain module 32; the first maintenance module 32 further includes: a ninth transistor M9; the gate of the ninth transistor M9 is connected to the pull-up control node PU, the source thereof is connected to the second sustain signal input terminal of the first sustain module 32, and the drain thereof is connected to the second level input terminal VSS.
Optionally, in the second unipolar sustain control module 33, a drain of a thirteenth transistor M3' is connected to the second sustain signal input terminal of the second sustain module 34; the first maintenance module 32 further includes: a nineteenth transistor M9'; the gate of the nineteenth transistor M9' is connected to the pull-up control node PU, the source is connected to the second sustain signal input terminal of the second sustain module 34, and the drain is connected to the second level input terminal VSS.
In the gate driving unit provided in this embodiment, an output terminal is added to the drain of the third transistor M3 of the first unipolar sustain control module 31, and the output terminal is connected to the ninth transistor M9 of the sustain module, so that the reliability of the first unipolar sustain control module 31 can be further improved.
Fig. 6 is a schematic structural diagram of a gate scan driving circuit according to an embodiment of the invention. As shown in fig. 6, in the present embodiment, the gate scan driving circuit uses 6 clock signals (CK1-CK6) for driving, it can be understood that, in practical applications, the number of clock signals may be determined according to the load of the panel and the driving capability of the circuit, for example, 8 clocks and 10 clocks may also be used, and in the present embodiment, 6 clocks are used to reduce the number of traces. The circuit structure mainly comprises a driving signal input part (such as CK1-CK6, LC1, LC2 and VSS in the figure), a circuit output and a stage transmission part (such as output and STV in the figure).
Fig. 7 is a schematic diagram of driving signals of a gate scan driving circuit according to another embodiment of the invention.
As shown in fig. 7:
STV is a start signal responsible for starting the circuits of the previous stage;
CK1-CK6 are driving high-frequency clock signals and are mainly responsible for generating the scanning signals (namely the stage transmission signals) of the stage;
LC1 and LC2 are first and second low frequency clock signals that are opposite in phase, and the frequency of LC1 and LC2 is lower than the high frequency clock signal, but the specific frequency needs to be determined according to the panel characteristics and TFT element characteristics;
VSS is a constant voltage low level control signal, which is a low level in this embodiment;
fig. 8 is a schematic structural diagram of a liquid crystal display device according to still another embodiment of the invention. As shown in fig. 8, the liquid crystal display device 80 includes a liquid crystal display substrate 81, a gate driver 82 and a source driver 83 connected to the liquid crystal display substrate 81, and a circuit board 84 connected to the source driver 83, the gate driver 82 is disposed inside the liquid crystal display substrate 81, the circuit board 84 is connected to both the source driver 83 and the gate driver 82, a plurality of scanning lines Gx 1011 and a plurality of data lines Sy1012 are disposed on the liquid crystal display substrate 81, the scanning lines 811 are provided with gates, the gate driver 82 is connected to the plurality of scanning lines 811 and supplies signals to the scanning lines 811, and the source driver 83 is connected to the plurality of data lines 812 and supplies signals to the data lines 812.
The gate driver 102 is internally provided with the gate scan driving circuit, the circuit board 104 is internally provided with a Level shifter (Level shift), a timing controller chip (T-CON), a GIP circuit and the like, and the circuit board outputs a low Level VSS, a current-stage clock signal CKm, a front-stage clock signal CKm-2, a rear-stage clock signal CKm +2, a first low-frequency clock signal LC1, a second low-frequency clock signal LC2 and a start signal STV to the gate scan driving circuit.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A gate drive unit, comprising: the device comprises a pull-up input module, a pull-up module, a pull-down module, a first single-pole maintenance control module and a first maintenance module;
the pull-up input module is connected with the drive signal input end and the pull-up control node, and is used for receiving a superior drive signal and setting the pull-up control node to be a first level when the superior drive signal is at the first level;
the pull-up module is connected with the pull-up control node, the clock signal input end and the driving signal output end and is used for conducting the clock signal input end and the driving signal output end when the pull-up control node is at a first level;
the pull-down module is connected with the pull-up control node, the drive signal output end, the lower drive signal input end and the second level input end, and is used for receiving a lower drive signal and conducting the pull-up control node and the drive signal output end with the second level input end when the lower drive signal is at a first level;
the first unipolar maintenance control module is connected to a first maintenance signal input end and a first low-frequency clock signal input end of the first maintenance module, and configured to receive a first low-frequency clock signal and set the first maintenance signal input end to a first level when the first low-frequency clock signal is at the first level, where the first unipolar maintenance control module includes: a gate and a source of the third transistor are both connected to the first low-frequency clock signal input terminal, a drain of the third transistor is connected to a gate of the fifth transistor, a source of the fifth transistor is connected to the first low-frequency clock signal input terminal, and a drain of the fifth transistor is connected to the first sustain signal input terminal of the first sustain module;
the first maintenance module is connected to the pull-up control node, the driving signal output end and the second level input end, and configured to enable the pull-up control node after being pulled down to the second level by the pull-down module, and conduct both the pull-up control node and the driving signal output end with the second level input end when the first maintenance signal input end of the first maintenance module is at the first level.
2. A gate drive unit as claimed in claim 1, wherein the first maintenance module comprises: a sixth transistor, a seventh transistor, and an eighth transistor;
a grid electrode of the sixth transistor is connected with the pull-up control node, a source electrode of the sixth transistor is connected with a first maintenance signal input end of the first maintenance module, and a drain electrode of the sixth transistor is connected with the second level input end;
a gate of the seventh transistor is connected to the first unipolar sustain control module, a source of the seventh transistor is connected to the pull-up control node, and a drain of the seventh transistor is connected to the second level input terminal;
and the grid electrode of the eighth transistor is connected with the first unipolar maintaining control module, the source electrode of the eighth transistor is connected with the driving signal output end, and the drain electrode of the eighth transistor is connected with the second level input end.
3. The gate driving unit of claim 1, wherein in the first unipolar sustain control module, a drain of a third transistor is connected to a second sustain signal input terminal of the first sustain module; the first maintenance module further comprises: a ninth transistor;
the gate of the ninth transistor is connected to the pull-up control node, the source of the ninth transistor is connected to the second sustain signal input terminal of the first sustain module, and the drain of the ninth transistor is connected to the second level input terminal.
4. A gate drive unit as claimed in claim 1, wherein the pull-down module comprises: a second transistor;
and the grid electrode of the second transistor is connected with the lower-level driving signal input end, the source electrode of the second transistor is connected with the pull-up control node, and the drain electrode of the second transistor is connected with the second level input end.
5. A gate drive unit as claimed in claim 4, wherein the pull-down module further comprises: a fourth transistor;
and the grid electrode of the fourth transistor is connected with the lower-level driving signal input end, the source electrode of the fourth transistor is connected with the driving signal output end, and the drain electrode of the fourth transistor is connected with the second level input end.
6. A gate drive unit as claimed in claim 1, wherein the pull-up input module comprises: a first transistor;
and the grid electrode and the source electrode of the first transistor are both connected with the driving signal input end, and the drain electrode of the first transistor is connected with the pull-up control node.
7. A gate drive unit as claimed in any one of claims 1 to 6, characterized in that the unit further comprises: the second unipolar maintenance control module is the same in structure as the first unipolar maintenance control module, and the second maintenance module is arranged symmetrically to the first maintenance module;
the second single-pole maintaining control module is connected with a first maintaining signal input end and a second low-frequency clock signal input end of the second maintaining module, and is used for receiving a second low-frequency clock signal and setting the first maintaining signal input end to be at a first level when the second low-frequency clock signal is at the first level;
the second maintenance module is connected to the pull-up control node, the driving signal output end and the second level input end, and configured to enable the pull-up control node after being pulled down to a second level by the pull-down module, and connect both the pull-up control node and the driving signal output end to the second level input end when the first maintenance signal input end is at a first level;
wherein the first low frequency clock signal and the second low frequency clock signal are opposite clock signals.
8. A gate drive unit as claimed in claim 1, wherein the pull-up module comprises: a tenth transistor and a first capacitor;
a grid electrode of the tenth transistor is connected with the pull-up control node, a source electrode of the tenth transistor is connected with the clock signal input end, and a drain electrode of the tenth transistor is connected with the driving signal output end;
one end of the first capacitor is connected with the pull-up control node, and the other end of the first capacitor is connected with the driving signal output end.
9. A gate scan driving circuit, comprising: a plurality of cascaded gate drive units; the gate driving unit is as claimed in any one of claims 1 to 8.
10. A liquid crystal display device, comprising: a liquid crystal display substrate, and a source driving circuit and a gate scanning driving circuit as claimed in claim 9 provided on the liquid crystal display substrate.
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| CN113870765A (en) * | 2020-06-30 | 2021-12-31 | 深圳市柔宇科技有限公司 | Light-emitting scanning signal line drive circuit, display panel and electronic device |
| CN112037728B (en) * | 2020-09-22 | 2022-03-15 | 成都中电熊猫显示科技有限公司 | Gate driving unit, gate scanning driving circuit and liquid crystal display device |
| CN114999420B (en) * | 2022-07-07 | 2023-05-02 | 武汉华星光电半导体显示技术有限公司 | GOA circuit and display panel |
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| CN108767015A (en) * | 2018-06-06 | 2018-11-06 | 中国科学院宁波材料技术与工程研究所 | Field-effect transistor and its application |
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| CN104269152B (en) * | 2014-10-22 | 2017-01-18 | 深圳市华星光电技术有限公司 | Line drive circuit used for oxide semiconductor thin-film transistor |
| CN104464662B (en) * | 2014-11-03 | 2017-01-25 | 深圳市华星光电技术有限公司 | GOA circuit based on low-temperature polycrystalline silicon semiconductor thin film transistor |
| CN107424575A (en) * | 2017-08-01 | 2017-12-01 | 深圳市华星光电半导体显示技术有限公司 | GOA drive circuits and liquid crystal panel |
| CN107358931B (en) * | 2017-09-04 | 2019-12-24 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit |
| CN107705768B (en) * | 2017-11-15 | 2019-07-02 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit |
| CN107919100B (en) * | 2018-01-04 | 2020-10-13 | 深圳市华星光电技术有限公司 | Grid driving circuit and liquid crystal display |
| CN108847193A (en) * | 2018-06-20 | 2018-11-20 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and liquid crystal display device with the GOA circuit |
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