CN108847193A - GOA circuit and liquid crystal display device with the GOA circuit - Google Patents
GOA circuit and liquid crystal display device with the GOA circuit Download PDFInfo
- Publication number
- CN108847193A CN108847193A CN201810639675.9A CN201810639675A CN108847193A CN 108847193 A CN108847193 A CN 108847193A CN 201810639675 A CN201810639675 A CN 201810639675A CN 108847193 A CN108847193 A CN 108847193A
- Authority
- CN
- China
- Prior art keywords
- thin film
- film transistor
- pull
- module
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 14
- 239000003990 capacitor Substances 0.000 claims abstract description 13
- 239000010409 thin film Substances 0.000 claims description 122
- 238000012423 maintenance Methods 0.000 abstract description 4
- 230000005540 biological transmission Effects 0.000 abstract 4
- 238000010586 diagram Methods 0.000 description 13
- 238000004088 simulation Methods 0.000 description 3
- 230000002349 favourable effect Effects 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a kind of GOA circuit, including multiple cascade GOA units, the N grades of GOA units include pull-up control module, pull-up module, lower transmission module, drop-down maintenance module, pull-down module and bootstrap capacitor；The pull-up control module is connect with the lower transmission module and the drop-down maintenance module respectively；The pull-up module is connect with the scan line of CK clock cable and the same level respectively；The lower transmission module is connect with CK clock cable and pull-down module respectively；The drop-down maintenance module and the pull-down module are connect with pulldown signal line respectively；The pull-down module is connect respectively with the scan line of the same level and the connection of XCK clock cable；One end of the bootstrap capacitor is connect with the pull-up control module and the lower transmission module respectively, the scan line connection of the other end and the same level.
Description
Technical Field
The invention relates to the technical field of liquid crystal display and the like, in particular to a GOA circuit and a liquid crystal display device with the GOA circuit.
Background
With the improvement of the performance of the TFT, the GOA technology is currently and widely applied to the panel, and has many advantages, so that Gate ICs can be saved, the yield of customers can be improved, and a frameless design can be realized.
The principle of the currently available GOA circuit is shown in fig. 1, and generally includes a pull-down unit, a pull-up unit, a pull-down sustain unit, and the like. Taking the 8CK circuit as an example, G (N) and Q (N) are pulled down by G (N +4) or ST (N-4) of the pull-down unit, and then the low-point bit is pull-down maintained by the pull-down maintaining circuit. The G (N) and Q (N) points are kept at a low potential in the sustain period. Wherein G (N +4) is an in-plane Gate signal, which traverses the entire plane and is affected by the in-plane conditions, and may affect the entire GOA cycle if there are particles or other abnormal conditions in the plane causing open or short circuits. And the pull-down is performed by using G (N +4) or ST (N-4), and the pull lines are required to be pulled among different stages in the circuit wiring, so that more space is required, and the narrow frame design is not facilitated. As shown in fig. 2, fig. 2 is a simple diagram using the lower signal pull-down, i.e., 1-pass 3, 6-pull 3, two windings are required, and more complex circuits may be N-pull down, N may be 4, 5, 6, or even more, which requires more windings and more space for circuit layout, which is not favorable for narrow frame design.
Disclosure of Invention
The invention provides a GOA circuit and a liquid crystal display device with the same, and aims to solve the problem that in the prior art, the display frame is not narrow enough due to the fact that the wiring of the GOA circuit is complex.
In order to solve the above technical problem, the present invention provides a GOA circuit, which includes a plurality of cascaded GOA units, wherein an nth level of the GOA unit includes a pull-up control module, a pull-up module, a pull-down maintaining module, a pull-down module, and a bootstrap capacitor; the pull-up control module is respectively connected with the pull-down module and the pull-down maintaining module; the pull-up module is respectively connected with the CK clock signal line and the scanning line of the current stage; the down-pulling module is connected with the CK clock signal line and the down-pulling module respectively; the pull-down maintaining module and the pull-down module are respectively connected with a pull-down signal line; the pull-down module is respectively connected with the scanning line of the current stage and the XCK clock signal line; one end of the bootstrap capacitor is connected with the pull-up control module and the download module respectively, and the other end of the bootstrap capacitor is connected with the scanning line of the stage.
In a preferred embodiment of the present invention, the pull-up control module includes a first thin film transistor T11, a gate of the first thin film transistor T11 is used for outputting a trigger signal of a GOA unit of the nth-4 th stage, and a drain of the first thin film transistor T11 is respectively connected to the pull-down module and the pull-down maintaining module.
In a preferred embodiment of the present invention, the down module includes a second thin film transistor T22, a gate of the second thin film transistor T22 is connected to a drain of the first thin film transistor T11, a source of the second thin film transistor T22 is connected to the CK clock signal line, and a drain of the second thin film transistor T22 is configured to output a trigger signal of the GOA unit of the current stage.
In a preferred embodiment of the present invention, the pull-up module includes a third tft T21, a gate of the third tft T21 is connected to a drain of the first tft T11, a source of the third tft T21 is connected to the CK clock signal line, and a drain of the third tft T21 is connected to the scan line of the current stage.
In a preferred embodiment of the present invention, the pull-down module includes a fourth thin film transistor T41 and a fifth thin film transistor T31, a gate of the fourth thin film transistor T41 is connected to the XCK clock signal line, a source of the fourth thin film transistor T41 is connected to the gate of the second thin film transistor T22, and a drain of the fourth thin film transistor T41 is connected to the pull-down signal line; a gate of the fifth thin film transistor T31 is connected to an XCK clock signal line, a source of the fifth thin film transistor T31 is connected to a scan line of the current stage, and a drain of the fifth thin film transistor T31 is connected to a pull-down signal line.
In a preferred embodiment of the present invention, the pull-down maintaining module includes a sixth thin film transistor T52, a seventh thin film transistor T51, an eighth thin film transistor T42, and a ninth thin film transistor T32; the gate of the sixth thin film transistor T52 is connected to the drain of the first thin film transistor T11, the source thereof is connected to the drain of the seventh thin film transistor T51, and the gate thereof is connected to a pull-down signal line; the gate of the seventh thin film transistor T51 is connected to the source thereof for receiving a control signal; a gate electrode of the eighth thin film transistor T42 is connected to a source electrode of the sixth thin film transistor T52, a source electrode of the eighth thin film transistor T42 is connected to a drain electrode of the first thin film transistor T11, and a drain electrode of the eighth thin film transistor T42 is connected to a pull-down signal line; the gate of the ninth thin film transistor T32 is connected to the source of the sixth thin film transistor T52, the source of the ninth thin film transistor T32 is connected to the scan line of the present stage, and the drain of the ninth thin film transistor T32 is connected to the pull-down signal line.
In a preferred embodiment of the present invention, one end of the bootstrap capacitor is a first node Q (N), and is connected to the drain of the first thin film transistor T11 through the first node Q (N).
In a preferred embodiment of the present invention, the source of the fourth thin film transistor T41 and the gate of the second thin film transistor T22 are connected to the drain of the first thin film transistor T11 through a first node Q (N).
In a preferred embodiment of the present invention, the gate of the eighth tft T42, the source of the sixth tft T52 and the drain of the seventh tft T51 are connected to each other through a second node P (N).
In order to solve the above technical problem, the present invention further provides a liquid crystal display device, including the GOA circuit.
The invention has the advantages that: according to the GOA circuit and the liquid crystal display device, the potentials of G (N) and Q (N) points are pulled down by using the XCK clock signal line, so that the problem that the whole device fails due to in-plane abnormity because the G (N) scanning line is used for pulling down is solved, and the product yield is improved. Meanwhile, all CK signals are at Busline, only one line is needed to pull the Busline signals to the Circuit for pull-down, so that the space required by a Circuit flat cable when G (N +4) or ST (N-4) is used for pull-down can be saved, and the narrow-frame design is facilitated.
Drawings
The invention is further explained below with reference to the figures and examples;
FIG. 1 is a basic block diagram of a GOA circuit in the prior art;
FIG. 2 is a waveform diagram of driving signals of a GOA circuit in the prior art;
FIG. 3 is a diagram of a portion of a prior art GOA circuit layout;
fig. 4 is a basic structure diagram of a GOA circuit according to an embodiment of the present invention;
FIG. 5 is a waveform diagram of driving signals of a GOA circuit according to an embodiment of the present invention;
FIG. 6 is a diagram of a portion of a GOA circuit layout structure according to an embodiment of the present invention;
FIG. 7 is a full level signal test diagram using XCK clock signal line pull-down output.
FIG. 8 is a diagram of a single-stage signal simulation using XCK clock line pull-down output;
FIG. 9 is a simplified diagram of a liquid crystal display device according to an embodiment of the present invention;
wherein,
1 a liquid crystal panel; 2GOA circuit;
100 a pull-up control module; 200, a pull-up module;
300 a download module; 400 pull down maintenance module;
500 pull down the module; 600 bootstrap capacitance;
700XCK clock signal line; 800CK clock signal lines;
900 scan lines of this level; 1000 pull down the signal line.
Detailed Description
The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced. The directional terms used in the present invention, such as "up", "down", "front", "back", "left", "right", "top", "bottom", etc., refer to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention.
The GOA circuit 2 comprises a plurality of cascaded GOA cells. As shown in fig. 3, fig. 3 is a diagram of the GOA unit in the nth stage according to the present invention. The N-th level GOA unit includes a pull-up control module 100, a pull-up module 200, a pull-down module 300, a pull-down sustain module 400, a pull-down module 500, and a bootstrap capacitor 600.
Specifically, the pull-up control module 100 is connected to the pull-down module 300 and the pull-down maintaining module 400, respectively. The pull-up module 200 is connected to the CK clock signal line 800 and the scan line 900 of the current stage, respectively; the pull-down module 300 is connected to the CK clock signal line 800 and the pull-down module 500, respectively; the pull-down maintaining module 400 and the pull-down module 500 are respectively connected to the pull-down signal lines; the pull-down module 500 is connected to the scan line 900 and the XCK clock signal line 700 of the current stage, respectively; one end of the bootstrap capacitor 600 is connected to the pull-up control module 100 and the pull-down module 300, respectively, and the other end is connected to the scan line 900 of the current stage.
The pull-up control module 100 includes a first thin film transistor T11, a gate of the first thin film transistor T11 is configured to receive a trigger signal ST (N-4) of the GOA cell of the nth-4 th stage, and a drain of the first thin film transistor is respectively connected to the pull-down module 300 and the pull-down sustain module 400.
The down-link module 300 includes a second thin film transistor T22, a gate of the second thin film transistor T22 is connected to a drain of the first thin film transistor T11, a source of the second thin film transistor T22 is connected to the CK clock signal line 800, and a drain of the second thin film transistor T22 is used for outputting the trigger signal ST (N) of the GOA cell of the current stage.
The pull-up module 200 includes a third thin film transistor T21, a gate of the third thin film transistor T21 is connected to a drain of the first thin film transistor T11, a source of the third thin film transistor T21 is connected to the CK clock signal line 800, and a drain of the third thin film transistor T21 is connected to the scan line 900 of the present stage.
The pull-down module 500 includes a fourth thin film transistor T41 and a fifth thin film transistor T31, a gate of the fourth thin film transistor T41 is connected to the XCK clock signal line 700, a source of the fourth thin film transistor T41 is connected to a gate of the second thin film transistor T22, and a drain of the fourth thin film transistor T41 is connected to the pull-down signal line; a gate of the fifth thin film transistor T31 is connected to the XCK clock signal line 700, a source of the fifth thin film transistor T31 is connected to the scan line 900 of the current stage, and a drain of the fifth thin film transistor T31 is connected to the pull-down signal line.
The pull-down maintaining module 400 includes a sixth thin film transistor T52, a seventh thin film transistor T51, an eighth thin film transistor T42, and a ninth thin film transistor T32; a gate of the sixth thin film transistor T52 is connected to the drain of the first thin film transistor T11, a source thereof is connected to the drain of the seventh thin film transistor T51, and a gate thereof is connected to the pull-down signal line; the gate of the seventh thin film transistor T51 is connected to the source thereof for receiving the control signal LC 1; a gate electrode of the eighth thin film transistor T42 is connected to a source electrode of the sixth thin film transistor T52, a source electrode of the eighth thin film transistor T42 is connected to a drain electrode of the first thin film transistor T11, and a drain electrode of the eighth thin film transistor T42 is connected to a pull-down signal line; the gate of the ninth thin film transistor T32 is connected to the source of the sixth thin film transistor T52, the source of the ninth thin film transistor T32 is connected to the scan line 900 of the present stage, and the drain of the ninth thin film transistor T32 is connected to the pull-down signal line. One end of the bootstrap capacitor 600 is a first node Q (N), and is connected to the drain of the first thin film transistor T11 through the first node Q (N). A source of the fourth thin film transistor T41 and a gate of the second thin film transistor T22 are connected to a drain of the first thin film transistor T11 through a first node Q (N). The gate electrode of the eighth thin film transistor T42, the source electrode of the sixth thin film transistor T52, and the drain electrode of the seventh thin film transistor T51 are connected through a second node P (N).
As shown in fig. 6, the pull-down connection line originally designed between the current stage signal and the pull-down signal in fig. 3 is omitted in fig. 6, and the pull-down connection line is added between the current stage signal and the XCK clock signal line 700, so that the space of circuit wiring is saved.
As shown in fig. 5, fig. 5 is a waveform diagram of the driving signal of the GOA circuit of the present invention. As can be seen, when G (N) is controlled by the CK clock signal, G (N-1) is controlled by the XCK clock signal, and G (N +1) is controlled by the XCK clock signal.
When G (N-1) is in operation: ST (N-1) is high, node Q (N) is high, and node P (N) is low.
When G (N) is active: ST (N) is high, node Q (N) will generate higher potential due to capacitance coupling effect, and point P (N) is low.
When G (N +1) is active: the node Q (N) is maintained at a low potential without generating a high potential.
This patent not only TFT is few, is favorable to the preparation of narrow frame, has left out original drop-down connecting wire, has guaranteed the normal wave form of Q (N) simultaneously, ensures that G (N) normally opens. The GOA circuit 2 of the present example was evaluated by simulation: the simulation results are shown in fig. 7 and 8. The GOA circuit 2 of this embodiment can output the Gate signal well, and fig. 7 and 8 show the full-level signal and the single-level signal outputted by using XCK pull-down, respectively. The new circuit can be seen to work normally, the product yield is increased, the Layout space is reduced, and the narrow frame design is facilitated
The embodiment also provides a liquid crystal display device, which comprises a liquid crystal panel 1 and a GOA circuit. As shown in fig. 9, fig. 9 is a simplified diagram of the liquid crystal display device of the present embodiment. Other structural features of the liquid crystal display device are conventional, and the connection structure between the GOA circuit and the other structural features of the present embodiment is a general knowledge that must be grasped by those skilled in the art, and will not be described again.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A GOA circuit is characterized by comprising a plurality of cascaded GOA units, wherein the GOA unit of the Nth level comprises a pull-up control module, a pull-up module, a pull-down maintaining module, a pull-down module and a bootstrap capacitor;
the pull-up control module is respectively connected with the pull-down module and the pull-down maintaining module;
the pull-up module is respectively connected with the CK clock signal line and the scanning line of the current stage;
the down-pulling module is connected with the CK clock signal line and the down-pulling module respectively;
the pull-down maintaining module and the pull-down module are respectively connected with a pull-down signal line;
the pull-down module is respectively connected with the scanning line of the current stage and the XCK clock signal line;
one end of the bootstrap capacitor is connected with the pull-up control module and the download module respectively, and the other end of the bootstrap capacitor is connected with the scanning line of the stage.
2. The GOA circuit of claim 1, wherein the pull-up control module comprises a first thin film transistor T11, a gate of the first thin film transistor T11 is configured to receive a trigger signal of a GOA unit of the Nth-4 th stage, and a drain of the first thin film transistor T11 is respectively connected to the pull-down module and the pull-down maintaining module.
3. The GOA circuit of claim 2, wherein the downstream module comprises a second thin film transistor T22, a gate of the second thin film transistor T22 is connected to a drain of the first thin film transistor T11, a source of the second thin film transistor T22 is connected to the CK clock signal line, and a drain of the second thin film transistor T22 is configured to output a trigger signal of a GOA unit of the current stage.
4. The GOA circuit of claim 3, wherein the pull-up module comprises a third TFT T21, the gate of the third TFT T21 is connected to the drain of the first TFT T11, the source of the third TFT T21 is connected to the CK clock signal line, and the drain of the third TFT T21 is connected to the scan line of the current stage.
5. The GOA circuit according to claim 4, wherein the pull-down module comprises a fourth thin film transistor T41 and a fifth thin film transistor T31, wherein a gate of the fourth thin film transistor T41 is connected to an XCK clock signal line, a source of the fourth thin film transistor T41 is connected to a gate of the second thin film transistor T22, and a drain of the fourth thin film transistor T41 is connected to a pull-down signal line; a gate of the fifth thin film transistor T31 is connected to an XCK clock signal line, a source of the fifth thin film transistor T31 is connected to a scan line of the current stage, and a drain of the fifth thin film transistor T31 is connected to a pull-down signal line.
6. The GOA circuit of claim 5, wherein the pull-down maintaining module comprises a sixth thin film transistor T52, a seventh thin film transistor T51, an eighth thin film transistor T42, a ninth thin film transistor T32; the gate of the sixth thin film transistor T52 is connected to the drain of the first thin film transistor T11, the source thereof is connected to the drain of the seventh thin film transistor T51, and the gate thereof is connected to a pull-down signal line; the gate of the seventh thin film transistor T51 is connected to the source thereof for receiving a control signal; a gate electrode of the eighth thin film transistor T42 is connected to a source electrode of the sixth thin film transistor T52, a source electrode of the eighth thin film transistor T42 is connected to a drain electrode of the first thin film transistor T11, and a drain electrode of the eighth thin film transistor T42 is connected to a pull-down signal line; the gate of the ninth thin film transistor T32 is connected to the source of the sixth thin film transistor T52, the source of the ninth thin film transistor T32 is connected to the scan line of the present stage, and the drain of the ninth thin film transistor T32 is connected to the pull-down signal line.
7. The GOA circuit of claim 6, wherein one end of the bootstrap capacitor is a first node Q (N), and is connected to the drain of the first thin film transistor T11 through the first node Q (N).
8. The GOA circuit according to claim 7, wherein the source of the fourth TFT T41 and the gate of the second TFT T22 are connected to the drain of the first TFT T11 via a first node Q (N).
9. The GOA circuit according to claim 6, wherein the gate of the eighth thin film transistor T42, the source of the sixth thin film transistor T52 and the drain of the seventh thin film transistor T51 are connected through a second node P (N).
10. A liquid crystal display device comprising the GOA circuit of any one of claims 1-9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810639675.9A CN108847193A (en) | 2018-06-20 | 2018-06-20 | GOA circuit and liquid crystal display device with the GOA circuit |
| PCT/CN2018/104511 WO2019242111A1 (en) | 2018-06-20 | 2018-09-07 | Goa circuit and liquid crystal display device having the goa circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810639675.9A CN108847193A (en) | 2018-06-20 | 2018-06-20 | GOA circuit and liquid crystal display device with the GOA circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108847193A true CN108847193A (en) | 2018-11-20 |
Family
ID=64202725
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810639675.9A Pending CN108847193A (en) | 2018-06-20 | 2018-06-20 | GOA circuit and liquid crystal display device with the GOA circuit |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN108847193A (en) |
| WO (1) | WO2019242111A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109616068A (en) * | 2019-01-04 | 2019-04-12 | 深圳市华星光电半导体显示技术有限公司 | GOA scanning circuit and liquid crystal display device |
| CN110827780A (en) * | 2019-11-25 | 2020-02-21 | 成都中电熊猫显示科技有限公司 | Gate driving unit, gate scanning driving circuit and liquid crystal display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060001637A1 (en) * | 2004-06-30 | 2006-01-05 | Sang-Jin Pak | Shift register, display device having the same and method of driving the same |
| US20150279481A1 (en) * | 2012-10-05 | 2015-10-01 | Sharp Kabushiki Kaisha | Shift register |
| CN106448606A (en) * | 2016-11-23 | 2017-02-22 | 深圳市华星光电技术有限公司 | GOA (gate driver on array) driving circuit |
| CN107068087A (en) * | 2017-03-31 | 2017-08-18 | 深圳市华星光电技术有限公司 | A kind of GOA drive circuits |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI421881B (en) * | 2009-08-21 | 2014-01-01 | Au Optronics Corp | Shift register |
| CN104795034B (en) * | 2015-04-17 | 2018-01-30 | 深圳市华星光电技术有限公司 | A kind of GOA circuits and liquid crystal display |
| CN106997753B (en) * | 2017-04-07 | 2019-07-12 | 深圳市华星光电技术有限公司 | A kind of GOA driving circuit |
| CN107123405A (en) * | 2017-06-01 | 2017-09-01 | 深圳市华星光电技术有限公司 | Bidirectional shift register unit, bidirectional shift register and display panel |
| CN107154245B (en) * | 2017-07-17 | 2019-06-25 | 深圳市华星光电技术有限公司 | A kind of gate driving circuit and its driving method |
| CN107358931B (en) * | 2017-09-04 | 2019-12-24 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit |
-
2018
- 2018-06-20 CN CN201810639675.9A patent/CN108847193A/en active Pending
- 2018-09-07 WO PCT/CN2018/104511 patent/WO2019242111A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060001637A1 (en) * | 2004-06-30 | 2006-01-05 | Sang-Jin Pak | Shift register, display device having the same and method of driving the same |
| US20150279481A1 (en) * | 2012-10-05 | 2015-10-01 | Sharp Kabushiki Kaisha | Shift register |
| CN106448606A (en) * | 2016-11-23 | 2017-02-22 | 深圳市华星光电技术有限公司 | GOA (gate driver on array) driving circuit |
| CN107068087A (en) * | 2017-03-31 | 2017-08-18 | 深圳市华星光电技术有限公司 | A kind of GOA drive circuits |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109616068A (en) * | 2019-01-04 | 2019-04-12 | 深圳市华星光电半导体显示技术有限公司 | GOA scanning circuit and liquid crystal display device |
| WO2020140321A1 (en) * | 2019-01-04 | 2020-07-09 | 深圳市华星光电半导体显示技术有限公司 | Goa scanning circuit and liquid crystal display device |
| CN110827780A (en) * | 2019-11-25 | 2020-02-21 | 成都中电熊猫显示科技有限公司 | Gate driving unit, gate scanning driving circuit and liquid crystal display device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2019242111A1 (en) | 2019-12-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107799083B (en) | GOA circuit | |
| DE112014007252B4 (en) | Shift register, step-by-step transfer gate drive and display panel | |
| KR101937963B1 (en) | Scan driving circuit | |
| CN103117091B (en) | Shift buffer and driving method thereof | |
| DE102014019791B4 (en) | Gate driver device and display device | |
| KR101985119B1 (en) | Goa circuit and liquid crystal display device | |
| US7688934B2 (en) | Shift register and shift register unit for diminishing clock coupling effect | |
| CN106448592B (en) | GOA driving circuits and liquid crystal display device | |
| JP6732911B2 (en) | Gate drive circuit and display device | |
| US10204580B2 (en) | Scan-driving device with detective-driving circuit | |
| JP2019537073A (en) | GOA drive circuit and liquid crystal display device | |
| CN108320717B (en) | GOA driving circuit and liquid crystal display panel prepared by same | |
| CN100397468C (en) | Shift register circuit | |
| JP2020502554A (en) | GOA drive circuit and liquid crystal display device | |
| CN111145680B (en) | Drive circuit and display panel | |
| CN107492362B (en) | Grid driving circuit and liquid crystal display | |
| US10580375B2 (en) | Gate drive circuit | |
| CN107331360B (en) | GOA circuit and liquid crystal display device | |
| CN105304044A (en) | Liquid crystal display device and GOA circuit | |
| CN107086028B (en) | Liquid crystal display device and its GOA circuit | |
| KR102608449B1 (en) | Array substrate row driving circuit unit, its driving circuit, and liquid crystal display panel | |
| CN104008738A (en) | Display Panel and Gate Driver | |
| CN110827776A (en) | GOA device and gate drive circuit | |
| CN113257134A (en) | Display panel and display device | |
| CN108847193A (en) | GOA circuit and liquid crystal display device with the GOA circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20181120 |