CN113092863A - Method and device for measuring and calculating internal resistance of grid electrode of power device and storage medium - Google Patents

Method and device for measuring and calculating internal resistance of grid electrode of power device and storage medium Download PDF

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CN113092863A
CN113092863A CN202110391454.6A CN202110391454A CN113092863A CN 113092863 A CN113092863 A CN 113092863A CN 202110391454 A CN202110391454 A CN 202110391454A CN 113092863 A CN113092863 A CN 113092863A
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power device
voltage
inter
value
driving
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CN113092863B (en
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孙帅
韩荣刚
杜玉杰
赵志斌
李学宝
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North China Electric Power University
Global Energy Interconnection Research Institute
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Global Energy Interconnection Research Institute
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Abstract

The invention discloses a method, a device and a storage medium for measuring and calculating grid internal resistance of a power device, wherein the method comprises the following steps: constructing a double-pulse test circuit; establishing a first calculation relational expression related to the internal resistance of the grid according to a driving voltage value of a driving power supply, a first preset resistance value of a driving external resistor, a first inter-electrode capacitance value of a power device to be tested and a first change rate of the capacitance voltage between the first electrodes; changing the driving external resistance into a second preset resistance value, and establishing a second calculation relational expression about the first end voltage and the grid internal resistance of the power device to be tested according to the driving voltage value of the driving power supply, the second preset resistance value, the first inter-electrode capacitance value of the power device to be tested and the second change rate of the first inter-electrode capacitance voltage; and calculating the resistance value of the grid internal resistance according to the first calculation relational expression and the second calculation relational expression. By implementing the invention, the grid internal resistance of the power device can be calculated by adopting a simple test method and a common test instrument, and the invention has higher practical value.

Description

Method and device for measuring and calculating internal resistance of grid electrode of power device and storage medium
Technical Field
The invention relates to the technical field of power electronic devices, in particular to a method and a device for measuring and calculating grid internal resistance of a power device and a storage medium.
Background
The power semiconductor device is a power electronic device for high power in the aspect of power conversion and control circuits of power equipment, and therefore, the power semiconductor device is a core device in the power electronic device. With the rapid development of digital information technology, power semiconductor devices are more and more widely applied, wherein an Insulated Gate Bipolar Transistor (IGBT) is a transistor which can be widely used in analog circuits and digital circuits, and therefore, if the IGBT device is fully utilized, it is necessary to research the electrical characteristics of the IGBT device, wherein the Gate internal resistance of the IGBT device belongs to one of important electrical characteristic parameters, the Gate internal resistance of the IGBT device affects the charging and discharging speed of the device, and the measurement of the Gate internal resistance of the IGBT device is helpful for the drive matching of the device. At present, the internal resistance of the grid electrode of the IGBT device is difficult to test, and a complex test instrument is needed.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method, an apparatus, and a storage medium for measuring and calculating a gate internal resistance of a power device, so as to solve the technical problem in the prior art that it is difficult to test the gate internal resistance of an IGBT.
The technical scheme provided by the invention is as follows:
the first aspect of the embodiments of the present invention provides a method for measuring and calculating internal resistance of a gate of a power device, including: constructing a double-pulse test circuit, wherein the double-pulse test circuit comprises a power device to be tested, a driving power supply and a driving external resistor; establishing a first calculation relation formula about the first end voltage and the grid internal resistance of the power device to be tested according to the driving voltage value of the driving power supply, the first preset resistance value of the driving external resistor, the first inter-electrode capacitance value of the power device to be tested and the first change rate of the first inter-electrode capacitance voltage, wherein the first change rate of the first inter-electrode capacitance voltage is the change rate of the first inter-electrode capacitance voltage during the Miller platform period; changing the driving external resistance into a second preset resistance value, and establishing a second calculation relational expression about the first end voltage and the grid internal resistance of the power device to be tested according to the driving voltage value of the driving power supply, the second preset resistance value, the first inter-electrode capacitance value of the power device to be tested and a second change rate of the first inter-electrode capacitance voltage, wherein the second change rate of the first inter-electrode capacitance voltage is the change rate of the first inter-electrode capacitance voltage during the Miller platform period; and calculating the resistance value of the grid internal resistance according to the first calculation relational expression and the second calculation relational expression.
Optionally, the first rate of change of the first inter-electrode capacitance voltage is calculated by the following formula:
Figure BDA0003014524160000021
wherein the content of the first and second substances,
Figure BDA0003014524160000022
is a first rate of change, V, of the capacitance voltage between the first electrodesCE1The voltage of the second end of the power device to be tested when the driving external resistor is a first preset resistance value (t)b1，Vb1) And (t)a1，Va1) Is at t-VCE1Two coordinates during the period of the Miller platform selected on the curve;
the second rate of change of the first inter-electrode capacitance voltage is calculated by the following formula:
Figure BDA0003014524160000023
wherein the content of the first and second substances,
Figure BDA0003014524160000024
is a second rate of change, V, of the first inter-electrode capacitance voltageCE2The power device to be tested is driven by the external resistor with the second preset resistance value(ii) a second terminal voltage, (t)b2，Vb2) And (t)a2，Va2) Is at t-VCE2Two coordinates during the selected miller stage on the curve.
Optionally, the first time difference value and the second time difference value are equal, and the first time difference value is denoted as tb1-ta1Said second time difference being denoted tb2-ta2。
Optionally, the driving voltage value is a driving voltage value of an on process or a driving voltage value of an off process, and the change rate of the first inter-electrode capacitance voltage during the miller plateau is a change rate of the first inter-electrode capacitance voltage during the miller plateau is on or a change rate of the first inter-electrode capacitance voltage during the miller plateau is off.
Optionally, during the turning on of the miller platform, the first calculation relation is expressed by the following formula:
Figure BDA0003014524160000031
wherein, VGin,PIs the first terminal voltage, V, of the power device to be testedG,offFor the drive voltage value, R, of the drive power supply during the switching-on of the Miller platformext1Is the first predetermined resistance value, RintIs the internal resistance of the gate, CGCA first inter-electrode capacitance value of a power device to be tested;
the second calculation relationship is expressed by the following formula:
Figure BDA0003014524160000032
wherein R isext2Is the second preset resistance value;
during the off-period of the miller platform, the first calculation relationship is represented by the following formula:
Figure BDA0003014524160000033
wherein, VG,onThe driving voltage value of the driving power supply during the period of turning off the Miller platform;
the second calculation relationship is expressed by the following formula:
Figure BDA0003014524160000034
optionally, the resistance value of the gate internal resistance is calculated by the following formula:
Figure BDA0003014524160000035
wherein, is Δ V1＝Vb1-Va1，ΔV2＝Vb2-Va2。
Optionally, the power device to be tested is an IGBT.
A second aspect of the embodiments of the present invention provides a device for measuring and calculating internal resistance of a gate of a power device, including: the device comprises a construction module, a power supply module and a drive external resistor, wherein the construction module is used for constructing a double-pulse test circuit which comprises a power device to be tested, a drive power supply and a drive external resistor; a first establishing module, configured to establish a first calculation relation regarding a first end voltage and a gate internal resistance of the power device to be tested according to a driving voltage value of the driving power supply, a first preset resistance value of the external driving resistor, a first inter-electrode capacitance value of the power device to be tested, and a first change rate of a first inter-electrode capacitance voltage, where the first change rate of the first inter-electrode capacitance voltage is a change rate of the first inter-electrode capacitance voltage during the miller plateau; a second establishing module, configured to change the external driving resistance to a second preset resistance value, and establish a second calculation relation between the first terminal voltage of the power device to be tested and the internal gate resistance according to a driving voltage value of the driving power supply, the second preset resistance value, the first inter-electrode capacitance value of the power device to be tested, and a second change rate of the first inter-electrode capacitance voltage, where the second change rate of the first inter-electrode capacitance voltage is a change rate of the first inter-electrode capacitance voltage during the miller plateau; and the calculation module is used for calculating the resistance value of the grid internal resistance according to the first calculation relational expression and the second calculation relational expression.
A third aspect of the embodiments of the present invention provides a computer-readable storage medium, where computer instructions are stored, and the computer instructions are configured to cause the computer to execute the method for measuring and calculating gate internal resistance of a power device according to any one of the first aspect and the first aspect of the embodiments of the present invention.
A fourth aspect of an embodiment of the present invention provides an electronic device, including: the memory and the processor are connected with each other in a communication mode, the memory stores computer instructions, and the processor executes the computer instructions to execute the method for measuring and calculating the internal resistance of the gate of the power device according to any one of the first aspect and the first aspect of the embodiments of the invention.
The technical scheme provided by the invention has the following effects:
the method, the device and the storage medium for measuring and calculating the gate internal resistance of the power device are based on a double-pulse test circuit, when the power device to be measured is on a Miller platform, a first calculation relational expression about the first end voltage and the gate internal resistance of the power device to be measured is established by combining a driving voltage value of a driving power supply, a first preset resistance value of a driving external resistance, a first inter-electrode capacitance value of the power device to be measured and a first change rate of a first inter-electrode capacitance voltage, a second calculation relational expression about the first end voltage and the gate internal resistance of the power device to be measured is established by combining the driving voltage value of the driving power supply, a second preset resistance value, the first inter-electrode capacitance value of the power device to be measured and a second change rate of the first inter-electrode capacitance voltage, two calculation relational expressions are further combined to obtain the gate internal resistance of the power device to be measured, in the process of solving the simultaneous difference equation, the voltage at the first end of the power device to be measured can be eliminated as an intermediate quantity, and measurement is not needed. Therefore, the method for measuring and calculating the internal resistance of the gate of the power device provided by the embodiment of the invention can calculate the internal resistance of the gate of the power device by adopting a simple test method and a common test instrument without using a complex test instrument, and has higher practical value.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart of a method for measuring gate internal resistance of a power device according to an embodiment of the invention;
FIG. 2 is a diagram of a double pulse test circuit according to an embodiment of the present invention;
fig. 3 is a waveform diagram of an IGBT turn-on process according to an embodiment of the invention;
FIG. 4 is a diagram of an IGBT input side model and a drive model during switching on of the Miller platform according to an embodiment of the present invention;
FIG. 5 is a diagram of a dual pulse test waveform for a turn-on process according to an embodiment of the present invention;
FIG. 6 is a diagram of a dual pulse test waveform for a turn-on process according to another embodiment of the present invention;
fig. 7 is a waveform diagram of an IGBT turn-off process according to an embodiment of the invention;
FIG. 8 is a diagram of the IGBT input side model and the drive model during the switching off of the Miller stage according to an embodiment of the present invention;
FIG. 9 is a diagram of a dual pulse test waveform for a shut down process according to an embodiment of the present invention;
FIG. 10 is a block diagram of an apparatus for measuring gate internal resistance of a power device according to an embodiment of the present invention;
FIG. 11 is a schematic structural diagram of a computer-readable storage medium provided in accordance with an embodiment of the present invention;
fig. 12 is a schematic structural diagram of an electronic device provided in an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
The embodiment of the invention provides a method for measuring and calculating the internal resistance of a grid electrode of a power device, as shown in figure 1, the evaluation method comprises the following steps:
step S101: and constructing a double-pulse test circuit, wherein the double-pulse test circuit comprises a power device to be tested, a driving power supply and a driving external resistor.
In an embodiment, the power device to be tested may be a MOSFET chip or an IGBT chip, which is not limited in the embodiment of the present invention. The method for measuring and calculating the internal resistance of the gate of the power device is described below by taking the power device to be measured as an IGBT chip as an example. As shown in FIG. 2, a double pulse test circuit, R, is employed for this embodimentextTo drive an external resistance, RintIs the internal resistance of the device gate, CGCIs the gate-collector capacitance, CGEIs the gate-emitter capacitance, VDCIs the bus voltage, LloadIs a load inductance, CCEIs the collector-emitter capacitance, LσIs parasitic inductance of power loop, VG,offAnd VG,onThe driving voltage values of the driving power supply during the ON period and the OFF period, respectively, DFThe test diode is used.
Step S102: establishing a first calculation relation related to the first end voltage and the grid internal resistance of the power device to be tested according to the driving voltage value of the driving power supply, the first preset resistance value of the driving external resistor, the first inter-electrode capacitance value of the power device to be tested and the first change rate of the first inter-electrode capacitance voltage, wherein the first change rate of the first inter-electrode capacitance voltage is the change rate of the first inter-electrode capacitance voltage during the Miller platform.
Specifically, fig. 3 shows a typical turn-on waveform under a double-pulse test condition when the power device to be tested is an IGBT, and since the diode reverse recovery characteristic has no influence on the measurement method, the reverse recovery characteristic of the accompanying diode is not considered in the waveform. Wherein VGsingalFor the drive signal, VGIs the device gate voltage, ICIs the collector current of the device, VCEFor collector-emitter voltage of the device, VGE,onFor driving high values of signal, VGPDevice gate voltage value, V, for Miller platformthIs a threshold voltage value, ILAt a rated current value, VbusIs the value of the bus voltage, VcesatIs the device saturation voltage value. At t2At the moment the collector current reaches the nominal value, the gate voltage enters the miller plateau, after which at t2-t3The waveform characteristics of the time period are as follows: the collector-emitter voltage changes rapidly and the gate voltage exhibits a miller plateau.
FIG. 4 is a driving portion of an input side model of a power device to be tested and a test circuit during the switching on of the Miller platform, the circuit neglects parasitic parameters of all poles with small influence, the flow direction of grid current in partial devices is marked in the figure, wherein RextFor driving external resistance of the circuit, RintIs the internal resistance of the device, CGCIs the gate-collector capacitance, CGEThe gate-emitter capacitance. Since the driving voltage is constant, the gate current flows entirely into the collector-gate capacitance, which is represented by gate current CGCDischarge, CGCCollector-emitter voltage V of two-terminal voltage followerCEDecreases rapidly. Thus V can be adoptedCEDv/dt of the descending process estimates the internal resistance R of the gridintThe size of (2).
In an embodiment, V may be based on a period of time V during which the Miller platform is turned onCEThe change in gate internal resistance is calculated. Specifically, in the turn-on process, after the power device to be tested enters the Miller platform, the bus voltage source starts to supply CGCDischarge, internal grid GinVoltage VGinIs maintained unchanged and has a size of VGin,PThe voltage value is not the Miller platform voltage at the test end, and the Miller platform voltage at the test end is divided by VGinExternal bagIncluding the voltage on the internal resistance of the gate. According to the model shown in FIG. 4, the gate current igCan be expressed as:
Figure BDA0003014524160000081
wherein, CGCA first inter-electrode capacitance value of the power device to be measured, i.e. a gate-collector capacitance, VGin,PIs the first terminal voltage, V, of the power device to be testedCIs CGCThe voltage at two ends is smaller at the moment di/dt, the voltage drop on the parasitic parameters of the collector and the emitter package can be ignored, and VCIs approximately equal to VCEThe method comprises the following steps:
Figure BDA0003014524160000082
thus, equation (1) can be rewritten as:
Figure BDA0003014524160000083
in the formula (3), VG,offAnd RextCan be set by presetting, dVCEThe/dt can be obtained by a double-pulse test waveform, and the specific obtaining method is as follows: at t-V, as shown in FIG. 5CEOn the curve, a certain point is taken in the voltage change section, and the time is marked as tr0(ii) a At t ═ tr0The time and voltage values around the point are recorded as (t)m，Vm) And (t)n，Vn) (ii) a Then dVCEThe/dt can be expressed as:
Figure BDA0003014524160000084
in one embodiment, since equation (3) includes two unknown parameters, V needs to be transformed by "difference methodGin,PAnd (5) eliminating. If different driving external resistors R are adopted for the same power device to be testedext1，Rext2The two double-pulse tests are respectively completed, and the voltage change rate in the turn-off process is changed. If the turn-off current is kept consistent, according to the principle of a controlled source model, in a linear region of the IGBT, IC is gm (V)GE-Vth) Where gm is the transconductance of the IGBT, VGEIs the gate emitter drive voltage, V, of the IGBTthIs the IGBT threshold voltage. Because the turn-off current of the double-pulse test circuit is determined by the bus voltage and the load inductance, even if the driving resistance is different, the collector current of the IGBT is the same in the Miller platform stage, and then V isGinSame, are all VGin,P. Therefore, V in formula (3) can be eliminated by changing the driving external resistanceGin,P. When the external resistance is the first preset resistance Rext1When, formula (3) can be rewritten as:
Figure BDA0003014524160000091
wherein the content of the first and second substances,
Figure BDA0003014524160000092
is a first rate of change, V, of the capacitance voltage between the first electrodesCE1The voltage of the second end of the power device to be tested is the collector-emitter voltage of the power device to be tested when the driving external resistor is a first preset resistance value.
Step S103: and changing the driving external resistance into a second preset resistance value, and establishing a second calculation relation formula about the first end voltage and the grid internal resistance of the power device to be tested according to the driving voltage value of the driving power supply, the second preset resistance value, the first inter-electrode capacitance value of the power device to be tested and a second change rate of the first inter-electrode capacitance voltage, wherein the second change rate of the first inter-electrode capacitance voltage is the change rate of the first inter-electrode capacitance voltage during the Miller platform.
Specifically, when the driving external resistance is changed from the first preset resistance value to the second preset resistance value, formula (5) becomes formula (6):
Figure BDA0003014524160000093
wherein the content of the first and second substances,
Figure BDA0003014524160000094
is a second rate of change of the first interelectrode capacitance voltage.
Step S104: and calculating the resistance value of the grid internal resistance according to the first calculation relational expression and the second calculation relational expression. Specifically, by combining the formula (5) and the formula (6), the expression of the gate internal resistance can be obtained as follows:
Figure BDA0003014524160000095
in one embodiment, as shown in fig. 6, in order to reduce the calculation time of the internal resistance of the gate, a first time difference value t may be setn1-tm1And a second time difference tn2-tm2Equality, whereby equation (7) can be further simplified as:
Figure BDA0003014524160000101
wherein Vm1To drive the external resistor with a resistance value of Rext1When, VCEAt tm1Voltage value of time, Vm2To drive the external resistor with a resistance value of Rext2When, VCEAt tm2A voltage value at a time; vn1Is a resistance of Rext1When, VCEAt tn1Voltage value of time, Vn2Is a resistance of Rext2When, VCEAt tn2The voltage value at the moment. Let Δ V1＝Vn1-Vm1，ΔV2＝Vn2-Vm2Then equation (8) can be rewritten as:
Figure BDA0003014524160000102
in one embodiment, FIG. 7 shows an IGBT on-double-pulse test stripA typical turn-off waveform under conditions. At t1At time, the gate voltage goes to turn off the miller stage, after which it is at t1-t2The waveform characteristics of the time period are as follows: the collector current is unchanged, the collector-emitter voltage changes rapidly, and the gate voltage appears in a Miller platform. Fig. 8 shows the input side model of the test device and the driving part of the test circuit during the switching off of the miller stage, which ignores the parasitic parameters of the poles with less influence, and marks the flow direction of the gate current in some components. Since the driving voltage is constant, the gate current flows out from the collector-gate capacitor completely, and the gate current is CGCCharging, CGCThe voltage at both ends rises rapidly along with the voltage of the collector and the emitter of the device. Therefore, the period V of switching off the Miller stage can be adoptedCEDv/dt of rising process estimates internal resistance R of grid electrodeintThe size of (2).
Specifically, during the shutdown process, after entering the miller platform, the bus voltage source starts to supply CGCCharging, internal grid GinVoltage VGinIs maintained unchanged and has a size of VGin,PThe voltage value is not the Miller platform voltage at the test end, and the Miller platform voltage at the test end is divided by VGinAnd the voltage on the internal resistance of the grid electrode is also included. According to the model shown in FIG. 8, the gate current igCan be expressed as:
Figure BDA0003014524160000103
wherein VCIs CGCThe voltage at two ends is smaller at the moment di/dt, the voltage drop on the parasitic parameters of the collector and the emitter package can be ignored, and VCIs approximately equal to VCEThen, then
Figure BDA0003014524160000104
Thus, when the driving external resistance is set to the first preset resistance value, the formula (10) can be rewritten as:
Figure BDA0003014524160000111
similarly, when the driving external resistance is set to the second preset resistance value, equation (10) becomes:
Figure BDA0003014524160000112
in particular, the amount of the solvent to be used,
by combining the formula (11) and the formula (12), the expression of the gate internal resistance can be obtained as follows:
Figure BDA0003014524160000113
in order to reduce the calculation time of the internal resistance of the gate, as shown in fig. 9, a time difference t between two times of sampling may be setb1-ta1And tb2-ta2Similarly, equation (13) can be further modified as:
Figure BDA0003014524160000114
wherein Va1To drive the external resistor with a resistance value of Rext1When, VCEAt ta1Voltage value of time, Va2To drive the external resistor with a resistance value of Rext2When, VCEAt ta2Voltage value of time, Vb1Is a resistance of Rext1When, VCEAt tb1Voltage value of time, Vb2Is a resistance of Rext2When, VCEAt tb2The voltage value at the moment. Let Δ V1＝Vb1-Va1，ΔV2＝Vb2-Va2Equation (14) may be rewritten as:
Figure BDA0003014524160000115
in addition, at Va1、Vb1、Va2、Vb2、Vm1、Vn1、Vm2、Vn2The letters a, b, m, n, etc. are selected only to facilitate V for the turn-on and turn-off processesCEThe selected voltage value is used for illustration, and other letters can be selected, which is not limited in the present invention.
The method for measuring and calculating the gate internal resistance of the power device provided by the embodiment of the invention is based on a double-pulse test circuit, when the power device to be measured is positioned on a Miller platform, a first calculation relational expression about the first end voltage and the gate internal resistance of the power device to be measured is established by combining the driving voltage value of a driving power supply, a first preset resistance value of a driving external resistor, a first inter-electrode capacitance value of the power device to be measured and a first change rate of a first inter-electrode capacitance voltage, a second calculation relational expression about the first end voltage and the gate internal resistance of the power device to be measured is established by combining the driving voltage value of the driving power supply, a second preset resistance value, the first inter-electrode capacitance value of the power device to be measured and a second change rate of the first inter-electrode capacitance voltage, so as to establish the two calculation relational expressions to obtain the gate internal resistance of the power device to be measured, and, the voltage at the first end of the power device to be measured can be eliminated as an intermediate quantity, and measurement is not needed. Therefore, the method for measuring and calculating the internal resistance of the gate of the power device provided by the embodiment of the invention can calculate the internal resistance of the gate of the power device by adopting a simple test method and a common test instrument without using a complex test instrument, and has higher practical value.
Example 2
An embodiment of the present invention further provides a device for measuring and calculating internal resistance of a gate of a power device, as shown in fig. 10, the device includes:
the device comprises a construction module 1, a power supply module and a drive external resistor, wherein the construction module is used for constructing a double-pulse test circuit which comprises a power device to be tested, a drive power supply and a drive external resistor; for details, refer to the related description of step S101 in the above method embodiment.
The first establishing module 2 is configured to establish a first calculation relation equation regarding a first end voltage and a gate internal resistance of the power device to be tested according to a driving voltage value of a driving power supply, a first preset resistance value of the external driving resistor, a first inter-electrode capacitance value of the power device to be tested, and a first change rate of a first inter-electrode capacitance voltage, where the first change rate of the first inter-electrode capacitance voltage is a change rate of the first inter-electrode capacitance voltage during the miller plateau; for details, refer to the related description of step S102 in the above method embodiment.
A second establishing module 3, configured to change the driving external resistance to a second preset resistance value, and establish a second calculation relation regarding the first terminal voltage and the gate internal resistance of the power device to be tested according to the driving voltage value of the driving power supply, the second preset resistance value, the first inter-electrode capacitance value of the power device to be tested, and a second change rate of the first inter-electrode capacitance voltage, where the second change rate of the first inter-electrode capacitance voltage is a change rate of the first inter-electrode capacitance voltage during the miller plateau; for details, refer to the related description of step S103 in the above method embodiment.
And the calculating module 4 is used for calculating the resistance value of the grid internal resistance according to the first calculating relational expression and the second calculating relational expression. For details, refer to the related description of step S104 in the above method embodiment.
The device for measuring and calculating the internal resistance of the grid electrode of the power device is based on a double-pulse test circuit, when the power device to be measured is positioned on a Miller platform, a first calculation relational expression about the voltage of the first end of the power device to be measured and the internal resistance of the grid electrode is established by combining the driving voltage value of a driving power supply, a first preset resistance value of a driving external resistor, the capacitance value between the first electrodes of the power device to be measured and a first change rate of the capacitance voltage between the first electrodes, a second calculation relational expression about the voltage of the first end of the power device to be measured and the internal resistance of the grid electrode is established by combining the driving voltage value of the driving power supply, a second preset resistance value, the capacitance value between the first electrodes of the power device to be measured and a second change rate of the capacitance voltage between the first electrodes, then the two calculation relational expressions are combined to obtain the internal resistance of the grid electrode of, the voltage at the first end of the power device to be measured can be eliminated as an intermediate quantity, and measurement is not needed. Therefore, the device for measuring and calculating the internal resistance of the grid electrode of the power device provided by the embodiment of the invention can calculate the internal resistance of the grid electrode of the power device by adopting a simple test method and a common test instrument without using a complex test instrument, and has higher practical value.
The functional description of the device for measuring and calculating the internal resistance of the gate of the power device provided by the embodiment of the invention refers to the description of the method for measuring and calculating the internal resistance of the gate of the power device in the embodiment.
Example 3
The embodiment of the invention provides a method for measuring and calculating the internal resistance of a grid of a power device, which is used for verifying the accuracy of calculating the internal resistance of the grid by adopting the formula (9) and the formula (15). Specifically, power device selection: 1200V, 50A silicon-based IGBT; the set value of the IGBT internal resistance is 10.5 omega; in the employed double pulse test circuit, VDC＝800V，VGC＝0/15V，Ig＝50A，Rext1＝12Ω，Rext2＝18Ω。
In one embodiment, the collector-emitter voltage V of different driving external resistors in the turn-off process is collectedCECollector current ICWaveform, selecting two time points respectively at VCERead voltage value on curve, labeled Va1、Vb1、Va2And Vb2The resulting simulation parameters are shown in table 1.
TABLE 1
Rext Va Vb ΔV
Test1 12Ω 611.68V 772.01V 160.33V
Test2 18Ω 316.44V 442.87V 126.43V
According to the simulation parameters and the formula (15), the internal resistance of the grid electrode is calculated to be
Figure BDA0003014524160000141
Figure BDA0003014524160000142
Comparing the calculated internal resistance value of the grid with the set internal resistance value of the grid, the error rate of the method is only 1.14 percent, namely the method for measuring and calculating the internal resistance value of the grid of the power device has more accurate calculation result.
In one embodiment, the collector-emitter voltages V of different driving external resistors in the turn-on process are collectedCECollector current ICWaveform, selecting two time points respectively at VCERead voltage value on curve, labeled Vm1、Vn1、Vm2、Vn2The resulting simulation parameters are shown in table 2.
TABLE 1
Rext Vm Vn ΔV
Test1 12Ω 401.47V 277.69V -123.78V
Test2 18Ω 508.07V 410.23V -97.84V
According to the simulation parameters and the formula (15), the internal resistance of the grid electrode is calculated to be
Figure BDA0003014524160000143
Figure BDA0003014524160000144
Comparing the calculated internal resistance value of the grid with the set internal resistance value of the grid, the error rate of the method is only 1.24 percent, namely the method for measuring and calculating the internal resistance value of the grid of the power device has more accurate calculation result.
Example 4
An embodiment of the present invention further provides a storage medium, as shown in fig. 11, on which a computer program 601 is stored, where the instructions are executed by a processor to implement the steps of the method for calculating the gate internal resistance of a power device in the foregoing embodiments. The storage medium is also stored with audio and video stream data, characteristic frame data, an interactive request signaling, encrypted data, preset data size and the like. The storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a Hard Disk (Hard Disk Drive, abbreviated as HDD) or a Solid State Drive (SSD), etc.; the storage medium may also comprise a combination of memories of the kind described above.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a Hard Disk (Hard Disk Drive, abbreviated as HDD) or a Solid State Drive (SSD), etc.; the storage medium may also comprise a combination of memories of the kind described above.
Example 5
An embodiment of the present invention further provides an electronic device, as shown in fig. 12, the electronic device may include a processor 51 and a memory 52, where the processor 51 and the memory 52 may be connected by a bus or in another manner, and fig. 12 takes the example of connection by a bus as an example.
The processor 51 may be a Central Processing Unit (CPU). The Processor 51 may also be other general purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, or combinations thereof.
The memory 52, which is a non-transitory computer readable storage medium, may be used to store non-transitory software programs, non-transitory computer executable programs, and modules, such as the corresponding program instructions/modules in the embodiments of the present invention. The processor 51 executes various functional applications and data processing of the processor by running the non-transitory software programs, instructions and modules stored in the memory 52, that is, the method for measuring and calculating the gate internal resistance of the power device in the above method embodiment is implemented.
The memory 52 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created by the processor 51, and the like. Further, the memory 52 may include high speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory 52 may optionally include memory located remotely from the processor 51, and these remote memories may be connected to the processor 51 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The one or more modules are stored in the memory 52 and when executed by the processor 51, perform the method of estimating the internal gate resistance of a power device as in the embodiments of fig. 1-9.
The details of the electronic device may be understood by referring to the corresponding descriptions and effects in the embodiments shown in fig. 1 to fig. 9, and are not described herein again.
Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.

Claims (10)

1. A method for measuring and calculating internal resistance of a grid electrode of a power device is characterized by comprising the following steps:
constructing a double-pulse test circuit, wherein the double-pulse test circuit comprises a power device to be tested, a driving power supply and a driving external resistor;
establishing a first calculation relation formula about the first end voltage and the grid internal resistance of the power device to be tested according to the driving voltage value of the driving power supply, the first preset resistance value of the driving external resistor, the first inter-electrode capacitance value of the power device to be tested and the first change rate of the first inter-electrode capacitance voltage, wherein the first change rate of the first inter-electrode capacitance voltage is the change rate of the first inter-electrode capacitance voltage during the Miller platform period;
changing the driving external resistance into a second preset resistance value, and establishing a second calculation relational expression about the first end voltage and the grid internal resistance of the power device to be tested according to the driving voltage value of the driving power supply, the second preset resistance value, the first inter-electrode capacitance value of the power device to be tested and a second change rate of the first inter-electrode capacitance voltage, wherein the second change rate of the first inter-electrode capacitance voltage is the change rate of the first inter-electrode capacitance voltage during the Miller platform period;
and calculating the resistance value of the grid internal resistance according to the first calculation relational expression and the second calculation relational expression.
2. The method for measuring and calculating the internal resistance of a gate of a power device according to claim 1,
the first rate of change of the first inter-electrode capacitance voltage is calculated by the following formula:
Figure FDA0003014524150000011
wherein the content of the first and second substances,
Figure FDA0003014524150000012
is a first rate of change, V, of the capacitance voltage between the first electrodesCE1The voltage of the second end of the power device to be tested when the driving external resistor is a first preset resistance value (t)b1，Vb1) And (t)a1，Va1) Is at t-VCE1Two coordinates during the period of the Miller platform selected on the curve;
the second rate of change of the first inter-electrode capacitance voltage is calculated by the following formula:
Figure FDA0003014524150000021
wherein the content of the first and second substances,
Figure FDA0003014524150000022
is a second rate of change, V, of the first inter-electrode capacitance voltageCE2The voltage of the second end of the power device to be tested when the driving external resistor is a second preset resistance value, (t)b2，Vb2) And (t)a2，Va2) Is at t-VCE2Two coordinates during the selected miller stage on the curve.
3. The method for measuring and calculating the internal resistance of a gate of a power device according to claim 2, wherein the first time difference and the second time difference are equal, and the first time difference is represented as tb1-ta1Said second time difference being denoted tb2-ta2。
4. The method according to claim 2, wherein the driving voltage value is a driving voltage value of an on process or a driving voltage value of an off process, and the rate of change of the first inter-electrode capacitance voltage during the miller plateau is a rate of change of the first inter-electrode capacitance voltage during the miller plateau is on or a rate of change of the first inter-electrode capacitance voltage during the miller plateau is off.
5. The method for measuring and calculating the internal resistance of a gate of a power device according to claim 4,
during the switching on of the miller platform, the first calculation relationship is represented by the following formula:
Figure FDA0003014524150000023
wherein, VGin,PIs the first terminal voltage, V, of the power device to be testedG,offFor the drive voltage value, R, of the drive power supply during the switching-on of the Miller platformext1Is the first predetermined resistance value, RintIs the internal resistance of the gate, CGCA first inter-electrode capacitance value of a power device to be tested;
the second calculation relationship is expressed by the following formula:
Figure FDA0003014524150000024
wherein R isext2Is the second preset resistance value;
during the off-period of the miller platform, the first calculation relationship is represented by the following formula:
Figure FDA0003014524150000031
wherein, VG,onThe driving voltage value of the driving power supply during the period of turning off the Miller platform;
the second calculation relationship is expressed by the following formula:
Figure FDA0003014524150000032
6. the method for measuring and calculating the internal resistance of the gate of the power device as claimed in claim 5, wherein the resistance value of the internal resistance of the gate is calculated by the following formula:
Figure FDA0003014524150000033
wherein, is Δ V1＝Vb1-Va1，ΔV2＝Vb2-Va2。
7. The method for measuring and calculating the internal resistance of the grid electrode of the power device as claimed in claim 1, wherein the power device to be measured is an IGBT.
8. An apparatus for measuring and calculating internal resistance of a gate of a power device, comprising:
the device comprises a construction module, a power supply module and a drive external resistor, wherein the construction module is used for constructing a double-pulse test circuit which comprises a power device to be tested, a drive power supply and a drive external resistor;
a first establishing module, configured to establish a first calculation relation regarding a first end voltage and a gate internal resistance of the power device to be tested according to a driving voltage value of the driving power supply, a first preset resistance value of the external driving resistor, a first inter-electrode capacitance value of the power device to be tested, and a first change rate of a first inter-electrode capacitance voltage, where the first change rate of the first inter-electrode capacitance voltage is a change rate of the first inter-electrode capacitance voltage during the miller plateau;
a second establishing module, configured to change the external driving resistance to a second preset resistance value, and establish a second calculation relation between the first terminal voltage of the power device to be tested and the internal gate resistance according to a driving voltage value of the driving power supply, the second preset resistance value, the first inter-electrode capacitance value of the power device to be tested, and a second change rate of the first inter-electrode capacitance voltage, where the second change rate of the first inter-electrode capacitance voltage is a change rate of the first inter-electrode capacitance voltage during the miller plateau;
and the calculation module is used for calculating the resistance value of the grid internal resistance according to the first calculation relational expression and the second calculation relational expression.
9. A computer-readable storage medium storing computer instructions for causing a computer to perform the method for estimating gate internal resistance of a power device according to any one of claims 1 to 7.
10. An electronic device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected with each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the method for measuring and calculating the gate internal resistance of a power device according to any one of claims 1 to 7.
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