CN110673010B - Method and device for measuring and calculating grid internal resistance of power semiconductor device - Google Patents

Method and device for measuring and calculating grid internal resistance of power semiconductor device Download PDF

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CN110673010B
CN110673010B CN201911037731.2A CN201911037731A CN110673010B CN 110673010 B CN110673010 B CN 110673010B CN 201911037731 A CN201911037731 A CN 201911037731A CN 110673010 B CN110673010 B CN 110673010B
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value
semiconductor device
power semiconductor
threshold voltage
driving
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CN110673010A (en
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孙帅
崔梅婷
陈中圆
陈艳芳
李翠
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Global Energy Interconnection Research Institute
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant

Abstract

The embodiment of the invention provides a method and a device for measuring and calculating grid internal resistance of a power semiconductor device, wherein the method comprises the steps of constructing an equivalent circuit model, setting a first preset resistance value and a second preset resistance value corresponding to a driving resistor, obtaining a driving voltage value corresponding to a driving power supply, an input capacitance value corresponding to a charging capacitor, a first turn-on delay value corresponding to the first preset resistance value and a second turn-on delay value corresponding to the second preset resistance value, utilizing a difference method to establish an equation expression about threshold voltage corresponding to the grid resistor, eliminating the threshold voltage as an intermediate quantity, further eliminating the need of measuring a threshold voltage parameter, solving the grid internal resistor only by two dynamic tests, and avoiding errors caused by inaccurate measurement of the threshold voltage, so that the measurement and calculation precision of the grid internal resistor is improved.

Description

Method and device for measuring and calculating grid internal resistance of power semiconductor device
Technical Field
The invention relates to the technical field of power electronic devices, in particular to a method and a device for measuring and calculating grid internal resistance of a power semiconductor device.
Background
The power semiconductor device is a power electronic device for high power in the aspect of power conversion and control circuits of power equipment, and therefore, the power semiconductor device is a core device in the power electronic device. With the rapid development of digital information technology, power Semiconductor devices are more and more widely applied, wherein a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET for short) is a Field Effect Transistor which can be widely used in analog circuits and digital circuits, so that if the MOSFET device is fully utilized, it is necessary to study the electrical characteristics of the MOSFET device, wherein the internal resistance of the gate of the MOSFET device belongs to one of important electrical characteristic parameters, the internal resistance of the gate of the MOSFET device affects the charging and discharging speed of the device, and the measurement of the internal resistance of the gate of the MOSFET device is helpful for the drive matching of the device.
At present, a driving voltage value, a threshold voltage value, an input capacitance value, a driving external resistance value and a switching-on delay value of the MOSFET device are generally measured by a measuring instrument in the switching-on process of the MOSFET device, and the gate internal resistance value of the MOSFET device is directly calculated based on a measuring formula of the MOSFET device.
Disclosure of Invention
The invention aims to overcome the defect of inaccurate measurement and calculation of the internal resistance of the grid in the prior art, and provides a method and a device for measuring the internal resistance of the grid of a power semiconductor device.
Therefore, the invention adopts the following technical scheme:
according to a first aspect, an embodiment of the present invention provides a method for measuring and calculating gate internal resistance of a power semiconductor device, including the following steps:
constructing a charging equivalent circuit model of a power semiconductor device to be tested, wherein the charging equivalent circuit model comprises the power semiconductor device to be tested, a driving resistor, a grid resistor, a charging capacitor and a driving power supply;
setting a first preset resistance value and a second preset resistance value respectively corresponding to the driving resistor according to the charging equivalent circuit model;
acquiring a driving voltage value corresponding to the driving power supply, an input capacitance value corresponding to the charging capacitor, a first turn-on delay value corresponding to the first preset resistance value and a second turn-on delay value corresponding to the second preset resistance value;
establishing a first threshold voltage calculation relation related to the grid resistance according to the driving voltage value, the input capacitance value, the first preset resistance value and the first turn-on delay value;
establishing a second threshold voltage calculation relation related to the grid resistance according to the driving voltage value, the input capacitance value, the second preset resistance value and the second turn-on delay value;
and calculating the difference value of the first threshold voltage calculation relational expression and the second threshold voltage calculation relational expression to obtain the internal resistance value of the grid corresponding to the grid resistor.
With reference to the first aspect, in a first embodiment of the first aspect, the input capacitance value is calculated by the following formula:
Ciss＝CGS+CGD；
said C isissIs the input capacitance value, CGSThe capacitance value between the first electrodes of the power semiconductor device to be tested is obtained; said C isGDAnd the capacitance value is the second interelectrode capacitance value of the power semiconductor device to be tested.
With reference to the first aspect, in a second implementation manner of the first aspect, the first threshold voltage calculation relation is as follows:
Figure GDA0003300291990000031
wherein, Vth1Is a first threshold voltage value, VG,onIs the value of the driving voltage, tdon1For said first opening delay value, CissFor said input capacitance value, Rext1Is the first predetermined resistance value, RintIs the gate internal resistance value.
With reference to the first aspect, in a third implementation manner of the first aspect, the second threshold voltage calculation relation is as follows:
Figure GDA0003300291990000032
wherein, Vth2Is a second threshold valuePressure value, VG,onIs the value of the driving voltage, tdon2For said second value of opening delay, Rext2Is the second predetermined resistance value, RintIs the gate internal resistance value.
With reference to the first aspect or any implementation manner of the first aspect, in a fourth implementation manner of the first aspect, the power semiconductor device to be tested includes a MOSFET chip.
According to a second aspect, an embodiment of the present invention provides an apparatus for measuring and calculating gate internal resistance of a power semiconductor device, including:
the device comprises a building module, a charging module and a charging module, wherein the building module is used for building a charging equivalent circuit model of a power semiconductor device to be tested, and the charging equivalent circuit model comprises the power semiconductor device to be tested, a driving resistor, a grid resistor, a charging capacitor and a driving power supply;
the setting module is used for setting a first preset resistance value and a second preset resistance value which correspond to the driving resistor respectively according to the charging equivalent circuit model;
an obtaining module, configured to obtain a driving voltage value corresponding to the driving power supply, an input capacitance value corresponding to the charging capacitor, a first turn-on delay value corresponding to the first preset resistance value, and a second turn-on delay value corresponding to the second preset resistance value;
a first establishing module, configured to establish a first threshold voltage calculation relation with respect to the gate resistor according to the driving voltage value, the input capacitance value, the first preset resistance value, and the first turn-on delay value;
a second establishing module, configured to establish a second threshold voltage calculation relation with respect to the gate resistor according to the driving voltage value, the input capacitance value, the second preset resistance value, and the second turn-on delay value;
and the calculation module is used for calculating a difference value between the first threshold voltage calculation relational expression and the second threshold voltage calculation relational expression to obtain the gate internal resistance value corresponding to the gate resistor.
With reference to the second aspect, in the first embodiment of the second aspect, the input capacitance value is calculated by the following formula:
Ciss＝CGS+CGD；
said C isissIs the input capacitance, CGSThe capacitance value between the first electrodes of the power semiconductor device to be tested is obtained; said C isGDAnd the capacitance value is the second interelectrode capacitance value of the power semiconductor device to be tested.
With reference to the second aspect, in a second implementation manner of the second aspect, the power semiconductor device to be tested comprises a MOSFET chip.
With reference to the second aspect, in a third embodiment of the second aspect, the first threshold voltage calculation relation is as follows:
Figure GDA0003300291990000051
wherein, Vth1Is a first threshold voltage value, VG,onIs the value of the driving voltage, tdon1For said first opening delay value, CissFor said input capacitance value, Rext1Is the first predetermined resistance value, RintIs the gate internal resistance value.
With reference to the second aspect, in a fourth embodiment of the second aspect, the second threshold voltage calculation relation is as follows:
Figure GDA0003300291990000052
wherein, Vth2Is a second threshold voltage value, VG,onIs the value of the driving voltage, tdon2For said second value of opening delay, Rext2Is the second predetermined resistance value, RintIs the gate internal resistance value.
According to a third aspect, an embodiment of the present invention provides a computer apparatus, including:
at least one processor and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, and the processor executes the instructions to perform the steps of the method for measuring and calculating the gate internal resistance of a power semiconductor device according to the first aspect or any of the embodiments of the first aspect.
According to a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the steps of the method for measuring and calculating the gate internal resistance of a power semiconductor device described in the first aspect or any of the embodiments of the first aspect.
The technical scheme of the invention has the following beneficial effects:
the embodiment of the invention provides a method and a device for measuring and calculating grid internal resistance of a power semiconductor device, wherein the method comprises the steps of constructing an equivalent circuit model, setting a first preset resistance value and a second preset resistance value corresponding to a driving resistor, obtaining a driving voltage value corresponding to a driving power supply, an input capacitance value corresponding to a charging capacitor, a first turn-on delay value corresponding to the first preset resistance value and a second turn-on delay value corresponding to the second preset resistance value, utilizing a difference method to establish an equation expression about threshold voltage corresponding to the grid resistor, eliminating the threshold voltage as an intermediate quantity, further eliminating the need of measuring a threshold voltage parameter, solving the grid internal resistor only by two dynamic tests, and avoiding errors caused by inaccurate measurement and calculation of the threshold voltage, so that the measurement and calculation precision of the grid internal resistor is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of a calculation method of a specific example of a method of measuring the internal resistance of a gate of a power semiconductor device in the embodiment of the present invention;
fig. 2 is a schematic diagram of a MOSFET turn-on circuit of a specific example of a method for measuring the internal resistance of a gate of a power semiconductor device in the embodiment of the present invention;
FIG. 3 is a simplified MOSFET turn-on model illustrating a specific example of a method for measuring the internal gate resistance of a power semiconductor device according to an embodiment of the present invention;
fig. 4 is a double pulse test circuit of a specific example of the apparatus for measuring the internal resistance of the gate of the power semiconductor device in the embodiment of the present invention;
fig. 5 is a MOSFET turn-on waveform of a specific example of the apparatus for measuring the internal resistance of the gate of the power semiconductor device in the embodiment of the present invention;
fig. 6 is a block diagram showing a specific example of the apparatus for measuring the internal resistance of the gate of the power semiconductor device in the embodiment of the present invention;
fig. 7 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1
The embodiment of the invention provides a method for measuring and calculating the internal resistance of a grid electrode of a power semiconductor device, as shown in figure 1, comprising the following steps:
step S1: and constructing a charging equivalent circuit model of the power semiconductor device to be tested, wherein the charging equivalent circuit model comprises the power semiconductor device to be tested, a driving resistor, a grid resistor, a charging capacitor and a driving power supply.
Specifically, the power semiconductor device to be tested in the embodiment of the present invention may be a MOSFET chip, and may also be an IGBT chip, without being limited thereto, and the power semiconductor device to be tested is preferably a MOSFET chip in this embodiment. The charging equivalent circuit model is an equivalent circuit formed by a double-pulse test of the MOSFET chip in an on state. As shown in FIG. 2, the circuit structure is formed by a double pulse test of the MOSFET chip in the ON state, in FIG. 2, N is the MOSFET chip, and the capacitor CGDIs the capacitance between the gate and the drain of the MOSFET chip, CGSIs the capacitance between gate and source, CDSIs the capacitance between the source and drain, RextIs an external drive resistance of the MOSFET chip, RintIs the driving internal resistance of the MOSFET chip, VG represents the driving power supply, VG,To turn off the drive voltage, VG,onTo turn on the driving voltage, D denotes a drain of the MOSFET chip, G denotes a gate of the MOSFET chip, S denotes a source of the MOSFET chip, and SP denotes a double throw switch.
In fig. 2, the direction of the arrow is the driving current direction of the MOSFET chip at the turn-on instant, and the dotted circle is the charging equivalent circuit model of the MOSFET chip. Due to the capacitance C between the gate and the sourceGSGreater than gate-drain capacitance CGDTherefore, most of the gate current flows to C during the on-delay periodGS. In fig. 5, the MOSFET is typically turned on. The output voltage V is output due to the turn-on delay and the current rising stageDSDo not change, therefore CGS、CGDThe voltage change amounts of the two capacitors are equal. Due to the input capacitance Ciss＝CGS+CGDThe model in the on-delay phase may be further equivalent to a charging equivalent circuit model as shown in fig. 3. Dividing the gate voltage into gate voltages V based on whether the internal resistance voltage is includedGGAnd the voltage V in the gateGSi，VGSFor driving voltage, V, including internal resistance of the chipGSiIs the actual driving voltage without the chip internal resistance.
Step S2: and setting a first preset resistance value and a second preset resistance value which respectively correspond to the driving resistor according to the charging equivalent circuit model.
In FIG. 3, in the equivalent charging circuit model, the driving resistor is the external driving resistor of the MOSFET chip, and the driving resistor is represented by RextThe gate resistance is expressed as R, the internal gate resistance of the MOSFET chipintAnd (4) showing.
Specifically, as shown in fig. 4, a charging equivalent circuit model is constructed by a typical double pulse test circuit, in which V isDCIs the bus voltage, L sigma is the stray inductance, LloadIs a load inductance, DFIs a freewheeling diode, VG,on，VG,offTo the value of the drive voltage, RextFor driving external resistance, RintIs the gate internal resistance.
The first step is as follows: matching appropriate parameters for a driving circuit and a main loop element of the charging equivalent circuit model;
the second step is that: at a driving resistance of Rext1Under the condition, the rise of the current value from the starting point of the driving voltage pulse to the measured value is ICD(ICDGreater than 0, less than nominal) time, denoted t 1;
the third step: changing the drive resistance to R onlyext2Measuring the rise from the starting point of the driving voltage pulse to the current value as ICD(ICDTo be guaranteed to coincide with the second step) is recorded as t 2. Specifically, in FIG. 3, in the charging equivalent circuit model, if different external driving resistors R are adopted for the same MOSFET chip to be testedext1，Rext2R is a hydrogen atomext1Is the first predetermined resistance value of the above, Rext2For the second predetermined resistance, the model shown in FIG. 3 will correspond to a different oneTime constant τ of1，τ2Two delay parameters t will be obtaineddon1，tdon2。
Step S3: and acquiring a driving voltage value corresponding to the driving power supply, an input capacitance value corresponding to the charging capacitor, a first turn-on delay value corresponding to the first preset resistance value and a second turn-on delay value corresponding to the second preset resistance value.
In fig. 3, the driving power source VG has a corresponding driving voltage value VG,onThe input capacitance value corresponding to the charging capacitor is CissThe time constant corresponding to the first preset resistance value is tau1The time constant corresponding to the second predetermined resistance value is tau2。
In particular, a first time constant τ1And a second time constant τ2The calculation can be performed by a direct calculation method, and in fig. 3, after the switch is switched, the gate starts to be charged by the driving power source VG, and the voltage V in the gate starts to be calculatedGSiExpressed by formula (1):
Figure GDA0003300291990000101
wherein the time constant τ is calculated by equation (2):
τ＝Ciss(Rext+Rint) (2)；
in the prior art, based on the direct calculation method, when the gate voltage reaches the threshold voltage V on the basis of the direct calculation methodthAnd (4) conducting the MOSFET chip and finishing the turn-on delay process. As shown in equations (1) and (2), the expression of the gate internal resistance can be represented by equation (3):
Figure GDA0003300291990000111
wherein, VthIs the threshold voltage, V, of the MOSFET chipG,onIs the driving voltage of the MOSFET chip, CissFor input capacitance value, RintIs the internal resistance of the gate, RextTo drive the external resistance, tdonThe turn-on time of the MOSFET chip is delayed.
Therefore, in the prior art, the gate internal resistance is measured and calculated by using a direct calculation method, in the measurement and calculation process, the threshold voltage of the MOSFET chip is considered, but the threshold voltage changes rapidly in the measurement process, so that the threshold voltage is difficult to ensure to be accurately measured, and finally the gate internal resistance of the MOSFET chip is measured and calculated inaccurately. The embodiment of the invention is further improved based on the driving voltage value corresponding to the driving power supply, the input capacitance value corresponding to the charging capacitor, the first turn-on delay value corresponding to the first preset resistance value and the second turn-on delay value corresponding to the second preset resistance value.
The input capacitance value in the above is calculated by the following formula (4):
Ciss＝CGS+CGD (4)；
in FIG. 3, CissTo input a capacitance value, CGSA first inter-electrode capacitance value of the power semiconductor device to be tested, the first inter-electrode capacitance value being the gate-source inter-electrode capacitance of the MOSFET chip, CGDAnd the second inter-electrode capacitance value is the second inter-electrode capacitance value of the power semiconductor device to be tested, and the second inter-electrode capacitance value is the gate-drain capacitance value of the MOSFET chip.
Step S4: and establishing a first threshold voltage calculation relation related to the grid resistance according to the driving voltage value, the input capacitance value, the first preset resistance value and the first turn-on delay value.
In one embodiment, in the execution of step S4, the first threshold voltage is calculated by equation (5):
Figure GDA0003300291990000121
wherein, Vth1Is a first threshold voltage value, VG,onIs a value of a driving voltage, tdon1For the first opening of a delay value, CissIs an input capacitance value, Rext1Is a first predetermined resistance value, RintIs the gate internal resistance value.
Step S5: and establishing a second threshold voltage calculation relation related to the grid resistance according to the driving voltage value, the input capacitance value, a second preset resistance value and a second turn-on delay value.
In one embodiment, in the execution of step S5, the second threshold voltage is calculated by equation (6):
Figure GDA0003300291990000122
wherein, Vth2Is a second threshold voltage value, VG,onIs the value of the driving voltage, tdon2For said second value of opening delay, Rext2Is the second predetermined resistance value, RintIs the gate internal resistance value.
Step S6: and calculating the difference value of the first threshold voltage calculation relational expression and the second threshold voltage calculation relational expression to obtain the internal resistance value of the grid corresponding to the grid resistance.
In an embodiment, the step S6 is executed, specifically:
the gate internal resistance R can be calculated by combining the above formulas (5) and (6)intSpecifically, the following formula (7) shows:
Figure GDA0003300291990000131
wherein R isintIs the internal resistance of the gate, tdon1For the first opening of the delay value, tdon2For the second switching-on delay value, Rext1Is a first predetermined resistance value, Rext2Is a second predetermined resistance value.
In summary, in the embodiments of the present invention, different driving resistors are used, and a first threshold voltage calculation relation is established by combining the driving voltage value, the input capacitance value, the first preset resistance value and the first turn-on delay value in the on state of the power semiconductor device to be tested based on the double-pulse dynamic test, and a second threshold voltage calculation relation is established by combining the driving voltage value, the input capacitance value, the second preset resistance value and the second turn-on delay valueAnd calculating the difference between the two different threshold voltages by combining the two different threshold voltage calculation relations, calculating the internal resistance of the grid of the power semiconductor device to be measured, and solving the threshold voltage V in the simultaneous difference equationthThe threshold voltage value is eliminated as an intermediate quantity, the threshold voltage value is not required to be measured, and errors caused by inaccurate threshold voltage measurement and calculation are avoided.
Example 2
Embodiments of the present invention provide a method for measuring and calculating the gate internal resistance of a power semiconductor device, by performing steps S1 to S6 in embodiment 1 as follows.
In the present embodiment, after the turn-on delay, in the current rising stage, based on the charging equivalent circuit model in fig. 3, the time for the current to rise to the rated value by 10% (in the national standard, the time from the start point of the voltage pulse at the input end to the time for the current to rise to 10% is defined as the turn-on delay td (on)) is selected as the reference time, and any other same current value may also be selected as the reference time. Using different driving external resistances Rext1，Rext2The time from the starting point of the gate input voltage pulse to the time when the current rises to a certain reference value in the two dynamic tests is t1 and t2 respectively. The expression for the internal resistance can be improved as formula (8):
Figure GDA0003300291990000141
therefore, threshold voltage parameters are not needed any more, the internal resistance of the grid electrode can be solved only by dynamic tests on two sides, the threshold voltage is not needed to be measured, and errors caused by inaccurate measurement of the threshold voltage are avoided.
Example 3
Embodiments of the present invention provide a method for measuring and calculating the gate internal resistance of a power semiconductor device, by performing steps S1 to S6 in embodiment 1 as follows.
Figure GDA0003300291990000142
In this implementationIn fig. 4, a circuit for forming a charging equivalent model by a double pulse test is shown, the charging equivalent model being formed by a bus voltage source VDCStray inductance LσMOSFET chip, freewheeling diode DFA load inductor LloadDriving external resistor RextDriving internal resistance RintA driving voltage value VG,on，VG,And a double throw switch SP. To verify the effectiveness of the method for calculating the gate internal resistance of the MOSFET chip in step S1 to step S6 in embodiment 1, simulation verification is performed in the following manner, and the simulation parameters are set as follows:
VDD＝800V，VGS＝-5/20V，ID＝40V，Rext1＝12Ω，Rext2＝24Ω，
Rint＝6.89Ω，Ciss＝1nF
the test procedure was as follows:
the first step is as follows: matching appropriate parameters for the drive circuit and the main loop element;
the second step is that: at a driving resistance of Rext1Under the condition, the rise of the current value from the starting point of the driving voltage pulse to the measured value is ICD(ICDGreater than 0, less than nominal) time, denoted t1；
The third step: at a driving resistance of Rext2Under the condition, the rise of the current value from the starting point of the driving voltage pulse to the measured value is ICD(ICDGreater than 0, less than nominal) time, denoted t2；
Through the two simulated waveforms of the grid internal voltage and the output current, the grid internal voltage (7.56V and 7.57V) is the same when the output current rises to 20% rated value (7.99A and 8A) under different driving external resistances (12 omega and 24 omega). Therefore, the time taken when the current rises to 20% of the rated value is recorded as t1＝143.2ns，t2＝233.5ns。
R is to beext1＝12Ω，Rext2＝24Ω，t1＝143.2ns，t2Substitution of 233.5ns into equation (7) results,
Figure GDA0003300291990000151
TABLE 1
Internal resistance set value of grid Calculated value of internal resistance of grid Error rate
6.89Ω 7.03Ω 2％
As can be seen from Table 1, the set value of the model internal resistance is 6.89 omega, the simulation calculation result of the test method is 7.03 omega, and the error rate is only 2%, thus proving the effectiveness of the method.
The method for measuring the grid internal resistance of the power semiconductor device belongs to a simpler measuring and calculating scheme, has less test data, easy realization of test conditions and simple test steps, only needs two dynamic tests, avoids errors caused by inaccurate measurement of threshold voltage, and has higher practical value.
Example 4
An embodiment of the present invention provides a computer-readable storage medium, including: at least one processor and a memory communicatively coupled to the at least one processor, wherein the memory stores instructions executable by the at least one processor, and the processor implements the steps of the method of embodiment 1 when executing the instructions. The computer readable storage medium further stores a first preset resistance value and a second preset resistance value, a driving voltage value, an input capacitance value, a first on-delay value corresponding to the first preset resistance value and a second on-delay value corresponding to the second preset resistance value, and the like. The storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a Hard Disk (Hard Disk Drive, abbreviated as HDD), a Solid State Drive (SSD), or the like; the storage medium may also comprise a combination of memories of the kind described above.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware related to instructions of a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a Random Access Memory (RAM), or the like.
Example 6
The embodiment of the invention provides computer equipment. As shown in fig. 7, the apparatus includes a memory 720, a processor 710 and a computer program stored in the memory 720 and running on the processor 710, and the processor 710 implements the steps of the method in embodiment 1 when executing the program.
Fig. 7 is a schematic diagram of a hardware structure of a server for performing a processing method for list item operations according to an embodiment of the present invention, as shown in fig. 7, the server includes one or more processors 710 and a memory 720, and one processor 710 is taken as an example in fig. 7.
The server executing the processing method of the list item operation may further include: an input device 730 and an output device 740.
The processor 710, the memory 720, the input device 730, and the output device 740 may be connected by a bus or other means, such as the bus connection in fig. 7.
Processor 710 may be a Central Processing Unit (CPU). The Processor 710 may also be other general purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, or any combination thereof.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.

Claims (8)

1. A method for measuring and calculating the internal resistance of a grid electrode of a power semiconductor device is characterized by comprising the following steps:
constructing a charging equivalent circuit model of a power semiconductor device to be tested, wherein the charging equivalent circuit model comprises the power semiconductor device to be tested, a driving resistor, a grid resistor, a charging capacitor and a driving power supply;
setting a first preset resistance value and a second preset resistance value respectively corresponding to the driving resistor according to the charging equivalent circuit model;
acquiring a driving voltage value corresponding to the driving power supply, an input capacitance value corresponding to the charging capacitor, a first turn-on delay value corresponding to the first preset resistance value and a second turn-on delay value corresponding to the second preset resistance value;
establishing a first threshold voltage calculation relation related to the grid resistance according to the driving voltage value, the input capacitance value, the first preset resistance value and the first turn-on delay value; the first threshold voltage calculation relation is as follows:
Figure FDA0003336611160000011
wherein, Vth1Is a first threshold voltage value, VG，onIs said driveDynamic voltage value, tdon1For said first opening delay value, CissFor said input capacitance value, Rext1Is the first predetermined resistance value, RintIs the gate internal resistance value;
establishing a second threshold voltage calculation relation related to the grid resistance according to the driving voltage value, the input capacitance value, the second preset resistance value and the second turn-on delay value; the second threshold voltage calculation relation is as follows:
Figure FDA0003336611160000021
wherein, Vth2Is a second threshold voltage value, VG，onIs the value of the driving voltage, tdon2For said second value of opening delay, Rext2Is the second predetermined resistance value, RintIs the gate internal resistance value;
and calculating the difference value of the first threshold voltage calculation relational expression and the second threshold voltage calculation relational expression to obtain the internal resistance value of the grid corresponding to the grid resistor.
2. The method for measuring and calculating the internal gate resistance of a power semiconductor device according to claim 1, wherein the input capacitance value is calculated by the following formula:
Ciss＝CGS+CGD；
said C isissIs the input capacitance value, CGSThe capacitance value between the first electrodes of the power semiconductor device to be tested is obtained; said C isGDAnd the capacitance value is the second interelectrode capacitance value of the power semiconductor device to be tested.
3. The method for measuring and calculating the gate internal resistance of a power semiconductor device according to any one of claims 1-2, wherein the power semiconductor device to be tested comprises a MOSFET chip.
4. An apparatus for measuring gate internal resistance of a power semiconductor device, comprising:
the device comprises a building module, a charging module and a charging module, wherein the building module is used for building a charging equivalent circuit model of a power semiconductor device to be tested, and the charging equivalent circuit model comprises the power semiconductor device to be tested, a driving resistor, a grid resistor, a charging capacitor and a driving power supply;
the setting module is used for setting a first preset resistance value and a second preset resistance value which correspond to the driving resistor respectively according to the charging equivalent circuit model;
an obtaining module, configured to obtain a driving voltage value corresponding to the driving power supply, an input capacitance value corresponding to the charging capacitor, a first turn-on delay value corresponding to the first preset resistance value, and a second turn-on delay value corresponding to the second preset resistance value;
a first establishing module, configured to establish a first threshold voltage calculation relation with respect to the gate resistor according to the driving voltage value, the input capacitance value, the first preset resistance value, and the first turn-on delay value; the first threshold voltage calculation relation is as follows:
Figure FDA0003336611160000031
wherein, Vth1Is a first threshold voltage value, VG，onIs the value of the driving voltage, tdon1For said first opening delay value, CissFor said input capacitance value, Rext1Is the first predetermined resistance value, RintIs the gate internal resistance value;
a second establishing module, configured to establish a second threshold voltage calculation relation with respect to the gate resistor according to the driving voltage value, the input capacitance value, the second preset resistance value, and the second turn-on delay value; the second threshold voltage calculation relation is as follows:
Figure FDA0003336611160000032
wherein, Vth2Is a second threshold voltage value, VG，onIs the value of the driving voltage, tdon2For said second value of opening delay, Rext2Is the second predetermined resistance value, RintIs the gate internal resistance value;
and the calculation module is used for calculating a difference value between the first threshold voltage calculation relational expression and the second threshold voltage calculation relational expression to obtain the gate internal resistance value corresponding to the gate resistor.
5. The apparatus for measuring gate internal resistance of a power semiconductor device according to claim 4, wherein the input capacitance is calculated by the following formula:
Ciss＝CGS+CGD；
said C isissIs the input capacitance value, CGSThe capacitance value between the first electrodes of the power semiconductor device to be tested is obtained; said C isGDAnd the capacitance value is the second interelectrode capacitance value of the power semiconductor device to be tested.
6. The apparatus for measuring gate internal resistance of a power semiconductor device according to any one of claims 4 to 5, wherein the power semiconductor device under test comprises a MOSFET chip.
7. A computer device, comprising:
at least one processor and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, and the processor executes the instructions to perform the steps of the method for estimating the gate internal resistance of a power semiconductor device according to any one of claims 1 to 3.
8. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of estimating the internal gate resistance of a power semiconductor device according to any one of claims 1 to 3.
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CN112213562A (en) * 2020-09-23 2021-01-12 龙腾半导体股份有限公司 Method for measuring and calculating internal resistance of grid electrode of power semiconductor device
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CN114019241A (en) * 2021-11-11 2022-02-08 江苏科技大学 Method and device for determining resistance value of resistor in power device driving circuit

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03218217A (en) * 1990-01-23 1991-09-25 Mitsubishi Electric Corp Power source circuit with rush current prevention circuit
CN102298110A (en) * 2011-08-29 2011-12-28 中国科学院计算技术研究所 Method and device for measuring electric property of solar cell
CN102608508A (en) * 2011-12-20 2012-07-25 西交利物浦大学 Automatic real-time pulse measuring device and method for threshold voltage parameter of field-effect transistor
CN103595402A (en) * 2013-11-18 2014-02-19 四川和芯微电子股份有限公司 High-accuracy oscillator
CN106059552A (en) * 2016-05-27 2016-10-26 西安电子科技大学 MOSFET (metal oxide semiconductor field effect transistor) switching dynamic characteristic-based driving circuit
CN106896307A (en) * 2017-01-18 2017-06-27 浙江大学 A kind of modeling method of silicon carbide MOSFET on-resistance characteristics
CN206292350U (en) * 2016-12-29 2017-06-30 江苏中科君芯科技有限公司 The IGBT test circuits of resistance, electric capacity continuously adjustabe
CN107064767A (en) * 2016-12-29 2017-08-18 江苏中科君芯科技有限公司 The IGBT test circuits of resistance, electric capacity continuously adjustabe
CN107342759A (en) * 2017-01-17 2017-11-10 青岛青铜剑电子技术有限公司 A kind of digital intelligent IGBT driving methods and its system
CN108267643A (en) * 2017-12-26 2018-07-10 全球能源互联网研究院有限公司 A kind of inductance extraction method and device based on IGBT device
CN108279333A (en) * 2017-12-26 2018-07-13 全球能源互联网研究院有限公司 A kind of inductance extraction method and device based on IGBT device
CN108768367A (en) * 2018-06-07 2018-11-06 重庆大学 SiC MOSFET driving circuits based on gate boost
CN110048699A (en) * 2019-05-21 2019-07-23 哈尔滨工业大学 A kind of gate driving circuit inhibiting the bridge arm crosstalk of GaN half-bridge module

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03218217A (en) * 1990-01-23 1991-09-25 Mitsubishi Electric Corp Power source circuit with rush current prevention circuit
CN102298110A (en) * 2011-08-29 2011-12-28 中国科学院计算技术研究所 Method and device for measuring electric property of solar cell
CN102608508A (en) * 2011-12-20 2012-07-25 西交利物浦大学 Automatic real-time pulse measuring device and method for threshold voltage parameter of field-effect transistor
CN103595402A (en) * 2013-11-18 2014-02-19 四川和芯微电子股份有限公司 High-accuracy oscillator
CN106059552A (en) * 2016-05-27 2016-10-26 西安电子科技大学 MOSFET (metal oxide semiconductor field effect transistor) switching dynamic characteristic-based driving circuit
CN206292350U (en) * 2016-12-29 2017-06-30 江苏中科君芯科技有限公司 The IGBT test circuits of resistance, electric capacity continuously adjustabe
CN107064767A (en) * 2016-12-29 2017-08-18 江苏中科君芯科技有限公司 The IGBT test circuits of resistance, electric capacity continuously adjustabe
CN107342759A (en) * 2017-01-17 2017-11-10 青岛青铜剑电子技术有限公司 A kind of digital intelligent IGBT driving methods and its system
CN106896307A (en) * 2017-01-18 2017-06-27 浙江大学 A kind of modeling method of silicon carbide MOSFET on-resistance characteristics
CN108267643A (en) * 2017-12-26 2018-07-10 全球能源互联网研究院有限公司 A kind of inductance extraction method and device based on IGBT device
CN108279333A (en) * 2017-12-26 2018-07-13 全球能源互联网研究院有限公司 A kind of inductance extraction method and device based on IGBT device
CN108768367A (en) * 2018-06-07 2018-11-06 重庆大学 SiC MOSFET driving circuits based on gate boost
CN110048699A (en) * 2019-05-21 2019-07-23 哈尔滨工业大学 A kind of gate driving circuit inhibiting the bridge arm crosstalk of GaN half-bridge module

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Stray Impedance Measurement and Improvement of High-Power IGCT Gate Driver Units;Zhengyu Chen et al.;《IEEE TRANSACTIONS ON POWER ELECTRONICS》;20190731;第34卷(第7期);第6639-6647页 *

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