CN112558342B - Simulation system and simulation method of pixel circuit - Google Patents
Simulation system and simulation method of pixel circuit Download PDFInfo
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- CN112558342B CN112558342B CN202011539020.8A CN202011539020A CN112558342B CN 112558342 B CN112558342 B CN 112558342B CN 202011539020 A CN202011539020 A CN 202011539020A CN 112558342 B CN112558342 B CN 112558342B
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- 238000004088 simulation Methods 0.000 title claims abstract description 103
- 238000000034 method Methods 0.000 title claims abstract description 11
- 239000003990 capacitor Substances 0.000 claims abstract description 79
- 239000010409 thin film Substances 0.000 claims description 20
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 31
- 238000005516 engineering process Methods 0.000 abstract description 11
- 230000003071 parasitic effect Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Mathematical Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal (AREA)
Abstract
The invention provides a simulation system of a pixel circuit, which comprises a plurality of scanning lines, a plurality of data lines and a plurality of patch cords; the plurality of scanning lines are mutually spaced and extend along a first direction, the plurality of data lines are mutually spaced and extend along a second direction, and the plurality of scanning lines and the plurality of data lines are in insulating intersection so as to correspondingly define a plurality of sub-pixel areas; the plurality of patch cords are mutually spaced and extend along the second direction, and each scanning line is correspondingly and electrically connected with at least one patch cord so as to transmit corresponding grid driving signals; each transfer line comprises a plurality of transfer sub-sections, each transfer sub-section corresponds to one sub-pixel area, and every two adjacent transfer sub-sections are electrically connected through the first resistor-capacitor module. The simulation system provided by the invention is close to an actual pixel circuit In the liquid crystal display panel by adopting the GCOF In Source technology, so that a simulation result obtained by simulating the pixel circuit based on the simulation system is more accurate and reliable. The invention also provides a simulation method of the pixel circuit.
Description
Technical Field
The invention relates to the technical field of display, in particular to a simulation system and a simulation method of a pixel circuit.
Background
In order to make the liquid crystal display panel have a narrower frame, a technology of integrating a gate driving function into a Source side flip chip film (Gate Chip On Flex In Source, GCOF In Source) is often used to drive a pixel circuit In the liquid crystal display panel instead of a conventional technology of integrating a gate driving function into an array substrate (Gate driver On Array, GOA).
Before fabricating a liquid crystal display panel, modeling simulation needs to be performed on a pixel circuit In the liquid crystal display panel, however, until now, no modeling simulation scheme suitable for a pixel circuit employing GCOF In Source technology has been available, and therefore, it is highly desirable to provide a modeling simulation scheme suitable for a pixel circuit employing GCOF In Source technology.
Disclosure of Invention
Therefore, it is necessary to provide a simulation system and a simulation method for a pixel circuit, so as to solve the problem that the prior art does not have a modeling simulation scheme suitable for the pixel circuit adopting the GCOF In Source technology.
In a first aspect, the present invention provides a simulation system for a pixel circuit, including:
a plurality of scanning lines, a plurality of data lines and a plurality of patch cords; wherein,
the plurality of scanning lines are mutually spaced and extend along a first direction, the plurality of data lines are mutually spaced and extend along a second direction, and the plurality of scanning lines and the plurality of data lines are in insulating intersection so as to correspondingly define a plurality of sub-pixel areas;
the plurality of patch cords are mutually spaced and extend along the second direction, and each scanning line is correspondingly and electrically connected with at least one patch cord so as to transmit corresponding grid driving signals;
each patch cord comprises a plurality of patch sub-segments, each patch sub-segment corresponds to one sub-pixel area, and every two adjacent patch sub-segments are electrically connected through a first resistor-capacitor module.
In some embodiments, each scan line includes a plurality of scan subsections, each scan subsection corresponds to one sub-pixel region, and a second resistance-capacitance module is disposed between every two adjacent scan subsections and is electrically connected through the second resistance-capacitance module.
In some embodiments, each patch cord corresponds to one of the data lines, and each patch cord is located on the same side of the corresponding data line.
In some embodiments, a thin film transistor is disposed in each sub-pixel region, a gate of the thin film transistor is electrically connected to the scan line defining the sub-pixel region, a source of the thin film transistor is electrically connected to the data line defining the sub-pixel region, a drain of the thin film transistor is electrically connected to a pixel electrode terminal, and the pixel electrode terminal is configured to receive an externally input pixel voltage.
In some embodiments, a twenty-first capacitor is further disposed in each sub-pixel area, one end of the twenty-first capacitor is electrically connected to the pixel electrode terminal in the sub-pixel area, and the other end of the twenty-first capacitor is electrically connected to the patch cord corresponding to the data line defining the sub-pixel area.
In some embodiments, a seventh capacitor is further disposed between every two adjacent sub-pixel regions in each row of the sub-pixel regions, one end of the seventh capacitor is electrically connected to the patch cord corresponding to the data line defining one of the sub-pixel regions, and the other end of the seventh capacitor is electrically connected to the pixel electrode terminal in the other sub-pixel region.
In some embodiments, a third capacitor is further disposed between every two adjacent sub-pixel regions in each row of the sub-pixel regions, one end of the third capacitor is electrically connected to the patch cord corresponding to the data line defining one of the sub-pixel regions, and the other end of the third capacitor is electrically connected to the data line defining the other sub-pixel region.
In some embodiments, a fourth capacitor is further disposed in each sub-pixel area, one end of the fourth capacitor is electrically connected to the data line defining the sub-pixel area, and the other end of the fourth capacitor is electrically connected to the pixel electrode terminal in the sub-pixel area.
In some embodiments, a first capacitor, a fifth capacitor and a sixth capacitor are further disposed in each of the sub-pixel regions; one end of the first capacitor is electrically connected with the grid electrode of the thin film transistor in the sub-pixel area, and the other end of the first capacitor is electrically connected with the pixel electrode terminal in the sub-pixel area; one end of the fifth capacitor is electrically connected with the pixel electrode terminal in the sub-pixel area, and the other end of the fifth capacitor is electrically connected with a first common electrode terminal, and the first common electrode terminal is used for receiving a first common voltage input from the outside; one end of the sixth capacitor is electrically connected with the pixel electrode terminal in the sub-pixel area, and the other end of the sixth capacitor is connected with a second common electrode terminal, and the second common electrode terminal is used for receiving an externally input second common voltage.
In a second aspect, the present invention provides a method for simulating a pixel circuit, including:
providing the simulation system;
the pixel circuit is simulated by inputting gate driving signals to a plurality of patch cords in the simulation system, inputting source driving signals to a plurality of data lines in the simulation system, inputting pixel voltages to all pixel electrode terminals in the simulation system, inputting first common voltages to all first common electrode terminals in the simulation system, and inputting second common voltages to all second common electrode terminals in the simulation system.
The arrangement of the scanning line, the data line and the patch cord In the simulation system of the pixel circuit completely accords with the design rule of the pixel circuit adopting the GCOF In Source technology, and the load of connecting lines In the actual pixel circuit of the liquid crystal display panel at different positions is considered, and a plurality of first resistance-capacitance modules are arranged In the connecting lines of the simulation system, so that the simulation system obtained by modeling is more close to the actual pixel circuit In the liquid crystal display panel, and the simulation result obtained by simulating the pixel circuit based on the simulation system is more accurate and reliable.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a simulation system of a pixel circuit according to an embodiment of the present invention.
Fig. 2 is an equivalent circuit diagram of a simulation system of a pixel circuit in each sub-pixel area according to an embodiment of the present invention.
Fig. 3 is a flowchart of a simulation method of a pixel circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Embodiments of the present invention provide a simulation system for pixel circuits, typically found in electronic design automation (Electronic Design Automation, EDA) software, to simulate actual pixel circuits in a liquid crystal display panel. Firstly modeling an actual pixel circuit in a liquid crystal display panel in EDA software to obtain a corresponding simulation system, then simulating the actual pixel circuit based on the simulation system, such as charging rate simulation or capacitive coupling simulation between signals, and the like, further determining the performance of the liquid crystal display panel according to simulation results, or adjusting the simulation system according to the simulation results to make the simulation results better, and finally manufacturing the actual pixel circuit in the liquid crystal display panel according to the simulation system with the optimal simulation results, thereby improving the performance of the liquid crystal display panel.
Referring to fig. 1, an embodiment of the present invention provides a simulation system 1 of a pixel circuit, where the simulation system 1 corresponds to a pixel circuit adopting GCOG In Source technology, and the simulation system 1 includes at least one pixel unit, and each pixel unit includes:
the display device comprises a plurality of scanning lines 10 and a plurality of data lines 20, wherein the plurality of scanning lines 10 are mutually spaced and extend along a first direction, the plurality of data lines 20 are mutually spaced and extend along a second direction, and the plurality of scanning lines 10 and the plurality of data lines 20 are in insulating intersection so as to correspondingly define a plurality of sub-pixel areas 40. The first direction is the horizontal direction shown in fig. 1, the second direction is the vertical direction shown in fig. 1, the number of scanning lines 10 is three as shown in fig. 1, the scanning lines 10 located in the M-1 row, the M-th row and the m+1th row are respectively located, the three scanning lines 10 are mutually spaced and extend along the horizontal direction, the number of the data lines 20 is three as shown in fig. 1, the data lines 20 located in the N-1 column, the N-th column and the n+1th column are respectively located, the three data lines 20 are mutually spaced and extend along the vertical direction, and the three scanning lines 10 and the three data lines 20 are in insulated intersection so as to correspondingly define nine sub-pixel areas 40 in three rows and three columns.
The plurality of patch cords 30 are spaced apart from each other and extend along the second direction, and each scan line 10 is electrically connected to at least one patch cord 30 to transmit a corresponding gate driving signal. The second direction is a vertical direction shown in fig. 1, the number of the patch cords 30 is three as shown in fig. 1, the three patch cords 30 are spaced from each other and extend along the vertical direction, and each scan line 10 is electrically connected to one patch cord 30 correspondingly to transmit a corresponding gate driving signal.
Each of the switching lines 30 includes a plurality of switching sub-segments, each of the switching sub-segments corresponds to one of the sub-pixel regions 40, and a first resistor-capacitor module 100 is disposed between each two adjacent switching sub-segments and electrically connected to each other through the first resistor-capacitor module 100. Each of the switching lines 30 includes three switching sub-segments shown in fig. 1, each switching sub-segment corresponds to one sub-pixel region 40 of a row of three sub-pixel regions 40, a resistor-capacitor module is disposed between each two adjacent switching sub-segments, and for convenience of description, the resistor-capacitor module is referred to as a first resistor-capacitor module 100, and each two adjacent switching sub-segments are electrically connected through the first resistor-capacitor module 100 located therebetween.
The arrangement of the scanning line 10, the data line 20 and the patch cord 30 In the simulation system 1 provided by the embodiment of the invention completely accords with the design rule of the pixel circuit adopting the GCOF In Source technology, and takes the load of connecting lines In actual pixel circuits of the liquid crystal display panel at different positions into consideration, and the simulation result obtained by modeling is more close to the actual pixel circuits In the liquid crystal display panel by arranging a plurality of first resistance capacitance modules 100 In the connecting lines of the simulation system 1, so that the simulation result obtained by simulating the pixel circuits based on the simulation system 1 is more accurate and reliable.
In some embodiments, referring to fig. 1, each scan line 10 includes a plurality of scan subsections, each scan subsection corresponds to one sub-pixel region 40, and a second rc module 200 is disposed between every two adjacent scan subsections and is electrically connected through the second rc module 200. Each scan line 10 includes three scan subsections shown in fig. 1, each scan subsection corresponds to one sub-pixel area 40 in a row of three sub-pixel areas 40, a resistor-capacitor module is disposed between every two adjacent scan subsections, for convenience of description, the resistor-capacitor module is referred to as a second resistor-capacitor module 200, and every two adjacent scan subsections are electrically connected through the second resistor-capacitor module 200 located therebetween.
It can be understood that, considering that the driving mode of the scan line in the actual pixel circuit of the liquid crystal display panel is multi-driving, that is, there are multiple force input points, and meanwhile, because the distances between different sub-pixel areas and the force input points are different, the size of the equivalent series circuit of the signal resistance and capacitance of the scan line is different, in the embodiment of the invention, the signal difference at different positions of the scan line 10 is simulated more effectively by arranging the plurality of second resistance-capacitance modules 200 in the scan line 10 of the simulation system 1, so that the simulation system 1 obtained by modeling is closer to the actual pixel circuit in the liquid crystal display panel, and further, the simulation result obtained by simulating the pixel circuit based on the simulation system 1 is more accurate and reliable.
In some embodiments, referring to fig. 1, each of the switching lines 30 corresponds to one of the data lines 20, and each of the switching lines 30 is located on the same side of the corresponding data line 20. Wherein each of the transfer lines 30 shown in fig. 1 is located on the right side of the corresponding data line 20.
In some embodiments, referring to fig. 1, a thin film transistor 401 is disposed in each sub-pixel region 40, a gate of the thin film transistor 401 is electrically connected to the scan line 10 defining the sub-pixel region 40, a source of the thin film transistor 401 is electrically connected to the data line 20 defining the sub-pixel region 40, a drain of the thin film transistor 401 is electrically connected to the pixel electrode terminal 402, and the pixel electrode terminal 402 is configured to receive an externally input pixel voltage.
In some embodiments, referring to fig. 1, a twenty-first capacitor C21 is further disposed in each sub-pixel region 40, one end of the twenty-first capacitor C21 is electrically connected to the pixel electrode terminal 402 in the sub-pixel region 40, and the other end of the twenty-first capacitor C21 is electrically connected to the patch cord 30 corresponding to the data line 20 defining the sub-pixel region 40.
In some embodiments, referring to fig. 1, a seventh capacitor C7 is further disposed between each two adjacent sub-pixel regions 40 in each row of sub-pixel regions 40, one end of the seventh capacitor C7 is electrically connected to the patch cord 30 corresponding to the data line 20 defining one of the sub-pixel regions 40, and the other end of the seventh capacitor C7 is electrically connected to the pixel electrode terminal 402 in the other sub-pixel region 40.
It can be understood that, considering that parasitic capacitance exists between the patch cord in the actual pixel circuit of the liquid crystal display panel and the pixel electrode in the sub-pixel area on two adjacent sides, in the embodiment of the invention, the twenty-first capacitor C21 and the seventh capacitor C7 are respectively disposed between each patch cord 30 of the simulation system 1 and the pixel electrode terminal 402 in the sub-pixel area 40 on two adjacent sides, so that the simulation system 1 obtained by modeling is more close to the actual pixel circuit in the liquid crystal display panel, and further, the simulation result obtained by simulating the pixel circuit based on the simulation system 1 is more accurate and reliable.
In some embodiments, referring to fig. 1, a third capacitor C3 is further disposed between each two adjacent sub-pixel regions 40 in each row of sub-pixel regions 40, one end of the third capacitor C3 is electrically connected to the patch cord 30 corresponding to the data line 20 defining one of the sub-pixel regions 40, and the other end of the third capacitor C3 is electrically connected to the data line 20 defining the other sub-pixel region 40.
It can be understood that, considering that parasitic capacitance exists between the patch cord and the adjacent data line in the actual pixel circuit of the liquid crystal display panel, in the embodiment of the invention, the third capacitance C3 is disposed between the patch cord corresponding to each sub-pixel area 40 of the simulation system 1 and the data line 20 defining the adjacent sub-pixel area 40, so that the simulation system 1 obtained by modeling is closer to the actual pixel circuit in the liquid crystal display panel, and further, the simulation result obtained by simulating the pixel circuit based on the simulation system 1 is more accurate and reliable.
In some embodiments, a fourth capacitor C4 is further disposed in each sub-pixel region 40, one end of the fourth capacitor C4 is electrically connected to the data line 20 defining the sub-pixel region 40, and the other end of the fourth capacitor C4 is electrically connected to the pixel electrode terminal 402 in the sub-pixel region 40.
It can be appreciated that, considering that there is a parasitic capacitance between the data line and the pixel electrode in the actual pixel circuit of the liquid crystal display panel, in the embodiment of the invention, the simulation system 1 obtained by modeling is more close to the actual pixel circuit in the liquid crystal display panel by setting the fourth capacitance C4 between the data line 20 and the pixel electrode terminal 402 of the simulation system 1, and further, the simulation result obtained by simulating the pixel circuit based on the simulation system 1 is more accurate and reliable.
In some embodiments, referring to fig. 2, a first capacitor C1, a fifth capacitor C5 and a sixth capacitor C6 are further disposed in each sub-pixel region 40; one end of the first capacitor C1 is electrically connected to the gate of the thin film transistor 401 in the sub-pixel region 40, and the other end of the first capacitor C1 is electrically connected to the pixel electrode terminal 402 (not shown in fig. 2) in the sub-pixel region 40; one end of the fifth capacitor C5 is electrically connected to the pixel electrode terminal 402 in the sub-pixel area 40, and the other end of the fifth capacitor C5 is electrically connected to the first common electrode terminal 403, where the first common electrode terminal 403 is configured to receive a first common voltage input from the outside, for example, a common voltage applied on the array substrate side in an actual pixel circuit of the liquid crystal display panel; one end of the sixth capacitor C6 is electrically connected to the pixel electrode terminal 402 in the sub-pixel area 40, and the other end of the sixth capacitor C6 is electrically connected to the second common electrode terminal 404, where the second common electrode terminal 404 is configured to receive a second common voltage input from the outside, for example, a common voltage applied on the color film substrate side in an actual pixel circuit of the liquid crystal display panel.
As can be appreciated, in consideration of parasitic capacitance existing between the gate and the drain of the thin film transistor in the actual pixel circuit of the liquid crystal display panel, in the embodiment of the present invention, the first capacitance C1 is provided between the gate and the drain of the thin film transistor 401 of the simulation system 1. In view of the storage capacitance and the liquid crystal capacitance existing between the pixel electrode in the actual pixel circuit of the liquid crystal display panel and the common electrode on the array substrate side, in the embodiment of the present invention, the fifth capacitance and the sixth capacitance are provided in the simulation system 1. Therefore, the simulation system 1 obtained by modeling is more close to an actual pixel circuit in the liquid crystal display panel, and the simulation result obtained by simulating the pixel circuit based on the simulation system 1 is more accurate and reliable.
The embodiment of the invention also provides a simulation method of the pixel circuit, referring to fig. 3, the simulation method comprises the following steps:
step S1, providing the simulation system 1 described above.
In step S2, the gate driving signals are input to the plurality of patch cords 30 in the simulation system 1, the source driving signals are input to the plurality of data lines 20 in the simulation system 1, the pixel voltages are input to all the pixel electrode terminals 402 in the simulation system 1, the first common voltage is input to all the first common electrode terminals 403 in the simulation system 1, and the second common voltage is input to all the second common electrode terminals 404 in the simulation system 1, so as to simulate the pixel circuit.
Specifically, since the structure of the simulation system 1 is described in detail in the above embodiments, the description thereof is omitted here. The arrangement of the scanning line 10, the data line 20 and the patch cord 30 In the simulation system 1 provided by the embodiment of the invention completely accords with the design rule of the pixel circuit adopting the GCOF In Source technology, and takes the load of connecting lines In actual pixel circuits of the liquid crystal display panel at different positions into consideration, and the simulation result obtained by modeling is more close to the actual pixel circuits In the liquid crystal display panel by arranging a plurality of first resistance capacitance modules 100 In the connecting lines of the simulation system 1, so that the simulation result obtained by simulating the pixel circuits based on the simulation system 1 is more accurate and reliable.
In summary, the embodiment of the invention provides a modeling simulation scheme suitable for a pixel circuit adopting a GCOF In Source technology, and the charging condition of sub-pixels In sub-pixel areas at different positions is obtained by constructing a simulation system corresponding to an actual pixel circuit, and then outputting a gate driving signal from a Source side flip-chip film and passing through different resistance-capacitance modules. The influence of the patch cord on the charging rate of the adjacent sub-pixels is simulated by adding a plurality of sub-pixel areas in the pixel unit and adding corresponding capacitors in the sub-pixel areas. By adopting the simulation method, the charging difference of adjacent sub-pixels caused by the patch cord can be simulated more finely, and the actual pixel circuit in the liquid crystal display panel can be simulated more finely, so that the accuracy and reliability of circuit simulation are improved.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (8)
1. A simulation system of a pixel circuit, comprising:
a plurality of scanning lines, a plurality of data lines and a plurality of patch cords; wherein,
the plurality of scanning lines are mutually spaced and extend along a first direction, the plurality of data lines are mutually spaced and extend along a second direction, and the plurality of scanning lines and the plurality of data lines are in insulating intersection so as to correspondingly define a plurality of sub-pixel areas;
the plurality of patch cords are mutually spaced and extend along the second direction, and each scanning line is correspondingly and electrically connected with at least one patch cord so as to transmit corresponding grid driving signals;
each patch cord comprises a plurality of patch sub-segments, each patch sub-segment corresponds to one sub-pixel area, every two adjacent patch sub-segments are electrically connected through a first resistance-capacitance module, and the patch sub-segments and the first resistance-capacitance modules in the same patch cord are sequentially and alternately distributed in the second direction;
a thin film transistor is arranged in each sub-pixel region, the drain electrode of the thin film transistor is electrically connected with a pixel electrode terminal, and the pixel electrode terminal is used for receiving externally input pixel electrode voltage;
a twenty-first capacitor is further arranged in each sub-pixel region, one end of the twenty-first capacitor is electrically connected with the pixel electrode terminal in the sub-pixel region, and the other end of the twenty-first capacitor is electrically connected with the patch cord corresponding to the data line defining the sub-pixel region;
a seventh capacitor is further arranged between every two adjacent sub-pixel areas in each row of the sub-pixel areas, one end of the seventh capacitor is electrically connected with the patch cord corresponding to the data line defining one of the sub-pixel areas, and the other end of the seventh capacitor is electrically connected with the pixel electrode terminal in the other sub-pixel area;
the data line electrically connected with the thin film transistor in the sub-pixel area and the switching line electrically connected with the twenty-first capacitor in the sub-pixel area are respectively positioned at two sides of the thin film transistor in the first direction.
2. The simulation system of claim 1, wherein each scan line comprises a plurality of scan subsections, each scan subsection corresponds to one of the sub-pixel areas, and a second resistance-capacitance module is arranged between every two adjacent scan subsections and is electrically connected through the second resistance-capacitance module.
3. The simulation system of claim 1, wherein each patch cord corresponds to one of the data lines, and each patch cord is located on a same side of the corresponding data line.
4. The simulation system of claim 1, wherein a gate of the thin film transistor is electrically connected to the scan line defining the sub-pixel region, and a source of the thin film transistor is electrically connected to the data line defining the sub-pixel region.
5. The simulation system of claim 4, wherein a third capacitor is further disposed between each two adjacent sub-pixel regions in each row of the sub-pixel regions, one end of the third capacitor is electrically connected to the patch cord corresponding to the data line defining one of the sub-pixel regions, and the other end of the third capacitor is electrically connected to the data line defining the other sub-pixel region.
6. The simulation system of claim 4, wherein a fourth capacitor is further disposed in each of the sub-pixel regions, one end of the fourth capacitor is electrically connected to the data line defining the sub-pixel region, and the other end of the fourth capacitor is electrically connected to the pixel electrode terminal in the sub-pixel region.
7. The simulation system according to claim 4, wherein each of the sub-pixel areas is further provided with a first capacitor, a fifth capacitor and a sixth capacitor; one end of the first capacitor is electrically connected with the grid electrode of the thin film transistor in the sub-pixel area, and the other end of the first capacitor is electrically connected with the drain electrode of the thin film transistor in the sub-pixel area; one end of the fifth capacitor is electrically connected with the pixel electrode terminal in the sub-pixel area, and the other end of the fifth capacitor is electrically connected with a first common electrode voltage terminal, and the first common electrode voltage terminal is used for receiving a first common electrode voltage input from the outside; one end of the sixth capacitor is electrically connected with the pixel electrode terminal in the sub-pixel area, and the other end of the sixth capacitor is connected with a second common electrode voltage terminal, and the second common electrode voltage terminal is used for receiving an externally input second common electrode voltage.
8. A method of simulating a pixel circuit, comprising:
providing a simulation system according to any of claims 1-7;
the pixel circuit is simulated by inputting gate driving signals to a plurality of patch cords in the simulation system, inputting source driving signals to a plurality of data lines in the simulation system, inputting pixel electrode voltages to all pixel electrode terminals in the simulation system, inputting first common electrode voltages to all first common electrode voltage terminals in the simulation system, and inputting second common electrode voltages to all second common electrode voltage terminals in the simulation system.
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