CN113078061A - Wafer structure, preparation method thereof, three-dimensional memory and electronic equipment - Google Patents
Wafer structure, preparation method thereof, three-dimensional memory and electronic equipment Download PDFInfo
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- CN113078061A CN113078061A CN202110315251.9A CN202110315251A CN113078061A CN 113078061 A CN113078061 A CN 113078061A CN 202110315251 A CN202110315251 A CN 202110315251A CN 113078061 A CN113078061 A CN 113078061A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 239000010409 thin film Substances 0.000 claims abstract description 265
- 239000010410 layer Substances 0.000 claims description 80
- 238000010438 heat treatment Methods 0.000 claims description 40
- 238000000059 patterning Methods 0.000 claims description 17
- 239000002346 layers by function Substances 0.000 claims description 9
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 239000010408 film Substances 0.000 abstract description 58
- 238000000034 method Methods 0.000 abstract description 17
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000003860 storage Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004093 laser heating Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Semiconductor Memories (AREA)
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Abstract
The application provides a wafer structure, wafer structure includes wafer and thin film layer, the thin film layer set up in one side of wafer, the thin film layer includes at least one first film portion and at least one second film portion, first film portion connects second film portion, just first film portion with the warpage degree of second film portion is different. The different positions of the thin film layer can be subjected to customized warping through a process technology, so that the thin film layer forms a plurality of first thin film portions and a plurality of second thin film portions, the warping degree of the wafer structure is controlled, the same warping degree in different radial directions can be achieved, and the warping degree is prevented from being too large. The application also provides a wafer preparation method, a three-dimensional memory and electronic equipment.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a wafer structure, a method for manufacturing the wafer structure, a three-dimensional memory, and an electronic device.
Background
In the manufacturing process of the semiconductor wafer, due to a series of reasons such as crystal mismatch and thermal mismatch between the film and the wafer and between the film and the wafer, the wafer can be deformed in different degrees and warped. If the wafer warpage is too large, the wafer cannot be leveled and cannot enter the machine. In addition, if the warpage of the wafer in different radial directions is different, the process with higher requirements on the flatness of the wafer, including wafer level bonding, etc., will be affected.
Disclosure of Invention
The application discloses wafer structure can solve the technical problem that the wafer warpage is too big, the warpage degree is different in different radial directions.
In a first aspect, the present application provides a wafer structure, the wafer structure includes a wafer and a thin film layer, the thin film layer is disposed on one side of the wafer, the thin film layer includes at least one first thin film portion and at least one second thin film portion, the first thin film portion is connected to the second thin film portion, and the first thin film portion and the second thin film portion are different in warpage degree.
The first thin film portion is warped towards one side away from the wafer, and the warping direction of the second thin film portion is the same as that of the first thin film portion.
The number of the first film parts is greater than or equal to two, the first film parts are arranged at intervals, the film layers are provided with centers, and the warping degree of the first film parts close to the centers is smaller than that of the first film parts far away from the centers.
Wherein the first film part and the second film part are arranged in a staggered manner.
The first film part further comprises a plurality of first sub-film parts arranged at intervals.
The second film part is arranged around the first film part; alternatively, the first thin film portion is provided so as to surround the second thin film portion.
Wherein the second thin film portion is externally connected to the peripheral side surface of the first thin film portion.
The number of the first thin film portions is two, and two opposite ends of the second thin film portion are externally connected to the peripheral side face of the first thin film portion, so that the two first thin film portions are distributed on two opposite sides of the second thin film portion.
The different positions of the thin film layer can be subjected to customized warping through a process technology, so that the thin film layer forms a plurality of first thin film portions and a plurality of second thin film portions, the warping degree of the wafer structure is controlled, the same warping degree in different radial directions can be achieved, and the warping degree is prevented from being too large.
In a second aspect, the present application further provides a wafer preparation method, where the wafer preparation method includes:
providing a wafer;
the thin film layer is formed on one side of the wafer; and
and carrying out graphical heat treatment on the thin film layer to form at least one first thin film part and at least one second thin film part, wherein the first thin film part is connected with the second thin film part, and the warping degree of the first thin film part is different from that of the second thin film part.
Wherein the step of performing a patterned heat treatment on the thin film layer to form at least one first thin film portion and at least one second thin film portion comprises:
the thin film layer is provided with at least one first thin film area and at least one second thin film area, and the at least one first thin film area is subjected to heat treatment so that the thin film layer of the first thin film area forms a first thin film part and the thin film layer of the second thin film area forms a second thin film part.
Wherein, the step of performing the graphic heat treatment on the film layer to form at least one first film portion and at least one second film portion, wherein the first film portion is connected with the second film portion, and the warping degree of the first film portion is different from that of the second film portion comprises the following steps:
the thin film layer has a center, and the thin film layer is subjected to patterning heat treatment so that the heating time or the heating temperature of the first thin film portion close to the center is shorter than the heating time or the heating temperature of the first thin film portion at the center.
In a third aspect, the present application further provides a three-dimensional memory, where the three-dimensional memory includes a functional layer and the wafer structure according to the first aspect, and the functional layer is disposed on a side of the wafer departing from the thin film layer.
In a fourth aspect, the present application further provides an electronic device, which includes a processor and the three-dimensional memory according to the third aspect, wherein the processor is configured to write data into the three-dimensional memory and read data from the three-dimensional memory.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for a person skilled in the art to obtain other drawings based on the drawings without any inventive exercise.
Fig. 1 is a partial top view of a wafer structure according to an embodiment of the present disclosure.
Fig. 2 is a schematic sectional view taken along line I-I in fig. 1.
Fig. 3 is a partial cross-sectional view of a wafer structure according to another embodiment of the present application.
Fig. 4 is a partial top view of a wafer structure according to another embodiment of the present disclosure.
Fig. 5 is a partial top view of a wafer structure according to another embodiment of the present disclosure.
Fig. 6 is a partial top view of a wafer structure according to another embodiment of the present disclosure.
Fig. 7 is a partial top view of a wafer structure according to another embodiment of the present disclosure.
Fig. 8 is a flowchart illustrating a wafer manufacturing method according to an embodiment of the present application.
Fig. 9 is a partial cross-sectional schematic view of a three-dimensional memory according to an embodiment of the present application.
Fig. 10 is a schematic diagram of an electronic device framework according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.
A wafer structure 1 is provided, please refer to fig. 1 and fig. 2 together, fig. 1 is a schematic partial top view of the wafer structure according to an embodiment of the present application; fig. 2 is a schematic sectional view taken along line I-I in fig. 1. The wafer structure 1 includes a wafer 11 and a thin film layer 12, the thin film layer 12 is disposed on one side of the wafer 11, the thin film layer 12 includes at least one first thin film portion 121 and at least one second thin film portion 122, the first thin film portion 121 is connected to the second thin film portion 122, and warpage degrees of the first thin film portion 121 and the second thin film portion 122 are different.
Specifically, the wafer 11 refers to a silicon wafer used for manufacturing a silicon semiconductor circuit. In this embodiment, the material of the thin film layer 12 is SiN (silicon nitride), and in other possible embodiments, the thin film layer 12 may also be made of other materials, which is not limited in this application.
It should be noted that, in the prior art, during the manufacturing process of the wafer structure 1, due to a series of reasons, such as crystal mismatch and thermal mismatch, between the thin film layer 12 and the wafer 11, or between thin film materials in the thin film layer 12, the wafer structure 1 may be deformed and warped to different degrees. If the wafer structure 1 is warped too much, it will not be leveled and will not enter the machine. In addition, if the wafer structure 1 warps in different radial directions to different degrees, the process procedure including wafer 11 level bonding, etc. which requires high flatness of the wafer structure 1 will be affected.
For example, in a possible embodiment, the thin film layer 12 has portions with different warpage degrees before the patterning heat treatment, the patterning heat treatment process is performed on the first film portion 121, the warpage degree of the first film portion 121 is controlled to be larger, and the first film portion 121 is distributed on the portion with the smaller warpage degree of the thin film layer 12, so that the difference of the warpage degrees between different portions of the thin film layer 12 is reduced, thereby adjusting the thin film layer 12 to be approximately flat. In other possible embodiments, the first film portion 121 may also be radially distributed, or the second film portion 122 may be subjected to a patterning heat treatment, and the like, which is not limited in this application.
Optionally, the area of the first film portion 121 occupies 10% to 50% of the area of the film layer 12. Further alternatively, the area of the first film portion 121 occupies 20% to 40% of the area of the film layer 12, which is not limited in this application.
It can be understood that, in the present embodiment, different positions of the thin film layer 12 can be subjected to customized warpage through a process technology, so that the thin film layer 12 forms a plurality of the first thin film portions 121 and a plurality of the second thin film portions 122, thereby controlling the warpage degree of the wafer structure 1, and realizing the same warpage degree in different radial directions and avoiding an excessive warpage degree.
In a possible embodiment, referring to fig. 2 again, a side of the first thin film portion 121 facing away from the wafer 11 is warped, and a warping direction of the second thin film portion 122 is the same as the first thin film portion 121.
Specifically, in the present embodiment, in order to make the thin film layer 12 approximately flat, the first film portion 121 and the second film portion 122 have the same warping direction. In another possible embodiment, please refer to fig. 3, in which fig. 3 is a partial cross-sectional view of a wafer structure according to another embodiment of the present disclosure. As shown in fig. 3, a specific electronic component may be mounted on the wafer structure 1 by making the warping directions of the first thin film portion 121 and the second thin film portion 122 different according to a desired special configuration.
Of course, in other possible embodiments, the warping directions of a portion of the first thin film portion 121 and a portion of the second thin film portion 122 may be the same, and the warping directions of the remaining portion of the first thin film portion 121 and the remaining portion of the second thin film portion 122 are different, which is not limited in this application.
In a possible embodiment, referring to fig. 1 again, the number of the first film portions 121 is greater than or equal to two, a plurality of the first film portions 121 are disposed at intervals, the film layer 12 has a center, and the warpage degree of the first film portions 121 near the center is smaller than the warpage degree of the first film portions 121 far from the center.
Specifically, in this embodiment, the degree of warpage of the first thin film portion 121 near the center is smaller than the degree of warpage of the first thin film portion 121 far from the center, and it can be understood that the degree of warpage of the first thin film portion 121 far from the center of the thin film layer 12 is larger than the degree of warpage of the first thin film portion 121 near the center of the thin film layer 12.
Specifically, the degree of warpage of the first thin film portion 121 may be different by patterning the first thin film portion 121 with different degrees of heat treatment. In general, since the degree of warpage is small at the edge of the thin film layer 12 and large at the portion near the center of the thin film layer 12, the degree of warpage at the edge of the thin film layer 12 should be increased by a process technique, that is, the degree of warpage of the first thin film portion 121 farther from the center of the thin film layer 12 is larger than that of the first thin film portion 121 closer to the center of the thin film layer 12. This method can be realized by varying the parameters and time for performing the heat treatment on the first thin film portion 121.
It is understood that, in the present embodiment, the degree of warpage of the first film portion 121 farther from the center of the thin film layer 12 is large as compared to the first film portion 121 closer to the center of the thin film layer 12, so that the difference in the degree of warpage between different portions of the thin film layer 12 is reduced.
In one possible embodiment, please refer to fig. 1 again, the first thin film portions 121 and the second thin film portions 122 are disposed alternately.
Specifically, as shown in fig. 1, the first thin film portion 121 and the second thin film portion 122 are in the shape of a long strip. When the first thin film portion 121 and the second thin film portion 122 are in the shape of long strips, the degree of warpage in the extending direction parallel to the first thin film portion 121 or the second thin film portion 122 is more uniform, and the method is suitable for the manufacturing process of some corresponding wafer structures 1. Of course, in other possible embodiments, the shapes of the first film portion 121 and the second film portion 122 may also be other shapes, which is not limited in this application.
In one possible embodiment, please refer to fig. 4, in which fig. 4 is a partial top view of a wafer structure according to another embodiment of the present disclosure. The first thin film portion 121 further includes a plurality of first sub-thin film portions 1211 disposed at intervals.
Specifically, as shown in fig. 4, the first sub-film portions 1211 are distributed more uniformly in the radial direction of the thin film layer 12, so that the degree of warp in the radial direction of the thin film layer 12 is controlled. In this embodiment, the first sub-thin film portion 1211 is rectangular, and in other possible embodiments, the first sub-thin film portion 1211 may also be other shapes, which is not limited in this application.
In one possible embodiment, please refer to fig. 5, in which fig. 5 is a partial top view of a wafer structure according to another embodiment of the present disclosure. The second thin film portion 122 surrounds the first thin film portion 121.
Specifically, as shown in fig. 5, a plurality of the second film portions 122 are respectively enclosed in the corresponding first film portions 121, so that after the patterning heat treatment is performed on the first film portions 121, the first film portions 121 and the second film portions 122 enclosed around the first film portions 121 have similar warpage, and the film layer 12 is approximately flat.
In one possible embodiment, please refer to fig. 6, in which fig. 6 is a partial top view of a wafer structure according to another embodiment of the present disclosure. The first thin film portion 121 surrounds the second thin film portion 122.
Specifically, in the present embodiment, the first film portion 121 is located at an edge portion of the film layer 12. Since the degree of warp is small at the edge of the film layer 12, the degree of warp is large at a portion near the center of the film layer 12. When the first thin film portion 121 is subjected to the patterning heat treatment, the degree of warpage of the first thin film portion 121 is increased, so that the difference in the degree of warpage between the first thin film portion 121 and the second thin film portion 122 is reduced, and the thin film layer 12 is made approximately flat.
In one possible embodiment, please refer to fig. 7, in which fig. 7 is a partial top view of a wafer structure according to another embodiment of the present disclosure. The second thin film portion 122 is externally connected to the peripheral surface of the first thin film portion 121.
It should be noted that, in the prior art, before the patterning heat treatment is performed on the thin film layer 12, the thin film layer 12 may warp to a large extent in a certain radial direction and an extending direction thereof, and warp to a small extent in a direction perpendicular to the radial direction may occur.
Specifically, in this embodiment, the number of the first thin film portions 121 is two, and two opposite ends of the second thin film portion 122 are externally connected to the peripheral side surface of the first thin film portion 121, so that the two first thin film portions 121 are distributed on two opposite sides of the second thin film portion 122. As shown in fig. 7, when the first thin film portion 121 is subjected to the patterning heat treatment, the second thin film portion 122 is externally connected to the peripheral surface of the first thin film portion 121, and a portion along the longer axis of the second thin film portion 122 is largely warped while a portion along the shorter axis of the second thin film portion 122 is largely warped. Therefore, after the patterning heat treatment is performed on the first thin film portion 121, the difference in the degree of warpage between the first thin film portion 121 and the second thin film portion 122 is reduced, so that the thin film layer 12 is made approximately flat.
It can be understood that the wafer structure 1 provided by the present application can adapt to the situation that the warpage degree of the wafer structure 1 is different under various technical processes by performing the graphic heat treatment on the thin film layer 12, so that the wafer structure 1 has the thin film layer 12 which is relatively flat and has little difference in the warpage degree in the radial direction.
Fig. 8 is a flowchart illustrating a method for manufacturing a wafer 11 according to an embodiment of the present disclosure, and fig. 8 is a schematic diagram illustrating a process of manufacturing a wafer. The wafer preparation method comprises the following steps: steps S701, S702, and S703, and steps S701, S702, and S703 are described in detail as follows.
S701, providing a wafer;
s702, forming a thin film layer on one side of the wafer; and
s703, performing a patterning heat treatment on the thin film layer to form at least one first thin film portion and at least one second thin film portion, where the first thin film portion is connected to the second thin film portion, and the first thin film portion and the second thin film portion have different warpage degrees.
Specifically, the step of performing a patterning heat treatment on the thin film layer to form at least one first thin film portion and at least one second thin film portion includes:
the thin film layer 12 has at least one first thin film region and at least one second thin film region, and the at least one first thin film region is subjected to heat treatment so that the thin film layer 12 of the first thin film region forms a first thin film portion 121 and the thin film layer of the second thin film region forms a second thin film portion 122.
Specifically, the number and shape of the first thin film portion 121 and the second thin film portion 122 are predetermined, and may be changed according to the actual situation of the wafer structure 1, the function, and the like, which are required.
In a possible embodiment, the step of performing a patterning heat treatment on the thin film layer to form at least one first thin film portion and at least one second thin film portion, wherein the first thin film portion is connected with the second thin film portion, and the first thin film portion and the second thin film portion are warped to different degrees includes:
the thin film layer 12 has a center, and the thin film layer 12 is subjected to a patterning heat treatment so that the heating time or the heating temperature of the first thin film portion 121 near the center is shorter than the heating time or the heating temperature of the first thin film portion 121 at the center.
Specifically, the warpage degree can be controlled by parameters or time of the patterning heat treatment, for example, when the technical process of the patterning heat treatment is laser heating, the warpage degree of different first thin film portions 121 can be made different by adjusting different laser power parameters of different first thin film portions 121; alternatively, the warping degree of the first thin film portion 121 may be different by adjusting the laser irradiation time of the first thin film portion 121, which is not limited in the present application.
For example, if the power parameters of the laser irradiation are the same, the irradiation time for a portion of the first thin film portion 121 is 5 seconds, and the irradiation time for the remaining portion of the first thin film portion 121 is 10 seconds, the warpage level of the first thin film portion 121 with the irradiation time of 10 seconds should be greater than the warpage level of the first thin film portion 121 with the irradiation time of 5 seconds; similarly, if the laser irradiation time is the same, the laser power applied to a part of the first thin film portion 121 is 1 watt, and the laser power applied to the other part of the first thin film portion 121 is 5 watts, the degree of warpage of the first thin film portion 121 with the laser power of 1 watt should be smaller than the degree of warpage of the first thin film portion 121 with the laser power of 5 watts. It should be understood that the above values are only exemplary, and the laser power and the laser irradiation time are not limited in the present application.
Fig. 9 is a schematic partial cross-sectional view of a three-dimensional memory 2 according to an embodiment of the present application. The three-dimensional memory 2 comprises the functional layer 21 and the wafer structure 1 as described above, wherein the functional layer 21 is arranged on the side of the wafer 11 away from the thin film layer 12.
Specifically, the functional layer 21 is provided with various electronic components and can realize some functions, and the wafer 11 and the thin film layer 12 are used for bearing the functional layer 21. Please refer to the above description for the wafer structure 1, which is not described herein. It can be understood that the thin film layer 12 in the wafer structure 1 provided by the present application is relatively flat, and can better bear the functional layer 21.
Fig. 10 is a drawing showing an electronic device 3, and fig. 10 is a schematic diagram of an electronic device framework according to an embodiment of the present application. The electronic device 3 comprises a processor 31 and the three-dimensional memory 2 as described above, the processor 31 being configured to write data into and read data from the three-dimensional memory 2.
Specifically, the electronic device 3 may be an electronic computer, a smart phone, a smart television, a smart set-top box, a smart router, an electronic digital camera, or the like having a storage device. The electronic device 3 of the present application typically further includes a processor 31, an input-output device, a display device, and the like. The three-dimensional memory 2 provided by the application is manufactured by processes such as packaging and the like to form a storage device such as a flash memory, and the storage device is used for storing files or data and is called by the processor 31. Specifically, the processor 31 may write data into the storage device, i.e., the three-dimensional memory 2 provided in the present application, or may read data from the storage device, i.e., the three-dimensional memory 2 provided in the present application. The input/output device is used for inputting instructions or outputting signals, and the display device visualizes the signals to realize various functions of the electronic device 3. The electronic device 3 provided by the present application can effectively improve the quality of the three-dimensional memory 2 and the electronic device 3 by using the three-dimensional memory 2 provided by the above embodiments of the present application.
The principle and the implementation of the present application are explained herein by applying specific examples, and the above description of the embodiments is only used to help understand the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (13)
1. A wafer structure is characterized by comprising a wafer and a thin film layer, wherein the thin film layer is arranged on one side of the wafer and comprises at least one first thin film part and at least one second thin film part, the first thin film part is connected with the second thin film part, and the warping degrees of the first thin film part and the second thin film part are different.
2. The wafer structure of claim 1, wherein a side of the first thin film portion facing away from the wafer is warped, and a warping direction of the second thin film portion is the same as the first thin film portion.
3. The wafer structure of claim 1, wherein the number of the first thin film portions is greater than or equal to two, a plurality of the first thin film portions are arranged at intervals, the thin film layer has a center, and the degree of warpage of the first thin film portions near the center is smaller than the degree of warpage of the first thin film portions far from the center.
4. The wafer structure of claim 3, wherein the first thin film portions and the second thin film portions are staggered.
5. The wafer structure of claim 3, wherein the first thin film portion further comprises a plurality of first sub-thin film portions arranged at intervals.
6. The wafer structure of claim 1, wherein the second thin film portion surrounds the first thin film portion; alternatively, the first thin film portion is provided so as to surround the second thin film portion.
7. The wafer structure of claim 1, wherein the second thin film portion circumscribes a peripheral side surface of the first thin film portion.
8. The wafer structure of claim 7, wherein the number of the first thin film portions is two, and two opposite ends of the second thin film portion are externally connected to the peripheral side surface of the first thin film portion, so that the two first thin film portions are distributed on two opposite sides of the second thin film portion.
9. A wafer preparation method is characterized by comprising the following steps:
providing a wafer;
the thin film layer is formed on one side of the wafer; and
and carrying out graphical heat treatment on the thin film layer to form at least one first thin film part and at least one second thin film part, wherein the first thin film part is connected with the second thin film part, and the warping degree of the first thin film part is different from that of the second thin film part.
10. The wafer preparation method of claim 9, wherein the step of performing a patterned heat treatment on the thin film layer to form at least one first thin film portion and at least one second thin film portion comprises:
the thin film layer is provided with at least one first thin film area and at least one second thin film area, and the at least one first thin film area is subjected to heat treatment so that the thin film layer of the first thin film area forms a first thin film part and the thin film layer of the second thin film area forms a second thin film part.
11. The wafer preparation method according to claim 9, wherein the step of performing the patterned heat treatment on the thin film layer to form at least one first thin film portion and at least one second thin film portion, wherein the first thin film portion is connected with the second thin film portion, and the first thin film portion and the second thin film portion have different warpage degrees comprises the steps of:
the thin film layer has a center, and the thin film layer is subjected to patterning heat treatment so that the heating time or the heating temperature of the first thin film portion close to the center is shorter than the heating time or the heating temperature of the first thin film portion at the center.
12. Three-dimensional memory, characterized in that the three-dimensional memory comprises a functional layer and a wafer structure according to any one of claims 1 to 8, wherein the functional layer is arranged on a side of the wafer facing away from the thin film layer.
13. An electronic device, comprising a processor and the three-dimensional memory of claim 12, wherein the processor is configured to write data to and read data from the three-dimensional memory.
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| CN202110315251.9A CN113078061B (en) | 2021-03-24 | 2021-03-24 | Wafer structure, preparation method thereof, three-dimensional memory and electronic equipment |
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Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH08321445A (en) * | 1995-05-25 | 1996-12-03 | Sumitomo Electric Ind Ltd | Microdevice substrate and manufacture thereof |
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| CN113078061B (en) | 2023-10-31 |
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