JP2009076721A - Multilayer wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer wiring board that does not require correction of warpage even in manufacturing the wiring board by preventing occurrence of warpage of the wiring board. <P>SOLUTION: This multilayer wiring board 100, 100a-100e including a wiring layer 40, 40a-40e with a power plane and/or ground plane 10, 10a-10ce formed therein, is characterized in that the power plane and/or the ground plane are/is cut at predetermined cut lines 20, 20a-20e to be divided into a plurality of power plane pieces and/or ground plane pieces 11, 11a-11e. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a multilayer wiring board, and more particularly to a multilayer wiring board including a wiring layer on which a power plane and / or a ground plane is formed.

  Conventionally, a multilayer wiring board (build-up board) having a multilayer wiring structure in which a resin layer and a wiring layer are stacked on a core board is known. However, due to recent demands for thinning and space saving, A coreless multilayer wiring board having a multilayer wiring structure without a substrate has been proposed. Such a coreless multilayer wiring board generally has a wiring layer on which a power plane and / or a ground plane is formed, and supplies a potential to a wiring pattern for signals.

  FIG. 9 is a plan configuration diagram of a wiring layer 240 in which a power plane and / or a ground plane 210 of a conventional multilayer wiring board 300 is formed. In addition, an insulating layer 250 existing above or below the wiring layer 240 is shown around the wiring layer 240.

  In many cases, the multilayer wiring board 300 includes a wiring layer 240 on which a power plane and / or a ground plane 210 are formed in order to supply a power source or a ground potential in addition to a signal wiring pattern. As an example, the power plane and / or the ground plane 210 is a so-called solid wiring layer 240 so as to surround the central portion 230 around the virtual semiconductor element 290 mounted on the semiconductor element mounting surface of the multilayer wiring board 300. It is formed as a wiring pattern that covers most of it with a continuous metal. The power plane and / or the ground plane 210 has vias (not shown) formed above or below the wiring pattern, and is connected to the power source or the ground via the vias to supply potential to the wiring layer 240. Further, the potential is supplied from the wiring layer 240 to the wiring layer on which the signal wiring pattern is formed. In the multilayer wiring board 300 having the wiring layer 240 and the insulating layer 250, copper is often used for the power plane and / or the ground plane 210, and an epoxy resin is often used for the insulating layer 250.

In such a coreless multilayer wiring board, since the wiring board is thinned and the strength of the board itself is weakened, there is a technique in which a metal frame is provided at the end of the board in order to improve handling properties such as transportation. It is known (see, for example, Patent Document 1).
JP 2000-323613 A

  However, in the configuration of the prior art shown in FIG. 9 described above, even when the heat treatment is performed in the manufacturing process of the multilayer wiring board 300, the manufacturing process is finished and the multilayer wiring board is finished even if the multilayer wiring board 300 is not warped. When 300 reaches normal temperature, the epoxy resin of the insulating layer 250 contracts and the multilayer wiring board 300 warps.

  FIG. 10 is a cross-sectional configuration diagram showing a cross-sectional structure of a wiring layer 240 on which a power plane and / or ground plane 210 is formed and a lower insulating layer 250 of a conventional wiring board 300.

  FIG. 10A is a diagram showing a cross-sectional configuration of the wiring layer 240 and the insulating layer 250 that are heated to, for example, about 150 ° C. when the wiring substrate 300 is manufactured. In FIG. 10A, a wiring layer 240 in which a power plane and / or a ground plane 210 made of copper is formed is disposed on an insulating layer 250 made of epoxy resin. In an environment of about 150 ° C. during the production of the wiring board 300, both form parallel layers.

  FIG. 10B is a diagram showing a cross-sectional configuration of the wiring layer 240 and the insulating layer 250 in a state where the temperature of the wiring board 300 is lowered. The thermal expansion coefficient of epoxy resin is 30-40 [1 / K], and the thermal expansion coefficient of copper is 17-18 [1 / K]. The shrinkage rate of the insulating layer 250 is larger than the shrinkage rate of the wiring layer 240, and when the temperature drops to the same temperature, the shrinkage amount of the insulating layer 250 is larger than that of the wiring layer 240. Therefore, as shown in FIG. 10B, the wiring layer 240 is pulled by the insulating layer 250, and the wiring substrate 300 is warped. When such a warp occurs during the production of the wiring board 300, it is necessary to correct the warp. However, this causes a problem of reducing the efficiency of the manufacturing process and increasing the cost.

  Further, in the configuration described in Patent Document 1 described above, although consideration is given to improvement in handling at the time of conveyance, no consideration is given to the problem of warpage that occurs in the manufacturing process of the wiring board. Therefore, when warpage occurs in the coreless multilayer wiring board in the manufacturing process, it is necessary to correct the warpage, and there is a problem in that the efficiency of the manufacturing process is reduced and the cost is increased.

  Further, even in a wiring board having a core substrate, if the board is warped, it is still necessary to correct the warp, and the reduction in the efficiency of the manufacturing process and the increase in cost are also problematic.

  Therefore, an object of the present invention is to provide a multilayer wiring board that suppresses the occurrence of warping of the wiring board even when the temperature is lowered and does not require correction of the warping even when the wiring board is manufactured.

In order to achieve the above object, a multilayer wiring board according to a first invention is a multilayer wiring board including a wiring layer in which a power plane and / or a ground plane is formed,
The power plane and / or the ground plane is cut along a predetermined cutting line, and is divided into a plurality of power plane pieces and / or ground plane pieces.

  As a result, even if the wiring board is warped due to the difference in thermal expansion coefficient between the metal and the resin, the stress can be released to the portion of the cutting line, and the wiring board can be prevented from greatly warping as a whole. it can.

A second invention is the multilayer wiring board according to the first invention,
The predetermined cutting line is a radial line extending outward from the center of the wiring layer.

  Thereby, the curvature of a wiring board can be suppressed centering on the mounted semiconductor element, and the influence on the mounted semiconductor element can be suppressed.

A third invention is a multilayer wiring board according to the first or second invention,
The predetermined cutting line includes a line that divides the adjacent power plane pieces and / or the ground plane into a substantially line symmetry.

  Thereby, the curvature of a wiring board can be escaped symmetrically to a cutting line, and the curvature of a wiring board can be suppressed effectively.

A fourth invention is the multilayer wiring board according to any one of the first to third inventions,
The plurality of power plane pieces and / or ground plane pieces are substantially congruent.

  This makes it possible to make uniform the warp generated in each power plane piece and / or ground plane piece, and evenly distribute the warp generated in the multilayer wiring board, thereby efficiently suppressing the warp of the entire multilayer wiring board. be able to.

A fifth invention is the multilayer wiring board according to any one of the first to fourth inventions,
The power supply device further includes electrical connection means for electrically connecting predetermined power plane pieces and / or ground plane pieces among the plurality of power plane pieces and / or ground plane pieces.

  As a result, it is possible to electrically form a large-area power plane and / or ground plane, as in the prior art, while efficiently distributing the warp generated in the multilayer wiring board.

A sixth invention is the multilayer wiring board according to the fifth invention,
The electrical connection means is a wiring pattern formed by cutting a part of the cutting line uncut.

  As a result, it is possible to easily maintain the electrical connection between the power plane and / or the ground plane as in the prior art while dispersing the warp in the entire multilayer wiring board.

A seventh invention is the multilayer wiring board according to the fifth or sixth invention,
The electrical connection means includes a wiring layer different from the wiring layer.

  Thereby, the board | substrate curvature can be efficiently suppressed, maintaining the wiring pattern of the power plane and / or ground plane similar to the past using the wiring structure of a multilayer wiring board.

A substrate according to an eighth invention is a substrate comprising a plurality of arranged multilayer wiring boards and a frame portion surrounding the plurality of multilayer wiring boards,
A metal member is attached to the surface of the frame portion,
The metal member is cut and divided by a predetermined cutting line.

  As a result, it is possible to suppress warping of the entire large-sized substrate due to the outer frame portion in a large-sized substrate having a considerable size as a whole, and it is no longer necessary to correct the warp when shipping as a sheet product. , Process efficiency and cost reduction can be achieved.

According to a ninth invention, in the substrate according to the eighth invention,
The predetermined cutting line is formed by extending an array line of the multilayer wiring board outward.

  As a result, stress can be released in a direction that has the least influence on each multilayer wiring board, and warpage of each multilayer wiring board can be reduced.

  ADVANTAGE OF THE INVENTION According to this invention, the curvature of the board | substrate with which the multilayer wiring board and the several multilayer wiring board were arranged can be suppressed.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a plan configuration diagram showing a plane configuration of a wiring layer 40 on which a power plane and / or a ground plane 10 are formed in a multilayer wiring board 100 according to a first embodiment to which the present invention is applied.

  In FIG. 1, the power plane and / or the ground plane 10 is formed in the upper layer or the lower layer of the insulating layer 50, and is a central portion around the virtual semiconductor element 90 mounted on the semiconductor element mounting surface on the surface of the multilayer wiring substrate 100. Except for 30, a wiring pattern in which most of the wiring layer 240 is covered with a metal such as copper or aluminum. The power plane and / or ground plane 10 is not a single continuous solid film as a whole, but four power planes by four cutting lines 20 extending from the central portion 30 to four corners. It is divided into pieces and / or ground plane pieces 11.

  In this way, the power plane and / or the ground plane 10 is not formed by a single solid film covering the entire wiring layer 240, but is appropriately slit-shaped cutting lines at predetermined positions on the power plane and / or the ground plane 10. By providing 20 and comprising a plurality of power plane pieces and / or ground plane pieces 11, thermal stress can be released at the cutting line 20, and warpage of the entire multilayer wiring board 100 can be reduced.

  The thermal stress is caused by the difference in thermal expansion coefficient between the metal and the resin, and when the resin is thermally cured, the resin contracts more than the metal, and the metal formed on the insulating layer 50 of the resin This is because the wiring layer 40 contracts so as to be pulled by the insulating layer 50. For example, when the power plane and / or the ground plane 10 on the wiring layer 40 is copper and the insulating layer 50 is an epoxy resin, the thermal expansion coefficient of copper is 17 to 18 [1 / K]. Therefore, the thermal expansion coefficient of the epoxy resin is about twice the thermal expansion coefficient of copper. In this case, even when the multilayer wiring board 100 is not warped in the manufacturing process of about 150 ° C., if the manufacturing process is completed and the temperature is lowered, the thermal expansion as described above is caused in the multilayer wiring board 100. Deformation stress occurs due to the difference in coefficients.

  Therefore, in the wiring layer 40 in which the power plane and / or the ground plane 10 of the multilayer wiring board 10 is formed, the power plane and / or the ground plane 10 is changed into a small power plane piece and / or ground plane piece 11 by the cutting line 20. If it is divided, the cutting line 20 becomes an escape path for deformation stress, and the degree of deformation of the entire multilayer wiring board 100 can be reduced.

  In FIG. 1, a power plane and / or ground plane 10 is divided into four congruent and symmetric power plane pieces and / or ground plane pieces 11 by four slit-like cutting lines extending from the central portion 30 to four corners. It is divided into The cutting line 20 may be provided at various arbitrary positions. For example, as shown in FIG. 1, the cutting line 20 may be a radial cutting line extending outward from the central portion. For example, when the semiconductor element 90 is mounted in the central portion of the multilayer wiring substrate 100, the warp direction of the multilayer wiring substrate 100 is configured to be symmetric with respect to the semiconductor element 90. The influence on the semiconductor element 90 can be reduced.

  Further, as shown in FIG. 1, the cutting line 20 may be provided at a position where the power plane and / or the ground plane 10 is divided line-symmetrically. As a result, the individual power plane pieces and / or ground plane pieces 11 divided by the cutting line 20 are congruent, and the adjacent power plane pieces and / or ground plane pieces 11 are symmetric with respect to the cutting line 20. The stress escaping from both sides to the line 20 is equal on the left and right, and the stress can be released in a balanced manner on the left and right.

  The power plane and / or the ground plane 10 formed in the wiring layer 40 may be composed of only the power plane, may be composed of only the ground plane, or may be a combination of both. Good. When both the power plane and the ground plane are formed in the wiring layer 40, the power plane 10 and the ground plane 10 are divided from the beginning, and are formed of two wiring pattern pieces. Even in this case, when the two wiring pattern pieces are formed of a solid film, the entire wiring layer 40 is covered with the two wiring pattern pieces, so that the warpage of the substrate also increases. Therefore, as shown in FIG. 1, if the power plane and the ground plane 10 are each composed of two power plane pieces and ground plane pieces 11, warpage of the multilayer wiring board 100 is also reduced by this embodiment. can do.

  Further, the position and number of the cutting lines 20 can be arbitrarily set. For example, the cutting lines 20 can be divided more finely to reduce the size of the individual power plane pieces and / or ground plane pieces 11 and the cutting lines 20. If the number is increased, the deformation of the individual power plane pieces and / or ground plane pieces 11 is reduced, and the number of stress escape paths is increased, so that the warpage of the multilayer wiring board 100 can be further suppressed.

  FIG. 2 is a cross-sectional configuration diagram in which the wiring layer 40 and the insulating layer 50 of the multilayer wiring board 100 according to FIG. 1 are cut along the AA ′ section.

  FIG. 2A is a cross-sectional view showing a state in which the multilayer wiring board 100 is being manufactured at a temperature of about 150.degree. Although the length ratio of the power plane piece and / or the ground plane piece 11 is slightly different from that shown in FIG. In FIG. 2A, the wiring layer 40 is formed on the insulating layer 50, and the power supply plane and / the ground plane 10 are formed on the wiring layer 40. A gap is formed by the cutting line 20 instead of the so-called solid film. In a state where the temperature is about 150 ° C. during the production of the multilayer wiring substrate 100, both the insulating layer 50 and the wiring layer 40 are not contracted, and both are formed as parallel layers.

  FIG. 2B is a cross-sectional configuration diagram of the multilayer wiring board 100 in a state where the temperature is lowered. In FIG. 2B, since the thermal expansion coefficients of the metal and the resin are different, the shrinkage amount of the insulating layer 50 is larger than that of the wiring layer 40 when the resin is cured, but as shown in FIG. In addition, since the power plane and / or ground plane 10 is divided into three power plane pieces and / or ground plane pieces 11 by the slit-shaped cutting line 20, the wiring layer 40 and the insulating layer 50 are deformed in three ways. However, the individual deformation is reduced, and the warpage of the multilayer wiring board 100 as a whole is suppressed to a small level.

  As described above, according to the multilayer wiring board 100 according to the present embodiment, the power plane and / or the ground plane 10 is divided into smaller units by the predetermined cutting line 20, thereby reducing the size of each warp. The warpage of the multilayer wiring board 100 as a whole can be reduced.

  FIG. 3 is a plan configuration diagram of a wiring layer 40a formed with a power plane and / or a ground plane 10a of a multilayer wiring board 100a according to a second embodiment to which the present invention is applied. In FIG. 3, a wiring layer 40a is formed on an insulating layer 50, and four power plane pieces formed on the wiring layer 40a by four radial cutting lines 20a extending from the central portion 30 to four corners. And / or is the same as the power plane and / ground plane 10 according to the first embodiment in that the power plane and / or the ground plane 10a formed of the ground plane piece 11a is formed. This embodiment is different from the first embodiment in that it includes a zigzag line instead of a straight slit. The presence of the via 55 existing in the upper layer or the lower layer of the wiring layer 40 is shown in the portion of the predetermined cutting line 20a where the zigzag line is formed. In addition, you may form the cutting line 20a formed in the zigzag in the curved line which does not have a corner | angular part. In this case, since there is no stress concentration at the corner, it is possible to disperse the stress more suitably and release it.

  As described above, the predetermined cutting line 20a is connected to the via 55 and the desired power plane piece and / or ground plane piece 11a depending on the relationship between the arrangement position of the via 55 and the wiring pattern of the wiring layer 40. You may comprise in such a shape. According to the second embodiment, the line shape of the predetermined cutting line 20a can be a desired line shape according to the wiring pattern, and the stress is released to the cutting line 20a even by the planar configuration of the wiring layer 40. And the curvature of the multilayer wiring board 100a can be reduced.

  FIG. 4 is a plan configuration diagram of a wiring layer 40b formed with a power plane and / or a ground plane 10b of a multilayer wiring board 100b according to a third embodiment to which the present invention is applied.

  In FIG. 4, the power plane and / or ground plane 10b is divided into four power plane pieces and / or ground plane pieces 40b by four cutting lines 20b, which is the same as in the first and second embodiments. However, the cutting line 20 b is different from the first and second embodiments in that the cutting line 20 b extends from the central portion 30 to the midpoint of the four sides forming the wiring layer 40.

  Thus, the cutting line 20b may be a line that divides the power plane and / or the ground plane 10b into four rectangular power plane pieces and / or ground plane pieces 11b. Also in this case, the cutting line 20b is a line that divides the adjacent power plane pieces and / or ground plane pieces 11b symmetrically, and the four power plane pieces and / or ground plane pieces 10b are all congruent. is there. Therefore, the stress applied to each power plane piece and / or ground plane piece 10b is equal, and the stresses escaping to the cutting line 40b are all equal and balanced, so that the warpage of the multilayer wiring board 100b can be appropriately suppressed. it can.

  FIG. 5 is a plan configuration diagram of a wiring layer 40c formed with a power plane and / or a ground plane 10c of a multilayer wiring board 100c according to a fourth embodiment to which the present invention is applied.

  In FIG. 5, the power plane and / or ground plane 10c is cut by eight cutting lines 20c, and is divided into eight power plane pieces and / or ground plane pieces 11c. Is different. Thus, the number of cutting lines 20c may be increased, and the power plane and / or ground plane 10c may be divided into more power plane pieces and / or ground plane pieces 11c. Since the size of each power plane piece and / or ground plane piece 11c can be reduced, the magnitude of stress and deformation applied to each power plane piece and / or ground plane piece 11c can be further reduced. Further, since the number of cutting lines 20c serving as stress escape paths increases, the thermal stress can be released in finer units, and the overall warpage amount of the multilayer wiring board 100c can be reduced.

  In FIG. 5, the cutting line 20 c includes the cutting line 20 extending from the central portion 30 shown in the first embodiment to the four corners of the wiring layer 40 and the cutting portion 20 extending from the central portion 30 shown in the third embodiment. It is a combination with a cutting line 20b extending to the midpoint of the four sides. Thus, all the cutting lines 20c may not be the same, and may be a combination of a plurality of line shapes. By combining the desired cutting lines 20 and 20b, it is possible to configure a wiring pattern of an appropriate power plane and / or ground plane 10c according to the application.

  In FIG. 5, the predetermined cutting lines 20 c divide all adjacent power plane pieces and / or ground plane pieces 11 c in line symmetry, and the individual power plane pieces and / or ground plane pieces 11 c are totally divided. And have a congruent shape. Thereby, the stress which goes to the cutting line 20c can be made equal on both sides of the cutting line 20c, and the curvature of the multilayer wiring board 100c can be suppressed equally in a balanced manner.

  Thus, as described in the first to fourth embodiments, the power plane and / or the ground planes 10, 10a to 10c and the predetermined cutting lines 20, 20a to 20c apply various modes depending on the application. Is possible. In the first to fourth embodiments, the mode in which the power plane pieces and / or the ground plane pieces 11 and 11a to 11c are congruent has been described. The embodiment may be applied. For example, the power plane pieces and / or ground plane pieces 11, 11a to 11c may include power plane pieces and / or ground plane pieces 11, 11a to 11c having different shapes and sizes. Further, the wiring layers 40 and 40a to 40c are not necessarily formed only by the power plane and / or the ground planes 10, 10a to 10c, and may include portions where signal wiring patterns and the like are formed. Good.

  In addition, the multilayer wiring boards 100 and 100a to 100c according to the first to fourth embodiments are optimally applied to a coreless multilayer wiring board that easily causes warpage problems, but are multilayer wiring boards having a core board. Is also preferably applicable. The present invention can be suitably applied not only to a coreless multilayer wiring board having no core substrate but also to a multilayer wiring board having a core substrate.

  FIG. 6 is a diagram for explaining a multilayer wiring board 100d according to a fifth embodiment to which the present invention is applied. In the fifth embodiment, an example of a cross-sectional configuration of a multilayer wiring board 100d including wiring layers 40d and 40e on which power planes and / or ground planes 10d and 10e are formed will be described.

  FIG. 6A is a diagram illustrating a cross-sectional configuration of a multilayer wiring board 100d according to the fifth embodiment. In FIG. 6A, the multilayer wiring board 100d has a terminal pad 60 for mounting a semiconductor element on the surface and a terminal pad 61 for connecting an external terminal on the opposite surface, and is configured as a semiconductor package. Yes. Further, the portion other than the terminal pads 60 on the semiconductor element mounting surface of the multilayer wiring board 100d is covered with the solder resist 70, and similarly, the portions other than the terminal pads 61 on the external terminal connection surface are also covered with the solder resist 71. It has been broken.

  A pre-solder 80 is formed on the terminal pad 60 for mounting the semiconductor element and soldered to the bump 91 formed on the electrode terminal of the semiconductor element 90, and the semiconductor element 90 is mounted on the multilayer wiring board 100d. An underfill resin 95 is filled between the semiconductor element 90 and the multilayer wiring board 100d. On the other hand, solder balls 81 are formed as external connection terminals on the terminal pads 61 for external terminal connection on the opposite surface of the multilayer wiring board 100d, and are configured to be connectable to a mother board or the like. The solder ball 81 may be a solder bump, a pin or a land shape.

  The multilayer wiring board 100d according to the present embodiment may be applied as such a semiconductor package. Next, the multilayer wiring structure of the multilayer wiring board 100d will be described.

  In FIG. 6, a first insulating layer 50 is formed below the terminal pad 60 for mounting a semiconductor element, and a via 55 is formed immediately below the terminal pad 60 of the first insulating layer 50. And filled with metal. A wiring layer 40d in which a power plane and / or a ground plane 10d is formed in the same layer as the metal filled with the via 55 is formed.

  The wiring layer 40d is covered with the second insulating layer 51, and a via 56 for electrical connection with the wiring layer 40d is formed immediately below the wiring layer 40d of the second insulating layer 51. A wiring layer 40e in which a power plane and / or a ground plane 10e is formed is formed in the same layer as the metal layer formed by filling the metal. The wiring layer 40e is covered with the third insulating layer 52, and is electrically connected to the terminal pads 61 for connecting external terminals by vias 57 formed in the third insulating layer 52. . In addition, an opening 31 is formed in the wiring layer 40e for passing the via 56 and the via 57.

  As described above, the power and / or ground planes 10d and 10e may be provided in the inner layer of the multilayer wiring board 100d. The occurrence of warpage of the multilayer wiring board 100d is caused by the difference in the thermal expansion coefficient between the metal and the resin as described above. However, when the pattern of the solid metal film is present in the inner layer of the multilayer wiring board 100d, the multilayer wiring Since the symmetry in the thickness direction (stacking direction) of the substrate 100d is improved, the warpage of the substrate can be reduced.

  In the present embodiment, an example in which two wiring layers 40d and 40e having power planes and / or ground planes 10d and 10e are provided has been described. However, power planes and / or ground planes 10d and 10e are provided. The formed wiring layers 40d and 40e may be a single layer or a plurality of layers. The wiring layers 40d and 40e having the power planes and the ground planes 10d and 10e can be in various modes depending on the use and mode of the multilayer wiring board 100d.

  Next, a planar configuration example of the wiring layers 40d and 40e formed with the power plane and / or the ground planes 10d and 10e of the multilayer wiring board 100d according to the present embodiment will be described.

  FIG. 6B is a diagram illustrating a planar configuration example of the wiring layer 40d on which the power plane and / or the ground plane 10d is formed. In FIG. 6B, the wiring layer 40d has a power plane and / or a ground plane 10d surrounding the periphery of the central portion 30, and the power plane and / or the ground plane 10d is on a diagonal line of the wiring layer 40d. It is divided into four power plane pieces and / or ground plane pieces 11d by four cutting lines 20d.

  With this configuration, even if the thermal expansion coefficient is different between the wiring layer 40d and the upper and lower insulating layers 50 and 51, the generated stress can be released and the warpage of the multilayer wiring board 10d can be reduced. .

  FIG. 6C is a diagram illustrating a planar configuration example of the wiring layer 40e on which the power plane and / or the ground plane 10e is formed. In the wiring layer 40e, a power plane and / or a ground plane 10e is formed so as to surround each of the periphery of the plurality of openings 31 in which the vias 56 are formed. The power plane and / or ground plane 10e is divided into four power plane pieces and / or ground plane pieces 11e by two cutting lines 20e formed on the diagonal line of the wiring layer 40e.

  As described above, the planar configuration of the wiring layer 40e is not limited to the case where the central portion 30 is opened, but may be a mode in which a plurality of openings 31 are provided around the plurality of vias 56. Also in the wiring layer 40e, the power plane and / or the ground plane 10e is cut by a predetermined cutting line 20e, so that the wiring plane 40e is divided into a power plane piece and / or a ground plane piece 11e having a small area, and warping of the multilayer wiring board 100d is performed. Can be reduced.

  As described above, in the fifth embodiment, the wiring layers 40d and 40e on which the power planes and / or the ground planes 10d and 10e are formed are both arranged substantially symmetrically in the thickness direction on the inner layer of the multilayer wiring board 100d. Therefore, the warp of the multilayer wiring board 100d is effectively offset.

  In the fifth embodiment, the wiring layers 40d and 40e on which the power plane and / or the ground planes 10d and 10e are formed use one wiring layer 40d and 40e as a power plane layer and the other wiring layers 40d and 40e. May be used as a ground plane layer, or may be formed as wiring layers 40d and 40e in which a power plane and a power plane are mixed. The combination can be in various modes depending on the application.

  In the fifth embodiment, no wiring layer is provided in addition to the wiring layers 40d and 40e, but another wiring layer is provided and a power plane piece formed in the same wiring layer 40e and 40d using this and a via. And / or the electrical connection between the ground plane pieces 11d and 11e may be achieved. For example, when it is desired to connect all four power plane pieces and / or ground plane pieces 11d of the wiring layer 40d to the same potential, they may be connected via vias and other wiring layers. .

  In addition, among the plurality of power plane pieces and / or ground plane pieces 11d and 11e formed on the same wiring layer 40d and 40e, any power supply plane piece and / or ground plane pieces 11d and 11e are electrically connected. In order to achieve electrical connection, leave a part of the cut lines 20d, 20e between the power plane piece and / or the ground plane pieces 11d, 11e to be electrically connected, so as to make electrical connection. May be.

  As described above, the power plane and / or the ground planes 10d and 10e, which are originally solid films, are divided into a plurality of power plane pieces and / or ground plane pieces 11d and 11e having a small area, and these are electrically connected. By providing the electrical connection means, it is possible to obtain a configuration in which warpage of the multilayer wiring board 100d is suppressed while maintaining the conventional electrical connection relationship.

  In addition, description of the electrical connection in Example 5 can be applied to the multilayer wiring boards 100 and 100a to 100c of Examples 1 to 4 described so far.

  The planar configurations of the wiring layers 40 and 40a to 40c according to the first to fourth embodiments may also be applied to the cross-sectional configuration of the multilayer wiring board 100d according to the fifth embodiment.

  FIG. 7 is a view for explaining a large substrate 200 according to a sixth embodiment to which the present invention is applied. FIG. 7A is a plan view showing a large-sized substrate 200 according to the sixth embodiment. The large size substrate 200 is an aggregate of a plurality of multilayer wiring substrates 100e, and is an aggregate substrate in which wiring layers to be the individual multilayer wiring substrates 100e are formed on the large size substrate 200.

  In the manufacture of the multilayer wiring boards 100 and 100a to 100d described in the first to fifth embodiments, the wiring layers to be the individual multilayer wiring boards 100 and 100a to 100d are formed on the large-sized substrate 200, and finally In some cases, the large-sized substrate 200 is cut to obtain individual multilayer wiring boards 100, 100a to 100d. In the sixth embodiment, an example in which the present invention is applied to the large format substrate 200 in the case of such a manufacturing method will be described. In addition, since various aspects can be applied to each multilayer wiring board applied to the large-sized board 200, the multilayer wiring board 100e and the reference numeral will be collectively referred to hereinafter.

  In FIG. 7A, a large substrate 200 has a portion where a central multilayer wiring substrate 100e is formed, and a frame portion 110 that supports this from the outside in a frame shape. The individual multilayer wiring board 100e may be, for example, a semiconductor package for mounting a semiconductor element, and a wiring layer including a power plane and / or a ground plane is formed in the wiring structure portion. The frame 110 is a support that supports each multilayer wiring board 100e from the outside. In such a large substrate 200, when a power plane and / or a ground plane is formed in the wiring layer of each multilayer wiring substrate 100e, a solid wiring pattern in which a metal member is attached to the frame portion 110 is formed. The

  FIG. 7B is a diagram showing a state in which a metal member is deposited on the surface of the frame portion 110 of the large-sized substrate 200 and a solid wiring pattern is formed. As shown in FIG. 7B, when the multilayer wiring board 100e is manufactured while the solid wiring pattern of the frame portion 110 of the large-sized board 200 is formed, the manufacturing is performed due to the difference in the thermal expansion coefficient between the resin and the metal. The large substrate 200 is warped inside.

  Therefore, as shown in FIG. 7A, the large substrate 200 according to the present embodiment is provided with slits by the cutting line 120 in the frame portion 110 arranged around the large substrate 200 so as to relieve stress. Yes.

  That is, in FIG. 7A, a predetermined cutting line 120 is formed in the outer frame portion 110 that forms the outer frame of the large-sized substrate 200. In the large-sized substrate 200 according to the present embodiment, the cutting line 120 is provided on the extended portion of the vertical and horizontal array lines in the frame portion 110 so as to extend the vertical and horizontal array lines of each multilayer wiring substrate 100e outward. . The vertical and horizontal array lines may be considered as extending four sides of each multilayer wiring board 100e.

  As a result, even if deformation occurs due to the difference in thermal expansion coefficient during the manufacture of the large substrate 200, the stress caused by this escapes to the cutting line 120 and is released, so that warpage of the entire large substrate 200 can be suppressed.

  In the present embodiment, the cutting line 120 is provided on an extension line of the vertical and horizontal array lines of the multilayer wiring board 100e, so that the stress release position has the least influence on each multilayer wiring board 100e. Position. In other words, stress can be escaped not only in the middle of the side of each multilayer wiring board 100e but also in the notch where the multilayer wiring board 100e is adjacent, so that it is difficult to apply stress to the multilayer wiring board 100e itself.

  However, the position of the cutting line 120 is not limited to the present embodiment, and may be provided at an appropriate position depending on the mode.

  For example, the slit-like cutting lines 20 and 20a to 20e as described in the first to fourth embodiments are provided on the power plane and / or the ground plane of each multilayer wiring board 100e formed at the center of the large-sized substrate 200. May be formed. In this case, the cutting line 120 is formed on the frame portion 110 of the large-sized substrate 200 by connecting the cutting lines 20, 20a to 20e to the power plane and / or the ground plane provided in the wiring layer of the individual multilayer wiring board 100e. You may carry out simultaneously when providing.

  FIG. 8 is a view showing a state in which the large substrate 200 is cut into a strip shape. FIG. 8A is a plan configuration diagram showing a strip-shaped substrate 150 in which the large-sized substrate 200 according to the sixth embodiment is cut into strips. As an example, the semiconductor element 90 is mounted in the state of the strip-shaped substrate 150 shown in FIG. 8A, and then cut into individual multilayer wiring boards 100e to complete the semiconductor package.

  FIG. 8B is a diagram showing a strip-shaped substrate 150a in which the frame part 110 is formed in a solid wiring pattern. If the semiconductor element 90 is mounted on each multilayer wiring board 100e in this state, the strip-shaped substrate 150a is warped by heating during mounting, and the semiconductor element 90 cannot be mounted satisfactorily.

  On the other hand, FIG. 8A is a plan view showing the strip-shaped substrate 150 according to the present embodiment. Since the cutting line 120 is included in the frame portion 110, the stress can be released, and the semiconductor element 90 can be mounted satisfactorily. Then, after mounting the semiconductor element 90, the semiconductor package can be cut into individual multilayer wiring boards 100e to obtain a semiconductor package in which the semiconductor element 90 is well mounted.

  As described above, the present invention can be suitably applied not only to the individual multilayer wiring boards 100 and 100a to 100e but also to the large-sized board 200 and the strip-shaped board 150.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

1 is a plan configuration diagram of a wiring layer 40 of a multilayer wiring board 100 according to Example 1. FIG. It is the cross-sectional block diagram which cut the wiring layer 40 and the insulating layer 50 which concern on FIG. 1 in the AA 'cross section. FIG. 2A is a cross-sectional view showing a state in which the multilayer wiring board 100 is being manufactured. FIG. 2B is a cross-sectional view of the multilayer wiring board 100 in a state where warpage has occurred. 6 is a plan configuration diagram of a wiring layer 40a of a multilayer wiring board 100a according to Example 2. FIG. FIG. 6 is a plan configuration diagram of a wiring layer 40b of a multilayer wiring board 100b according to a third embodiment. FIG. 6 is a plan configuration diagram of a wiring layer 40c of a multilayer wiring board 100c according to a fourth embodiment. It is explanatory drawing of the multilayer wiring board 100d which concerns on Example 5. FIG. FIG. 6A is a cross-sectional configuration diagram of a multilayer wiring board 100d according to the fifth embodiment. FIG. 6B is a plan view of the wiring layer 40d. FIG. 6C is a plan configuration diagram of the wiring layer 40e. 10 is a diagram for explaining a large-sized substrate 200 according to Example 6; FIG. 7A is a plan view showing a large-sized substrate 200 according to the sixth embodiment. FIG. 7B is a diagram illustrating a state in which a solid wiring pattern is formed on the frame portion 110 of the large substrate 200. It is the figure which showed the state which cut | disconnected the large format board | substrate 200 in strip shape. FIG. 8A is a plan configuration diagram showing a strip-shaped substrate 150 obtained by cutting the large substrate 200 according to the sixth embodiment into a strip shape. FIG. 8B is a diagram showing a strip-shaped substrate 150a in which the frame part 110 is formed in a solid wiring pattern. It is a plane block diagram of the wiring layer 240 of the conventional multilayer wiring board 300. It is a cross-sectional block diagram of the wiring layer 240 and the insulating layer 250 of the conventional wiring board 300. FIG. 10A is a cross-sectional configuration diagram of the wiring layer 240 and the insulating layer 250 when the wiring board 300 is manufactured. FIG. 10B is a cross-sectional configuration diagram of the wiring layer 240 and the insulating layer 250 in a state where the temperature is lowered.

Explanation of symbols

10, 10a to 10e Power plane, ground plane 11, 11a to 11e Power plane piece, ground plane piece 20, 20a to 20e, 120 Cutting line 30 Center part 31 Opening part 40, 40a to 40e Wiring layer 50, 51, 52 Insulation Layer 55, 56, 57 Via 60, 61 Terminal pad 70, 71 Solder resist 80 Pre-solder 81 Solder ball 90 Semiconductor element 91 Bump 95 Underfill resin 100, 100a to 100e Multilayer wiring board 110 Frame part 150 Strip board 200 Large format board

Claims (9)

A multilayer wiring board including a wiring layer in which a power plane and / or a ground plane is formed,
The multilayer wiring board, wherein the power plane and / or the ground plane is cut along a predetermined cutting line and divided into a plurality of power plane pieces and / or ground plane pieces.   The multilayer wiring board according to claim 1, wherein the predetermined cutting line is a radial line extending outward from the center of the wiring layer.   3. The multilayer wiring board according to claim 1, wherein the predetermined cutting line includes a line that divides the adjacent power plane piece and / or the ground plane piece into substantially line symmetry. 4.   The multilayer wiring board according to claim 1, wherein the plurality of power plane pieces and / or ground plane pieces are substantially congruent.   5. The apparatus further comprises electrical connection means for electrically connecting predetermined power plane pieces and / or ground plane pieces among the plurality of power plane pieces and / or ground plane pieces. The multilayer wiring board according to any one of the above.   6. The multilayer wiring board according to claim 5, wherein the electrical connection means is a wiring pattern formed by cutting a part of the cutting line.   The multilayer wiring board according to claim 5, wherein the electrical connection means includes a wiring layer different from the wiring layer. A plurality of multilayer wiring boards arranged, and a board having a frame portion surrounding the plurality of multilayer wiring boards,
A metal member is attached to the surface of the frame portion,
The metal member is cut and divided by a predetermined cutting line.   9. The substrate according to claim 8, wherein the predetermined cutting line is an extension of an array line of the substrate.

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