CN113032317B - Method and equipment based on server PCIE signal expansion - Google Patents

Method and equipment based on server PCIE signal expansion Download PDF

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Publication number
CN113032317B
CN113032317B CN202110341122.7A CN202110341122A CN113032317B CN 113032317 B CN113032317 B CN 113032317B CN 202110341122 A CN202110341122 A CN 202110341122A CN 113032317 B CN113032317 B CN 113032317B
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oculink
pcie
interface
expansion
main
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CN113032317A (en
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王妍妍
马艳新
吴冬冬
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Beijing Zhongke Flux Technology Co ltd
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Beijing Zhongke Flux Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Information Transfer Systems (AREA)

Abstract

The invention discloses a method and equipment for expanding PCIE signals based on a server, wherein the method is to respectively expand two main Oculink interfaces on the server into two Oculink expansion interfaces, and the expansion method of any main Oculink interface comprises the following steps: the PCIE signal expansion method comprises the steps that a main Oculink interface obtains PCIE multiplied by 4 of two paths from a server host through an Oculink cable and respectively transmits the PCIE multiplied by 4 of the two paths to two PCIE repeaters, and any PCIE repeater expands PCIE multiplied by 4 of the corresponding path into PCIE multiplied by 2 of the two paths and simultaneously transmits the PCIE multiplied by 4 of the corresponding path to the corresponding Oculink expansion interface; the reset signal expansion method comprises the steps that a main Oculink interface transmits two paths of reset signals acquired from a server host to two Oculink expansion interfaces through NMOS drive circuits respectively; the clock signal expansion method is characterized in that two clock chips respectively transmit clock signals acquired from a main Oculink interface to corresponding Oculink expansion interfaces.

Description

Method and equipment based on server PCIE signal expansion
Technical Field
The invention relates to the technical field of computers, in particular to a method and equipment based on server PCIE signal expansion.
Background
In recent years, with the rapid development of intelligent applications, the application of a centralized video supervision system is also more and more widespread, a streaming server is used as a main data processing center, the processing capability of the streaming server is more and more required, when the server needs to increase the performance and the server density, some external expansion devices, such as applications of a standard hard disk-sized accelerator card with U.2 (also called SFF-8639) as an interface, are needed, but due to the limitation of the structural space of the server main board, no more expansion devices can be added, therefore, a PCIE (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, a high-speed serial computer expansion bus standard) adapter card needs to be designed to expand PCIE signals of the server main board, and the use of the acceleration devices is matched, so that the server density is improved and the processing capability of the server is enhanced.
The Oculink is an interface specification supporting PCIE 4.0, which is widely used on a server motherboard, but since the internal space of the server is limited, the configuration of the motherboard interface is limited by a certain condition, and the number of Oculink interfaces that can be used for connecting to external devices is limited, so a method for expanding the Oculink interface on the server motherboard is needed to meet the expansion requirement of more hardware acceleration devices.
Disclosure of Invention
In order to solve the above problems, the present invention provides a method and an apparatus for expanding PCIE signals of a server, which are used for expanding PCIE signals of a server motherboard by expanding two Oculink interfaces into four Oculink interfaces, so as to improve diversity of external devices that can be used with the server, increase server density, and enhance processing capability of the server.
In order to achieve the above objective, the present invention provides a method for expanding PCIE signals on the basis of a server, wherein two main Oculink interfaces on the server are respectively expanded into two Oculink expansion interfaces, and are expanded into four Oculink expansion interfaces in total, and the expansion method for expanding any main Oculink interface into two Oculink expansion interfaces includes a PCIE signal expansion method, a reset signal expansion method, and a clock signal expansion method, wherein:
The PCIE signal expansion method comprises the following specific processes:
step 101: the method comprises the steps that a main Oculink interface obtains PCIE signals from a server host through an Oculink cable, and the obtained PCIE multiplied by 4 paths are respectively transmitted to a first PCIE repeater and a second PCIE repeater;
step 102: any PCIE repeater expands the corresponding one-path PCIE multiplied by 4 into two-path PCIE multiplied by 2 and simultaneously transmits the two-path PCIE multiplied by 2 to the corresponding Oculink expansion interface;
the specific process of the reset signal expansion method comprises the following steps:
Step 200: the main Oculink interface transmits two paths of reset signals acquired from the server host to two Oculink expansion interfaces through NMOS driving circuits respectively; and
The clock signal expansion method comprises the following specific processes:
Step 300: the two clock chips respectively transmit clock signals acquired from the main Oculink interface to the corresponding Oculink expansion interfaces.
In an embodiment of the present invention, the specific transmission process in step 102 is:
The first PCIE repeater expands the corresponding one-path PCIE multiplied by 4 into two-path PCIE multiplied by 2 and transmits the two-path PCIE multiplied by 2 to the first Oculink expansion interface;
the second PCIE relay extends the corresponding one-path pcie×4 to two-path pcie×2, and transmits the two-path pcie×2 to the second Oculink extension interface.
In an embodiment of the present invention, the clock signal transmission process in step 300 is specifically:
The main Oculink interface transmits clock signals to the input ends of the first clock chip and the second clock chip respectively, then the two output ends of the first clock chip input the clock signals to the first Oculink expansion interface, and the two output ends of the second clock chip input the clock signals to the second Oculink expansion interface.
In order to achieve the above object, the present invention further provides a device based on server PCIE signal extension, including:
A board card;
The two main Oculink interfaces are arranged on the board card and are respectively a first main Oculink interface and a second main Oculink interface;
The four PCIE relays are arranged on the board and are respectively a first PCIE relay, a second PCIE relay, a third PCIE relay and a fourth PCIE relay, wherein the first PCIE relay and the second PCIE relay are connected with the first main Oculink interface, and the third PCIE relay and the fourth PCIE relay are connected with the second main Oculink interface;
The four Oculink expansion interfaces are arranged on the board and are respectively a first Oculink expansion interface, a second Oculink expansion interface, a third Oculink expansion interface and a fourth Oculink expansion interface, wherein the four Oculink expansion interfaces are correspondingly connected with the four PCIE relays;
The NMOS driving circuits are respectively a first NMOS driving circuit, a second NMOS driving circuit, a third NMOS driving circuit and a fourth NMOS driving circuit, wherein each NMOS driving circuit is respectively connected with one of the main Oculink interfaces and the corresponding Oculink expansion interface; and
The four clock chips are arranged on the board and are respectively a first clock chip, a second clock chip, a third clock chip and a fourth clock chip, wherein each clock chip is respectively connected with one of the main Oculink interfaces and the corresponding Oculink expansion interface.
In an embodiment of the present invention, each master Oculink interface includes two channels pcie×4.
In an embodiment of the present invention, each Oculink extension interface includes two channels pcie×2.
In an embodiment of the present invention, a specific connection manner between the four Oculink extension interfaces and the four PCIE repeaters is:
The first Oculink expansion interface is connected with the first PCIE repeater, the second Oculink expansion interface is connected with the second PCIE repeater, the third Oculink expansion interface is connected with the third PCIE repeater, and the fourth Oculink expansion interface is connected with the fourth PCIE repeater.
In an embodiment of the present invention, the connection between each NMOS driving circuit and one of the main Oculink interfaces and the corresponding Oculink extension interface is specifically:
The first NMOS drive circuit is respectively connected with the first main Olink interface and the first Olink expansion interface, the second NMOS drive circuit is respectively connected with the first main Olink interface and the second Olink expansion interface, the third NMOS drive circuit is respectively connected with the second main Olink interface and the third Olink expansion interface, and the fourth NMOS drive circuit is respectively connected with the second main Olink interface and the fourth Olink expansion interface.
In an embodiment of the present invention, each clock chip includes an input end and two output ends, and a specific connection manner of each clock chip is:
The input end of the first clock chip and the input end of the second clock chip are both connected to the first main Oculink interface, the two output ends of the first clock chip are connected with the first Oculink expansion interface, and the two output ends of the second clock chip are connected with the second Oculink expansion interface;
The input end of the third clock chip and the input end of the fourth clock chip are both connected to the second main Oculink interface, the two output ends of the third clock chip are connected with the third Oculink expansion interface, and the two output ends of the fourth clock chip are connected with the fourth Oculink expansion interface.
In an embodiment of the present invention, each of the main Oculink interfaces is connected to the server motherboard through an Oculink cable.
Compared with the prior art, the expansion method and the equipment based on the PCIE signals of the server can expand two Oculink interfaces into four Oculink interfaces, and can expand PCIE signals of the server main board on the basis of completing normal communication between the expansion equipment and the server main board, so that the diversity of external equipment which can be matched with the server for use is improved, the density of the server is increased, and the processing capacity of the server is enhanced.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an expansion method for expanding one Oculink interface into two according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an apparatus according to an embodiment of the present invention.
Reference numerals illustrate: 101-a main Oculink interface; 1021-PCIE repeater 1;1022-PCIE repeater 2; 1031-clock chip 1;1032—clock chip 2;1041-Oculink extension interface 1;1042-Oculink extension interface 2; 1051. 1052-NMOS drive circuit; 20-a board card; 2011-master Oculink interface 1;2012—master Oculink interface 2;2021-PCIE repeater 1;2022-PCIE repeater 2;2023-PCIE repeater 3;2024-PCIE repeater 4;2031—clock chip 1;2032—clock chip 2;2033—clock chip 3;2034—clock chip 4;2041-Oculink extension interface 1;2042-Oculink extension interface 2;2043-Oculink extension interface 3;2044-Oculink extension interface 4;2051-NMOS drive circuit 1;2052-NMOS drive circuit 2;2053-NMOS drive circuit 3;2054-NMOS drive circuit 4.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without any inventive effort, are intended to be within the scope of the invention.
Example 1
Fig. 1 is a schematic diagram of an expansion method for expanding one Oculink interface into two according to an embodiment of the present invention, as shown in fig. 1, this embodiment provides a method for expanding PCIE signals based on a server, which expands two main Oculink interfaces on the server into two Oculink expansion interfaces respectively, and expands them into four Oculink expansion interfaces altogether, wherein the expansion method for expanding any main Oculink interface into two Oculink expansion interfaces includes a PCIE signal expansion method, a Reset Signal (RST) expansion method, and a clock signal (CLK) expansion method, where:
the PCIE signal expansion method comprises the following specific processes:
Step 101: the main Oculink interface (Oculink Connector A) (101) acquires PCIE signals from the server host through an Oculink Cable (Cable), and transmits acquired two-path (Lane) PCIE×4 to the PCIE Repeater (Repeater) 1 (1021) and the PCIE Repeater (Repeater) 2 (1022) respectively;
Step 102: any PCIE Repeater (1021 or 1022) expands the PCIE×4 of the corresponding one-channel (Lane) into PCIE×2 of the two-channel (Lane), and transmits the PCIE×2 to the corresponding Oculink expansion interface (1041 or 1042);
in this embodiment, the specific transmission process in step 102 is as follows:
The PCIE Repeater (Repeater) 1 (1021) expands the corresponding one-Lane (Lane) pcie×4 into two-Lane (Lane) pcie×2, and transmits the two-Lane pcie×2 to the Oculink expansion interface (Oculink Connector) 1 (1041);
The PCIE Repeater (Repeater) 2 (1022) extends the corresponding one-Lane (Lane) pcie×4 to two-Lane (Lane) pcie×2 and transmits to the Oculink extension interface (Oculink Connector) 2 (1042).
The specific process of the Reset Signal (RST) expansion method is as follows:
Step 200: the main Oculink interface (Oculink Connector A) (101) transmits two paths of Reset Signals (RST) acquired from the server host to the Oculink expansion interface 1 (1041) and the Oculink expansion interface 2 (1042) through an NMOS (N-Metal-Oxide-Semiconductor) driving circuit respectively;
the specific process of the clock signal (CLK) expansion method is:
Step 300: the two Clock (CLK) chips (1031 and 1032) respectively transmit clock signals (CLK) acquired from the master Oculink interface (Oculink Connector A) (101) to the corresponding Oculink extension interfaces (1041 or 1042), respectively.
In this embodiment, the transmission process of the clock signal (CLK) in step 300 is specifically:
The master Oculink interface (Oculink Connector A) (101) transmits a clock signal (CLK) to the inputs of the Clock (CLK) chip 1 (1031) and the Clock (CLK) chip 2 (1032), respectively, and then two outputs of the Clock (CLK) chip 1 (1031) input the clock signal (CLK) to the Oculink expansion interface 1 (1041), and two outputs of the Clock (CLK) chip 2 (1032) input the clock signal (CLK) to the Oculink expansion interface 2 (1042).
By the expansion of the embodiment, two paths (Lane) pcie×4 of the main Oculink interface (101) are respectively expanded into four paths (Lane) pcie×2 through two PCIE repeaters (repeaters), each two paths (Lane) pcie×2 are integrated into one Oculink expansion interface, the two Oculink expansion interfaces are expanded altogether, and a Reset Signal (RST) and a clock signal (CLK) are also expanded through an NMOS driving circuit (NMOS) and a Clock (CLK) chip, so that each Oculink expansion interface (1041 and 1042) can acquire inputs of the two clock signals (CLK), the two paths of Reset Signals (RST) and the two paths (Lane) pcie×2. Similarly, another main Oculink interface can also expand two Oculink expansion interfaces, so that the expansion of the two main Oculink interfaces into four Oculink expansion interfaces is realized, and more hardware devices can be accessed.
Example two
Fig. 2 is a device architecture diagram of an embodiment of the present invention, as shown in fig. 2, and this embodiment provides a device based on PCIE signal expansion of a server, so as to implement a method for PCIE signal expansion, which includes:
A board (20);
the two main Oculink interfaces are arranged on the board card (20) and are used for being connected with a server main board, and the main Oculink interfaces are respectively a main Oculink interface 1 (2011) and a main Oculink interface 2 (2012);
Four PCIE repeaters (repeaters) disposed on the board (20) for expanding the one-path pcie×4 into two-path pcie×2, which are respectively PCIE Repeater 1 (2021), PCIE Repeater 2 (2022), PCIE Repeater 3 (2023), and PCIE Repeater 4 (2024), wherein PCIE Repeater 1 (2021) and PCIE Repeater 2 (2022) are connected with the main Oculink interface 1 (2011), and PCIE Repeater 3 (2023) and PCIE Repeater 4 (2024) are connected with the main Oculink interface 2 (2012);
Four Oculink expansion interfaces, which are an Oculink expansion interface 1 (2041), an Oculink expansion interface 2 (2042), an Oculink expansion interface 3 (2043) and an Oculink expansion interface 4 (2044) respectively, are arranged on the board (20), wherein the four Oculink expansion interfaces (2041, 2042, 2043 and 2044) are correspondingly connected with four PCIE repeaters (repeaters) (2021, 2022, 2023 and 2024);
A plurality of NMOS driver circuits (2051, 2052, 2053, and 2054) disposed on the board (20) and respectively including an NMOS driver circuit 1 (2051), an NMOS driver circuit 2 (2052), an NMOS driver circuit 3 (2053), and an NMOS driver circuit 4 (2054), wherein each NMOS driver circuit is respectively connected to one of the main Oculink interfaces and the corresponding Oculink extension interface;
Four clock chips, which are respectively clock chip 1 (2031), clock chip 2 (2032), clock chip 3 (2033) and clock chip 4 (2034), are arranged on the board card (20), wherein each clock chip is respectively connected with one of the main Oculink interfaces (2011 or 2012) and the corresponding Oculink expansion interface (2041, 2042, 2043 or 2044).
In the present embodiment, each master Oculink interface (2011 and 2012) includes two channels (Lane) pcie×4.
In the present embodiment, each Oculink extension interface (2041, 2042, 2043, and 2044) includes two-Lane (Lane) pcie×2.
In this embodiment, the specific connection manner between the four Oculink expansion interfaces (2041, 2042, 2043, and 2044) and the four PCIE repeaters (repeaters) (2021, 2022, 2023, and 2024) is as follows:
the Oculink expansion interface 1 (2041) is connected with the PCIE repeater 1 (2021), the Oculink expansion interface 2 (2042) is connected with the PCIE repeater 2 (2022), the Oculink expansion interface 3 (2043) is connected with the PCIE repeater 3 (2023), and the Oculink expansion interface 4 (2044) is connected with the PCIE repeater 4 (2024).
In this embodiment, the connection between each NMOS driving circuit and one of the main Oculink interfaces and the corresponding Oculink expansion interface is specifically:
NMOS drive circuit 1 (2051) is connected with main Oculink interface 1 (2011) and Oculink expansion interface 1 (2041) respectively, NMOS drive circuit 2 (2052) is connected with main Oculink interface 1 (2011) and Oculink expansion interface 2 (2042) respectively, NMOS drive circuit 3 (2053) is connected with main Oculink interface 2 (2012) and Oculink expansion interface 3 (2043) respectively, and NMOS drive circuit 4 (2054) is connected with main Oculink interface 2 (2012) and Oculink expansion interface 4 (2044) respectively.
In this embodiment, each clock chip (2031, 2032, 2033, and 2034) includes an input terminal and two output terminals, and the specific connection manner of each clock chip is:
the input end of the clock chip 1 (2031) and the input end of the clock chip 2 (2032) are both connected to the main Oculink interface 1 (2011), the two output ends of the clock chip 1 (2031) are connected with the Oculink expansion interface 1 (2041), and the two output ends of the clock chip 2 (2032) are connected with the Oculink expansion interface 2 (2042);
The input end of the clock chip 3 (2033) and the input end of the clock chip 4 (2034) are both connected to the main Oculink interface 2 (2012), the two output ends of the clock chip 3 (2033) are connected to the Oculink expansion interface 3 (2043), and the two output ends of the clock chip 4 (2034) are connected to the Oculink expansion interface 4 (2044).
In this embodiment, each main Oculink interface is connected to the server motherboard through an Oculink cable, where the length of each Oculink cable may be customized according to the requirement, and the length of each Oculink cable is not limited in this embodiment, so as to meet the matching requirement of different interfaces according to the actual situation, and has higher flexibility.
Compared with the prior art, the expansion method and the equipment based on the PCIE signals of the server can expand two Oculink interfaces into four Oculink interfaces, and can expand PCIE signals of the server main board on the basis of completing normal communication between the expansion equipment and the server main board, so that the diversity of external equipment which can be matched with the server for use is improved, the density of the server is increased, and the processing capacity of the server is enhanced.
Those of ordinary skill in the art will appreciate that: the drawing is a schematic diagram of one embodiment and the modules or flows in the drawing are not necessarily required to practice the invention.
Those of ordinary skill in the art will appreciate that: the modules in the apparatus of the embodiments may be distributed in the apparatus of the embodiments according to the description of the embodiments, or may be located in one or more apparatuses different from the present embodiments with corresponding changes. The modules of the above embodiments may be combined into one module, or may be further split into a plurality of sub-modules.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. The method for expanding PCIE signals based on the server is characterized in that two main Oculink interfaces on the server are respectively expanded into two Oculink expansion interfaces, and the two Oculink expansion interfaces are expanded into four Oculink expansion interfaces, wherein the expansion method for expanding any main Oculink interface into two Oculink expansion interfaces comprises a PCIE signal expansion method, a reset signal expansion method and a clock signal expansion method, and the expansion method comprises the following steps:
The PCIE signal expansion method comprises the following specific processes:
step 101: the method comprises the steps that a main Oculink interface obtains PCIE signals from a server host through an Oculink cable, and the obtained PCIE multiplied by 4 paths are respectively transmitted to a first PCIE repeater and a second PCIE repeater;
step 102: any PCIE repeater expands the corresponding one-path PCIE multiplied by 4 into two-path PCIE multiplied by 2 and simultaneously transmits the two-path PCIE multiplied by 2 to the corresponding Oculink expansion interface;
the specific process of the reset signal expansion method comprises the following steps:
Step 200: the main Oculink interface transmits two paths of reset signals acquired from the server host to two Oculink expansion interfaces through NMOS driving circuits respectively; and
The clock signal expansion method comprises the following specific processes:
Step 300: the two clock chips respectively transmit clock signals acquired from the main Oculink interface to the corresponding Oculink expansion interfaces.
2. The method of claim 1, wherein the specific transmission procedure of step 102 is:
The first PCIE repeater expands the corresponding one-path PCIE multiplied by 4 into two-path PCIE multiplied by 2 and transmits the two-path PCIE multiplied by 2 to the first Oculink expansion interface;
the second PCIE relay extends the corresponding one-path pcie×4 to two-path pcie×2, and transmits the two-path pcie×2 to the second Oculink extension interface.
3. The method according to claim 1, wherein the clock signal transmission process in step 300 is specifically:
The main Oculink interface transmits clock signals to the input ends of the first clock chip and the second clock chip respectively, then the two output ends of the first clock chip input the clock signals to the first Oculink expansion interface, and the two output ends of the second clock chip input the clock signals to the second Oculink expansion interface.
4. A device for implementing the method of any one of claims 1 to 3 based on server PCIE signal extension, characterized in that it comprises:
A board card;
The two main Oculink interfaces are arranged on the board card and are respectively a first main Oculink interface and a second main Oculink interface;
The four PCIE relays are arranged on the board and are respectively a first PCIE relay, a second PCIE relay, a third PCIE relay and a fourth PCIE relay, wherein the first PCIE relay and the second PCIE relay are connected with the first main Oculink interface, and the third PCIE relay and the fourth PCIE relay are connected with the second main Oculink interface;
The four Oculink expansion interfaces are arranged on the board and are respectively a first Oculink expansion interface, a second Oculink expansion interface, a third Oculink expansion interface and a fourth Oculink expansion interface, wherein the four Oculink expansion interfaces are correspondingly connected with the four PCIE relays;
The four NMOS drive circuits are arranged on the board card and are respectively a first NMOS drive circuit, a second NMOS drive circuit, a third NMOS drive circuit and a fourth NMOS drive circuit, wherein each NMOS drive circuit is respectively connected with one of the main Oculink interfaces and the corresponding Oculink expansion interface; and
The four clock chips are arranged on the board and are respectively a first clock chip, a second clock chip, a third clock chip and a fourth clock chip, wherein each clock chip is respectively connected with one of the main Oculink interfaces and the corresponding Oculink expansion interface.
5. The apparatus of claim 4 wherein each master Oculink interface comprises two lanes PCIE x 4.
6. The apparatus of claim 4 wherein each Oculink expansion interface comprises two channels PCIE x 2.
7. The apparatus of claim 4, wherein the specific connection manner of the four Oculink expansion interfaces and the four PCIE repeaters is:
The first Oculink expansion interface is connected with the first PCIE repeater, the second Oculink expansion interface is connected with the second PCIE repeater, the third Oculink expansion interface is connected with the third PCIE repeater, and the fourth Oculink expansion interface is connected with the fourth PCIE repeater.
8. The apparatus of claim 4, wherein each NMOS driver circuit is connected to one of the main Oculink interfaces and the corresponding Oculink extension interface, respectively, specifically:
The first NMOS drive circuit is respectively connected with the first main Olink interface and the first Olink expansion interface, the second NMOS drive circuit is respectively connected with the first main Olink interface and the second Olink expansion interface, the third NMOS drive circuit is respectively connected with the second main Olink interface and the third Olink expansion interface, and the fourth NMOS drive circuit is respectively connected with the second main Olink interface and the fourth Olink expansion interface.
9. The apparatus of claim 4, wherein each clock chip comprises an input and two outputs, each clock chip being specifically connected in a manner that:
The input end of the first clock chip and the input end of the second clock chip are both connected to the first main Oculink interface, the two output ends of the first clock chip are connected with the first Oculink expansion interface, and the two output ends of the second clock chip are connected with the second Oculink expansion interface;
The input end of the third clock chip and the input end of the fourth clock chip are both connected to the second main Oculink interface, the two output ends of the third clock chip are connected with the third Oculink expansion interface, and the two output ends of the fourth clock chip are connected with the fourth Oculink expansion interface.
10. The device of claim 4, wherein each master Oculink interface is connected to the server motherboard via an Oculink cable.
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