CN112968013A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN112968013A
CN112968013A CN202110161549.9A CN202110161549A CN112968013A CN 112968013 A CN112968013 A CN 112968013A CN 202110161549 A CN202110161549 A CN 202110161549A CN 112968013 A CN112968013 A CN 112968013A
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China
Prior art keywords
metal
redistribution structure
conductive
insulating layer
width
Prior art date
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Pending
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CN202110161549.9A
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English (en)
Inventor
吴澄玮
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Badi Leibo Co
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Badi Leibo Co
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Publication date
Priority claimed from US15/253,011 external-priority patent/US9679872B1/en
Application filed by Badi Leibo Co filed Critical Badi Leibo Co
Publication of CN112968013A publication Critical patent/CN112968013A/zh
Pending legal-status Critical Current

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Abstract

揭示一种半导体器件。所述半导体器件包括重分布结构、处理器芯片和金属柱。所述重分布结构包含连接结构，所述连接结构包含导电单元、焊料凸块、第一绝缘层、第二绝缘层、第三绝缘层、多个第一通孔以及多个第二通孔。所述金属柱具有第一端和第二端。所述金属柱的第一端连接到所述重分布结构。

Description

半导体封装
技术领域
本发明涉及半导体封装技术领域，尤其涉及一种晶圆级芯片尺寸封装(waferlevel chip scale packages(WLCSP))。
背景技术
在半导体产业中，芯片(die)内的集成密度成长迅速。芯片包括大量的主动与被动电子器件，因此可在所述芯片中执行多种功能。可在硅晶圆上通过半导体制程来行程所述电子器件。在完成所述电子器件的制程后，可将所述晶圆分离成多个芯片。之后对每一芯片进行封装处理，进而在所述芯片外形成保护性封装。所述芯片封装也可作为芯片和印刷电路板间的连接介面。积体电路的常见应用包括行动电话系统、电视系统、个人电脑系统与网路系统。
已发展出多种封装类型，例如双列直插管脚封装(DIP)、四方形平面封装(QFP)、球栅阵列(BGA)及晶圆级芯片尺寸封装(WLCSP)。DIP在两平行侧边上有连接管脚。DIP通常使用通孔安装或插座，以供放置于印刷电路板上。DIP通常包括填充于金属引线框架的绝缘材料。
QFP通常会有翅状引线由所述封装的四周延伸。QFP的接点只能位于所述封装的周边区域，因此其管脚数目受限。BGA可使用整个表面以形成接点阵列，而使得其能够提供更高的球数。所述接点阵和所述芯片间的长度较短，这对高速信号传输更为有利。WLCSP的封装器件尺寸和芯片尺寸几乎相等。WLCSP通常小于BGA封装。但是，现存的WLCSP的结构形状不佳，造成信号完整性(integrity)以及结构稳定性不好。所以，业界非常需要新的WLCSP，来达到较佳的信号完整性以及结构稳定性。
发明内容
发明人在观察到上述的技术问题后，提出了本发明，以解决上述的一个或多个技术问题。
本发明的一个目的在于提供一种半导体器件，其重分布结构具有特殊的连接结构，可达到较佳的信号完整性以及结构稳定性。
根据本发明一态样，揭示一种半导体器件。所述半导体器件包括重分布结构、处理器芯片以及金属柱。所述处理器芯片具有有源侧和背侧。所述有源侧朝向第一方向。所述处理器芯片的有源侧连接到所述重分布结构。
所述重分布结构包含连接结构，所述连接结构包含导电单元、焊料凸块、第一绝缘层、第二绝缘层、第三绝缘层、多个第一通孔以及多个第二通孔，所述导电单元具有凸缘,所述导电单元包含折边、倾斜侧壁以及底部，所述焊料凸块位于导电单元上,所述焊料凸块直接接触所述导电单元，所述第一绝缘层在折边下方，所述第二绝缘层在所述导电单元的底部下方,第二绝缘层具有第一通孔区，所述第三绝缘层在所述第二绝缘层之下,所述第三绝缘层具有第二通孔区，所述多个第一通孔位于所述第一通孔区之内,所述多个第一通孔不在所述导电单元的底部下方，所述多个第二通孔位于所述第二通孔区之内,所述第二通孔区在所述导电单元的垂直投影之内。
所述金属柱具有第一端和第二端。所述金属柱的第一端连接到所述重分布结构。所述第一端朝向所述第一方向。
根据本发明另一态样，揭示一种半导体器件。所述半导体器件包括重分布结构、处理器芯片以及金属柱。所述处理器芯片具有有源侧和背侧。所述有源侧朝向第一方向。所述处理器芯片的有源侧连接到所述重分布结构。
所述重分布结构包含连接结构，所述连接结构包含导电单元、焊料凸块、第一绝缘层、第二绝缘层、第三绝缘层、多个第一通孔以及多个第二通孔，所述导电单元具有凸缘,所述导电单元包含折边、倾斜侧壁以及底部，所述焊料凸块位于导电单元上,所述焊料凸块直接接触所述导电单元，所述第一绝缘层在折边下方，所述第二绝缘层在所述导电单元的底部下方,第二绝缘层具有第一通孔区，所述第三绝缘层在所述第二绝缘层之下,所述第三绝缘层具有第二通孔区，所述多个第一通孔位于所述第一通孔区之内,所述多个第一通孔不在所述导电单元的底部下方，所述多个第二通孔位于所述第二通孔区之内,所述第二通孔区在所述导电单元的垂直投影之内。
所述金属柱具有第一端和第二端。所述金属柱的第一端连接到所述重分布结构。所述第一端朝向所述第一方向。
相比于现有技术，本发明的技术方案具备以下有益效果：所述重分布结构具有特殊的连接结构，可达到较佳的信号完整性以及结构稳定性。
附图说明
附图1是半导体器件一实施方式的示意图；
附图2是重分布结构的剖视图；
附图3是另一种重分布结构的剖视图；
附图4是半导体器件一实施方式的示意图；
附图5是接点结构的剖视图；
附图6是另一种接点结构的剖视图；
附图7是一通孔的剖视图与上视图；
附图8是两个通孔的剖视图与上视图；
附图9是两个通孔的剖视图；
附图10是三个通孔的剖视图与上视图；
附图11是通孔区的剖视图和两个通孔的上视图；
附图12是通孔区的剖视图和四个通孔的上视图；
附图13是通孔区孔的剖视图和三个通孔的上视图；
附图14是五个通孔的上视图；
附图15是五个通孔的上视图；
附图16是多个通孔的上视图；
附图17是多个通孔的上视图；
附图18是接点结构的剖视图；
附图19是具有DRAM模块的半导体器件的示意图；
附图20是重分布结构一部分的示意图；
附图21是半导体器件的侧视图；
附图22是芯片和重分布结构间的接点结构的一实施例的示意图；
附图23是芯片和重分布结构间的接点结构的另一实施例的示意图；
附图24是芯片和重分布结构间的接点结构的另一实施例的示意图；
附图25是芯片和重分布结构间的接点结构的另一实施例的示意图；
附图26是芯片和重分布结构间的接点结构的另一实施例的示意图；
附图27是芯片和重分布结构间的接点结构的另一实施例的示意图；
附图28是重分布结构一部分的示意图；
附图29是重分布结构中金属层的一实施例的示意图；
附图30是重分布结构中金属层的另一实施例的示意图；
附图31是重分布结构中金属层的另一实施例的示意图；
附图32是半导体器件的上视图；
附图33是具有DRAM模块的半导体封装的示意图；
附图34是重分布结构的详细图式；
附图35是金属柱的一实施例的示意图；
附图36是金属柱的另一实施例的示意图；
附图37是位于金属柱一端的焊料凸块的示意图；
附图38是位于金属柱一端的焊料凸块的示意图；
附图39是半导体器件的示意图；
附图40是半导体器件的示意图；
附图41是重分布结构的详细图式；
附图42是一导电通孔的上视图及与剖视图；
附图43是一导电通孔的上视图及与剖视图；
附图44是多个导电通孔的剖视图；
附图45是多个导电通孔的剖视图；
附图46是导电通孔的上视图；
附图47是导电通孔的上视图；
附图48是导电通孔的上视图；
附图49是导电通孔的上视图；以及
附图50是导电通孔的上视图。
具体实施方式
附图1是半导体器件一实施例的示意图。附图2是重分布结构的剖视图。附图3是另一种重分布结构的剖视图。附图4是半导体器件一实施方式的示意图。附图5是接点结构的剖视图。附图6是另一种接点结构的剖视图。附图7是一通孔的剖视图与上视图。附图8是两个通孔的剖视图与上视图。附图9是两个通孔的剖视图。
附图10是三个通孔的剖视图与上视图。附图11是通孔区的剖视图和两个通孔的上视图。附图12是通孔区的剖视图和四个通孔的上视图。附图13是通孔区孔的剖视图和三个通孔的上视图。附图14是五个通孔的上视图。附图15是五个通孔的上视图。附图16是多个通孔的上视图。附图17是多个通孔的上视图。附图18是接点结构的剖视图。
根据一实施方式，参照附图1和附图5，揭示一种接点结构500。所述接点结构500包括导电单元205、焊料凸块206、第一绝缘层501、第二绝缘层502、第三绝缘层503以及多个通孔1602。所述导电单元205具有凸缘509。所述导电单元205包括折边506、倾斜侧壁507以及底部508。所述焊料凸块206位于所述导电单元205上。所述焊料凸块206和所述导电单元205直接接触。所述凸缘509在所述折边506与所述倾斜侧壁507接合处为弯曲状(由所述导电单元205上方观察)。
所述第一绝缘层501位于所述折边506下方。所述第二绝缘层502位于所述导电单元205的所述底部508下方。所述第三绝缘层503位于所述第二绝缘层502下方。所述第三绝缘层503具有通孔区512。所述多个通孔1602位于所述通孔区512中。所述通孔区512位于所述导电单元205的垂直投影513内。
所述焊料凸块包括但不限于含铅与不含铅焊料，含铅焊料如铅锡(Pb-Sn)组合物，而不含铅焊料则包括锡、铜、银或“SAC”组合物，以及具有共通熔点且可在电子应用中形成导电焊料连接的其他共熔物。在某些实施方式中，所述导电单元250包括凸块底层金属(under bump metal(UBM))。在某些实施方式中，UBM结构包括一或多金属层，譬如钛层与铜层。所述UBM可以利用沈积法来形成。
在某些实施方式中，参照附图1、附图5和附图16，所述通孔区512是第二通孔区512。所述第二绝缘层502具有第一通孔区511。所述接点结构500包括多个第一通孔1601位于所述第一通孔区511中。所述多个第一通孔1601并不位于所述导电单元205的底部508下方。在某些实施方式中，所述通孔区512位于所述凸缘509的一垂直投影中。
在某些实施方式中，所述第一通孔区511的大部分位于所述底部508及所述倾斜侧壁507下。亦即，所述第一通孔区511的大部分位于所述底部506与倾斜侧壁507的一垂直投影515下。一通孔区是可用以实作通孔的位置。在某些实施方式中，不能在通孔区以外实作通孔。在某些实施方式中，从上方观察，所述垂直投影515为环形。
参照附图5和附图6，从剖视图来看，通孔区516是所述第一通孔区511的两倍大。这表示通孔区516有更多空间以供实作通孔。在第四绝缘层504中形成和所述通孔区516相同的通孔区517。也就是说，所述通孔区517能用以实作的通孔数目和通孔区516中能够实作的通孔数目相同。在某些实施方式中，所述通孔区516中的通孔数目和所述通孔区517中的通孔数目相同。在某些实施方式中，所述通孔区516中的每一个通孔在通孔区517中都有对应的通孔。在某些实施方式中，通孔区516和通孔区517中的对应通孔垂直排列。
所述绝缘层501、502、503及504可以是聚酰亚胺、苯并环丁烯(benzocyclobutene(BCB))、聚苯并二恶唑(PolyBenzobisOxazole(PBO))或具有类似绝缘特性的其他材料。
在某些实施方式中，所述重分布结构102还具有通孔区518。所述通孔区518的大小和通孔区512一样，并允许实作相同数目的通孔。换句话说，当所述通孔区512允许实作4个通孔时，所述通孔区518亦允许实作4个通孔。在某些实施方式中，所述通孔区512中的每一个通孔在通孔区518中有一个对应通孔。在某些实施方式中，所述通孔区512和通孔区518中的对应通孔垂直排列。
参照附图7，通孔701包括折边704、倾斜侧壁705以及底部706。可用两个环来表示所述通孔701的对应上视图。内环703代表凸缘702的上视图。所述凸缘702在所述折边704与所述倾斜侧壁705接合处为弯曲状。外环707是通孔701的圆形边缘的上视图。
在某些实施方式中，参照附图8，所述多个通孔1602包括第一通孔801以及第二通孔802。所述第一通孔801包括第一通孔折边804、第一通孔倾斜壁803以及第一通孔底部807。所述第二通孔802包括第二通孔折边805、第二通孔倾斜壁806以及第二通孔底部808。所述第一通孔折边804和第二通孔折边805有一重叠区域809。在某些实施方式中，所述第一通孔折边804是宽度一致的环状折边。在某些实施方式中，所述第一通孔折边804是宽度不一致的环状折边。
在某些实施方式中，所述第一通孔折边804在第一位置813有第一宽度810，且在第二位置814有第二宽度812。所述第二位置814比起所述第一位置813更接近所述重叠区域809的中心点815。在某些实施方式中，所述第二通孔折边805是宽度一致的环状折边。在某些实施方式中，所述第二通孔折边805是宽度不一致的环状折边。在某些实施方式中，所述第二通孔折边805在第一位置816有第一宽度811，且在第二位置818有第二宽度817。所述第二位置818比起所述第一位置816更接近所述重叠区域809的中心点815。
根据另一实施方式，参照附图1、附图2、附图4以及附图5，揭示一半导体器件100。所述半导体器件100包括芯片101、重分布结构102、印刷电路板401以及非易失性存储模块402。所述芯片101具有有源侧103和背侧104。
所述重分布结构102具有前表面201与后表面202。所述前表面201通过一组金属柱204连接到所述芯片101的有源侧103。所述重分布结构102包括导电单元205、第一焊料凸块206、第一绝缘层501、第二绝缘层502、第三绝缘层503以及多个通孔1602。所述导电单元205具有凸缘509。所述金属柱204可以是铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)或银(Ag)，或其他适当的电性传导材料。
所述导电单元205包括折边506、倾斜侧壁507以及底部508。所述后表面202是所述第一绝缘层501的一个表面。所述第一焊料凸块206位于所述导电单元205上。所述第一焊料凸块206和所述导电单元205直接接触。所述第一绝缘层501位于所述折边506下方。所述第二绝缘层502位于所述导电单元205的底部508下方。所述第三绝缘层503位于所述第二绝缘层502下方。所述第三绝缘层503具有通孔区512。所述多个通孔1602位于所述通孔区512中。所述通孔区512位于所述导电单元205的垂直投影513内。
所述重分布结构102通过所述焊料凸块206连接到所述印刷电路板401。所述非易失性存储模块402通过多个第二焊料凸块403连接到所述印刷电路板401。动态随机存取存储(Dynamic Random Access Memory(DRAM))模块405通过多个第三焊料凸块406及多个金属柱107连接到所述重分布结构102。可利用镀覆法形成所述金属柱107。用以形成所述金属柱107的材料可以是Cu、Al、W、Au、焊料或其他适当的电性传导材料。
在某些实施方式中，所述金属柱107连接到所述重分布结构102以及所述焊料凸块406。可通过所述金属柱107在所述重分布结构102和所述DRAM模块405间传输电子信号。在某些实施方式中，所述非易失性存储模块402是快闪存储器模块。
在某些实施方式中，所述芯片101的背侧104上设有黏着层106。模塑材料105填充于所述芯片101和所述金属柱107间。所述模塑材料105和所述重分布结构102直接接触。所述黏着层106可以是芯片黏附膜(die attach film(DAF))或相似者。所述模塑材料105可以是聚合物复合材料，譬如有填充料的环氧树脂、有填充料的环氧基丙烯酸酯或有适当填充料的聚合物。
在某些实施方式中，参照附图2，所述重分布结构102还包括第四绝缘层504及第五绝缘层505。在所述第二绝缘层502、第三绝缘层503、第四绝缘层504和述第五绝缘层505的表面上形成金属迹线207，以在通孔间形成适当的接点。所述金属迹线207可以是铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)或银(Ag)，或其他适当的电性传导材料。
在某些实施方式中，参照附图2和附图3，不需所述导电单元205。所述焊料凸块206直接连接到所述金属迹线207。在某些实施方式中，所述重分布结构102中有四层或更多的绝缘层。每一绝缘层的金属迹线厚度可以不同。举例来说，在上方绝缘层中的金属迹线厚度可以大于下方绝缘层中的金属迹线厚度。相邻绝缘层中的金属迹线厚度的差异也可以不同。举例来说，将第一绝缘层501的金属迹线厚度和第二绝缘层502的金属迹线厚度两者间的差异定义为第一厚度差异。将第二绝缘层5021的金属迹线厚度和第三绝缘层503的金属迹线厚度两者间的差异定义为第二厚度差异，依此类推。如此一来，可以得到第一厚度差异、第二厚度差异、第三厚度差异等等，依绝缘层数目而定。在某些实施方式中，第一厚度差异、第二厚度差异、第三差异基本上相同。在某些实施方式中，第一厚度差异小于第二厚度差异，且第二厚度差异大于第三厚度差异。换句话说，在所述重分布结构的中间，相邻绝缘层间的金属迹线的厚度可能有更为明显的差异。此种情形有其优点。举例来说，在第一组绝缘层间采用相近的金属迹线厚度，且之后在第二组绝缘层间改用另一种金属迹线厚度可以省去调整每一绝缘层的金属迹线厚度的复杂性。
在某些实施方式中，所述通孔区512是第二通孔区512。所述第二绝缘层502具有第一通孔区511。参照附图16，所述半导体器件100还包括位于所述第一通孔区511中的多个第一通孔1601。所述多个第一通孔1601不是位于所述导电单元205的底部506下方。
根据另一实施方式，参照附图1、附图5和附图9，接点结构500包括导电单元205、焊料凸块206、第一绝缘层501、第二绝缘层502、第三绝缘层503、第一通孔801以及第二通孔802。所述导电单元205具有凸缘509。所述导电单元205包括折边506、倾斜侧壁507以及底部508。所述焊料凸块206位于所述导电单元205上。所述焊料凸块206和所述导电单元205直接接触。
所述第一绝缘层501位于所述折边506下方。所述第二绝缘层502位于所述导电单元205的底部508下方。所述第三绝缘层503位于所述第二绝缘层502下方。
所述第一通孔801具有第一通孔凸缘820。所述第一通孔凸缘820具有第一通孔凸缘直径822。所述第一通孔801具有第一通孔底部边缘818。所述第一通孔801位于所述导电单元205的垂直投影内。所述第二通孔802具有第二通孔凸缘821。所述第二通孔凸缘821具有第二凸缘直径823。所述第二通孔802具有第二通孔底部边缘819。所述第二通孔802位于所述导电单元205的垂直投影内。底部边缘距离824距离是第一通孔底部边缘818和第二通孔底部边缘819间的距离。所述第一凸缘的直径822大于所述底部边缘距离824。
参照附图5、附图6以及附图10，在某些实施方式中，在所述通孔区511内实作了三个通孔1001、1002以及1003。所述三个通孔1001、1002以及1003位于所述导电单元205的垂直投影内。在某些实施方式中，所述三个通孔1001、1002以及1003位于所述凸缘509的垂直投影内。所述通孔1001具有折边1004。所述通孔1002具有折边1005。所述通孔1003具有折边1006。所述折边1004及所述折边1005有一重叠区域1007。所述折边1005及所述折边1006有一重叠区域1008。
藉由所述重叠区域1007及1008，使得所述三个通孔1001、1002以及1003位置更为紧密。所述紧密设置的通孔1001、1002以及1003具有减少应力的功能。对于通孔1002来说，通孔1001和通孔1003的存在使得在通孔1001两侧的表面1010不平整，进而使得施加到所述通孔1002的底部1009的应力减低。所述表面1010是由绝缘层1013上的通孔1001、1003以及迹线207所形成。相似地，施加到通孔1001的底部1011的应力也会减少。施加到通孔1003的底部1012的应力也会减少。
在某些实施方式中，参照附图16，所述接点结构500还包括位于第二绝缘层502内的多个通孔1601。所述第二绝缘层502中没有通孔位于所述导电单元205的底部508下方。在某些实施方式中，所述第一通孔801和所述第二通孔802位于所述凸缘509的垂直投影内。
在某些实施方式中，参照附图8，所述第一通孔801包括第一通孔折边804、第一通孔倾斜壁803以及第一通孔底部807。所述第二通孔802包括第二通孔折边805、第二通孔倾斜壁806以及第二通孔底部808。所述第一通孔折边804和第二通孔折边805具有一重叠区域809。
在某些实施方式中，所述第一通孔折边804是宽度一致的环状折边。在某些实施方式中，所述第一通孔折边804是宽度不一致的环状折边。在某些实施方式中，所述第一通孔折边804在第一位置813具有第一宽度810，并在第二位置814有第二宽度812。所述第二位置814比起第一位置813更接近所述重叠区域809的中心点815。
根据另一实施方式，参照附图1、附图4、附图5以及附图9，半导体器件100包括芯片101、重分布结构102、印刷电路板401、非易失性存储模块402以及DRAM模块405。
所述芯片101具有有源侧103和背侧104。所述重分布结构102具有前表面201和后表面202。所述前表面201通过一组金属柱204连接到所述芯片101的有源侧103。所述重分布结构102包括导电单元205、焊料凸块206、第一绝缘层501、第二绝缘层502、第三绝缘层503、第一通孔801以及第二通孔802。所述后表面202是第一绝缘层501的一表面。
所述导电单元205具有凸缘509。所述导电单元205包括折边506、倾斜侧壁507以及底部508。所述焊料凸块206位于所述导电单元205上。所述焊料凸块206和所述导电单元205直接接触。所述第一绝缘层501位于所述折边506下方。所述第二绝缘层502位于所述导电单元205的底部508下方。所述第三绝缘层503位于所述第二绝缘层502下方。
参照附图5和附图9，所述第一通孔801具有第一通孔凸缘820。所述第一通孔801和第二通孔802实作于通孔区512中。所述第一通孔凸缘820具有第一通孔凸缘直径822。所述第一通孔801具有第一通孔底部边缘818。所述第一通孔801位于所述导电单元205的垂直投影内。所述第二通孔802具有第二通孔凸缘821。所述第二通孔凸缘821具有第二凸缘直径823。所述第二通孔802具有第二通孔底部边缘819。所述第二通孔802位于所述导电单元205的垂直投影内。底部边缘距离824是第一通孔底部边缘818和所述第二通孔底部边缘819间的距离。所述第一凸缘直径822大于所述底部边缘距离824。
参照附图4，所述重分布结构102通过所述焊料凸块206连接到所述印刷电路板401。所述非易失性存储模块402通过多个第二焊料凸块403连接到所述印刷电路板401。参照附图1和附图4，所述DRAM模块405通过多个第三焊料凸块406和多个金属柱107连接到所述重分布结构102。在某些实施方式中，所述第二绝缘层502中没有通孔位于导电单元205的底部508下方。
根据另一实施方式，参照附图1、附图5以及附图9以及附图16、接点结构500包括导电单元205、焊料凸块206、第一绝缘层501、第二绝缘层502、第三绝缘层503、第一通孔801、第二通孔802、第三通孔825以及第四通孔826。
所述导电单元205具有凸缘509。所述导电单元205包括折边506、倾斜侧壁507以及底部508。所述焊料凸块206位于所述导电单元205上。所述焊料凸块206和所述导电单元205直接接触。所述第一绝缘层501位于所述折边506下方。所述第二绝缘层502位于所述导电单元205的底部508下方。所述第三绝缘层503位于所述第二绝缘层502下方。
所述第一通孔801位于所述第三绝缘层503中。所述第一通孔801超过一半位于所述导电单元205的凸缘509的垂直投影内。所述第二通孔802位于所述第三绝缘层503中。所述第二通孔802超过一半位于所述导电单元205的凸缘509的垂直投影内。
所述第三通孔825位于所述第二绝缘层502中。所述第三通孔825超过一半位于所述导电单元205的折边506和倾斜侧壁507的垂直投影内。所述第四通孔826位于所述第二绝缘层502中。所述第四通孔826超过一半位于所述导电单元205的折边506和倾斜侧壁507的垂直投影内。
在某些实施方式中，所述第一通孔801、第二通孔802、第三通孔825以及第四通孔826相对于第一轴827对称。在某些实施方式中，所述第一通孔801、第二通孔802、第三通孔825以及第四通孔826沿着第二轴828排列。在某些实施方式中，所述接点结构500还包括第五通孔830以及第六通孔831。所述第五通孔830超过一半位于所述导电单元205的折边506和倾斜侧壁507的垂直投影内。所述第六通孔831超过一半位于所述折边506以及倾斜侧壁507的垂直投影内。所述通孔801、802、825、826、830以及831可以是铝、铜、钨、金、银，或其他适当的电性传导材料。用以形成所述金属通孔的方法可以是镀覆法。
参照附图5和附图16，在某些实施方式中，在绝缘层504的通孔区519中实作多个通孔。所述绝缘层504位于绝缘层503下方。在某些实施方式中，所述通孔区519中的通孔对应于所述通孔区511中的通孔。在某些实施方式中，所述通孔区511中的通孔和所述通孔区519中的通孔垂直排列。在某些实施方式中，所述通孔区511中的通孔数目和所述所述通孔区519中的通孔数目相同。
在某些实施方式中，所述通孔区519中的通孔排列方式和通孔区511中的通孔的排列方式相同。在某些实施方式中、所述通孔区519中通孔的厚度小于通孔区511中通孔的厚度。在某些实施方式中，参照附图2和附图5所示的导电单元205，通孔区511中的所有通孔、通孔区512中的所有通孔以及通孔区519中的所有通孔通过每一绝缘层中的金属迹线207而电性连接。
在某些实施方式中，参照附图16，所述第三通孔825、第四通孔826、第五通孔830以及第六通孔831相对于中心点829呈对成状。在某些实施方式中，参照附图8，所述第一通孔801包括第一通孔折边804、第一通孔倾斜壁803以及第一通孔底部807。所述第二通孔802包括第二通孔折边805、第二通孔倾斜壁806以及第二通孔底部808，且所述第一通孔折边804和第二通孔折边805有一重叠区域809。
在某些实施方式中，在绝缘层503中实作所述通孔801和通孔802。在绝缘层502中实作所述通孔825和通孔826。参照附图8与附图16，在绝缘层502中实作所述通孔830和通孔831。位于二相邻层中的通孔并未垂直排列。换句话说，位于二相邻层中的通孔彼此间有一位移。在某些实施方式中，通孔801、通孔802、通孔825、通孔826、通孔830、通孔831以及导电单元205都是通过金属迹线207而电性连接。
在某些实施方式中，所述第一通孔801包括第一通孔折边804、第一通孔倾斜壁803以及第一通孔底部807。所述第二通孔802包括第二通孔折边805、第二通孔倾斜壁806以及第二通孔底部808。参照附图11，所述第一通孔折边804的第一边缘832接触到所述第二通孔折边805的第二边缘833。
参照附图9和附图11，所述通孔801和通孔802位于通孔区512中。在某些实施方式中，边缘832不会接触到边缘833。边缘832和边缘833间的距离小于通孔801的凸缘820的直径。边缘832和边缘833间的距离小于通孔802的凸缘821的直径。在某些实施方式中，边缘832和边缘833在一点上接触。在某些实施方式中，通孔801的折边和通孔802的折边重叠，并形成重叠区域809。
紧密地配置所述通孔801和通孔802有助于减低施加到通孔801底部上以及通孔802底部上的应力。对通孔801来说，所述相邻的通孔802在一侧上形成不平整的金属表面。这有助于减少由该侧传递的应力。对通孔802来说，所述相邻的通孔801在一侧上形成不平整的金属表面。这有助于减少由该侧传递的应力。在导电单元205下方配置二或更多个通孔于提升由所述导电单元205至下方通孔的导电度，且同时可以减低应力。
参照附图12，在某些实施方式中，两个通孔1201和1202位于左侧通孔区516中。另两个通孔1203和1204位于右侧通孔区516中。从上方看来，通孔区516形成一环状。从上方看来，通孔区512形成圆圈状。在某些实施方式中，通孔1201和通孔1202间相隔的距离小于通孔1201的凸缘的直径。所述距离亦小于通孔1202的凸缘的直径。在某些实施方式中，通孔1201和通孔1202在一点上接触。在某些实施方式中，所述通孔1201和通孔1202有一重叠区域1205。
参照附图13，在某些实施方式中，在通孔区512中实作三个通孔1301、1302以及1303。在某些实施方式中，所述通孔1301和通孔1302在一点上接触。所述通孔1302和通孔1303在一点上接触。在某些实施方式中，所述通孔1301和通孔1302有一重叠的折边区域1304。所述通孔1302和通孔1303有一重叠的折边区域1305。
参照附图5和附图14，在某些实施方式中，在导电单元205的凸缘509的垂直投影1402内实作五个通孔1401。在某些实施方式中，沿着轴1404实作所述通孔1401中的三个通孔。在某些实施方式中，沿着轴1405实作所述通孔1401中的三个通孔。在某些实施方式中，所有所述通孔1401具有几乎相同的尺寸。在某些实施方式中，每一个所述通孔1401和一相邻的通孔1401有一重叠的折边区域。
参照附图5和附图15，在某些实施方式中，在所述导电单元205的凸缘509的垂直投影1502内实作五个通孔1501。在某些实施方式中，沿着轴1504实作所述通孔1501中的三个通孔。在某些实施方式中，沿着轴1505实作所述通孔1501中的三个通孔。在某些实施方式中，所有所述通孔1501具有几乎相同的尺寸。在某些实施方式中，每一个所述通孔1501和一相邻的通孔1501在一点上接触。
参照附图5和附图16，所述通孔801和通孔802位于所述凸缘509的垂直投影1603内。在某些实施方式中，通孔801的一小部分位于所述凸缘509的垂直投影1603外，且所述通孔801的大部分位于所述垂直投影1603内。在某些实施方式中，通孔802的一小部分位于所述凸缘509的垂直投影1603外，且所述通孔802的大部分位于所述垂直投影1603内。在某些实施方式中，沿着轴828实作所述通孔801、通孔802、通孔825和通孔826。在某些实施方式中，沿着轴827实作所述通孔830和通孔831。
参照附图5和附图17，在某些实施方式中，所述通孔801和通孔802位于所述凸缘509的垂直投影1701内。所述通孔801和通孔802有一重叠的折边区域1702。在某些实施方式中，在所述导电单元205的垂直投影1704内实作多个通孔1703。
根据另一实施方式，参照附图1、附图4、附图5以及附图9与附图16，半导体器件100包括芯片101、重分布结构102、印刷电路板401、非易失性存储模块402以及DRAM模块405。
所述芯片101具有有源侧103和背侧104。所述重分布结构102具有前表面201和后表面202。所述前表面201通过一组金属柱204连接到所述芯片101的有源侧103。所述重分布结构102包括导电单元205、焊料凸块206、第一绝缘层501、第二绝缘层502、第三绝缘层503、第一通孔801、第二通孔802、第三通孔825以及第四通孔826。所述导电单元205具有凸缘509。所述导电单元205包括折边506、倾斜侧壁507以及底部508。
所述焊料凸块206位于所述导电单元205上。所述焊料凸块206和所述导电单元205直接接触。所述第一绝缘层501位于所述折边506下方。所述第二绝缘层502位于所述导电单元205的底部508下方。所述第三绝缘层503位于所述第二绝缘层502下方。所述第一通孔801位于所述第三绝缘层503中。
所述第一通孔801有超过一半位于所述导电单元205的凸缘509的垂直投影内。所述第二通孔802位于所述第三绝缘层503中。所述第二通孔802有超过一半位于所述导电单元205的凸缘509的垂直投影内。所述第三通孔825位于所述第二绝缘层502中。所述第三通孔825有超过一半位于所述导电单元205的折边506和倾斜侧壁507的垂直投影内。所述第四通孔826位于所述第二绝缘层502中。所述第四通孔826有超过一半位于所述导电单元205的折边506和倾斜侧壁507的垂直投影内。
所述重分布结构102通过所述焊料凸块206连接到所述印刷电路板401。所述非易失性存储模块402通过多个第二焊料凸块403连接到所述印刷电路板401。所述DRAM模块405通过多个第三焊料凸块406和多个金属柱107而连接到所述重分布结构102。在某些实施方式中，所述第一通孔801、第二通孔802、第三通孔825以及第四通孔826相对于第一轴827为对称的。
参照附图5和附图18，在所述导电单元205的垂直投影内实作一通孔1801、一通孔1802以及一通孔1803。在所述导电单元205下方实作金属层1804。所述金属层1804和所述导电单元205的底部直接接触。在某些实施方式中，所述金属层1804的一区域面积和所述导电单元205的底部面积大致相等。
在某些实施方式中，所述金属层1804的一区域面积大于所述导电单元205的底部面积。所述金属层1804的区域正好位于所述导电单元205的底部下方，而使得其能够和所述导电单元205的底部形成良好与全面的接触。在某些实施方式中，不会在区1805中实作通孔。所述区1805位于所述导电单元205的底部下方。在某些实施方式中，所述金属层1804连接到所述金属迹线207，而使得所述金属层1804、金属迹线207、通孔1801、通孔1802以及通孔1803都电性连接。在某些实施方式中，金属柱1806位于所述导电单元205上方。在某些实施方式中，以焊料凸块取代所述金属柱1806。
上述实施方式的一个目的是提出一种接点结构，此种接点结构有助于减少半导体封装中的应力。上述实施方式的另一个目的是提出在重分布结构的导电单元下方的一种通孔排置方式，以实现较佳的导电性。上述实施方式的又另一个目的是提出一种接点结构，此种接点结构相对于一中心点为对称的，因而能够实现应力的平衡。
参照附图19和附图20，根据一实施方式，揭示半导体器件1900。所述半导体器件1900包括芯片1901、重分布结构1902、多个导电柱1903、DRAM模块1904以及多个焊料凸块1905。所述芯片1901具有有源侧1906和背侧1907。所述重分布结构1902具有前表面1908和后表面1909。所述重分布结构1902通过多个导电柱2001连接到所述芯片1901。
在某些实施方式中，所述重分布结构1902具有多个子层2002。所述子层2002为绝缘层。每一子层2002包括金属迹线2003和通孔2004。电子信号及电源/接地电平是通过所述金属迹线2003及通孔2004而连接。在某些实施方式中，所述重分布结构1902包括多个导电单元2005及多个焊料凸块2006。每一焊料凸块2006位于其对应的导电单元2005上。在某些实施方式中，所述导电单元为包括凸块底层金属(UBM)层。
在某些实施方式中，所述半导体器件1900包括黏着层1910。所述黏着层1910是芯片黏附膜(DAF)。在某些实施方式中，所述半导体器件1900包括无源器件1911和无源器件1912。所述无源器件1911是电容。所述无源器件1912是电容。在某些实施方式中，所述无源器件1911是电感。所述无源器件1912是电感。在某些实施方式中，所述无源器件1911和所述无源器件1912位于芯片1901的垂直投影1913内。由上方看来，所述垂直投影1913的形状为矩形，因为所述芯片1901是矩形的。
在某些实施方式中，所述无源器件1911通过焊料凸块2009连接到所述重分布结构1902的后表面1909。在某些实施方式中，所述无源器件1911是集成无源器件(Integratedpassive device(IPD))。在某些实施方式中，所述半导体器件1900包括无源器件1914和无源器件1915。所述无源器件1914是电容。所述无源器件1915是电容。在某些实施方式中，所述无源器件1914是电感。所述无源器件1915是电感。在某些实施方式中，所述无源器件1914和无源器件1915位于芯片1901的垂直投影1913内。
在某些实施方式中，所述半导体器件1900包括无源器件1916和无源器件1917。在某些实施方式中，所述无源器件1916是电容。所述无源器件1917是电容。在某些实施方式中，所述无源器件1916是电感。所比述无源器件1917是电感。所述无源器件1916和无源器件1917位于所述重分布结构1902的前表面1908上。
在某些实施方式中，所述无源器件1916和无源器件1917位于所述芯片1901旁。在某些实施方式中，所述无源器件1916和无源器件1917比起任何导电柱1903更靠近所述芯片1901。在某些实施方式中，底部填料1919围绕所述焊料凸块1905。在某些实施方式中，在所述DRAM模块1904和黏着层1910间形成空隙1920。在某些实施方式中，所述空隙1920并未以底部填料1919填充。在某些实施方式中，所述空隙1920也填满底部填料1919。
在某些实施方式中，所述半导体器件1900包括模塑材料1918，其填满所述导电柱1903其中一个和芯片1901间的空隙。在某些实施方式中，所述模塑材料1918围绕所有导电柱1903。在某些实施方式中，所述半导体器件1900包括绝缘层2007，其位于所述重分布结构1902的前表面1908以及所述芯片1901的有源侧1906间。在某些实施方式中，所述绝缘层2007是聚合物层。在某些实施方式中，所述绝缘层2007是聚酰亚胺层。在某些实施方式中，所述绝缘层2007和所述模塑材料1918有相同的材料。在某些实施方式中，所述绝缘层2007围绕位于所述重分布结构1902和芯片1901间的每一导电柱2001。
在某些实施方式中，所述绝缘层2007并未提供信号迹线的布线。也就是说，所述绝缘层2007不具有任何重分布功能。不会基于布线目的而在所述绝缘层2007形成金属迹线。参照附图20和附图24，在某些实施方式中，所述重分布结构1902的前表面1908下方以及所述钝化层2401上方不会提供任何金属迹线的重分布。
参照附图22，在某些实施方式中，所述绝缘层2007位于所述芯片1901的有源侧1906及所述重分布结构1902的前表面1908间。在某些实施方式中，所述绝缘层2007包括聚酰亚胺。在某些实施方式中，所述绝缘层2007和所述重分布结构1902的前表面1908直接接触。在某些实施方式中，所述绝缘层2007和所述芯片1901的有源侧1906直接接触。
参照附图22，所述芯片1901具有芯片边缘2203。所述绝缘层2007具有外边缘2204。所述芯片边缘2203并未与所述绝缘层2007的外边缘2204垂直排列。所述芯片边缘2203以及所述绝缘层2007的外边缘2204间有水平位移2208。
所述水平位移2208的原因在于，在晶圆的切割芯片过程中，所述晶圆的切割道存有聚合物绝缘层2007时，会引发一些问题。若在进行芯片切割过程前，于所述切割道上方形成绝缘层2007，在芯片切割过程中可能无法轻易切割所述绝缘层2007，因为绝缘层2007和芯片1901具备不同的化学与物理性质。在某些情形中，芯片切割过程可能会撕下所述绝缘层2007，并破坏所述半导体器件1900的结构。因此，在形成所述绝缘层2007时，最好使其和芯片1901的边缘2203保持距离。也就是说，所述绝缘层2007最好不要位于靠近所述切割道的区域。
参照附图22，在所述重分布结构1902和芯片1901间形成凹部2205。在某些实施方式中，所述凹部2205由模塑材料1918所填满。在某些实施方式中，所述黏着层1910具有边缘2206。所述黏着层1910的边缘2206和所述芯片边缘2203垂直排列。在某些实施方式中，所述模塑材料1918覆盖所述芯片边缘2203和黏着层1910的边缘2206。在某些实施方式中，所述黏着层的边缘2206并未和芯片边缘2203垂直排列。所述黏着层1910的边缘2206在芯片1901下方产生一凹部2207。在某些实施方式中，所述模塑材料1918填充于所述凹部2207。
参照附图22，所述导电柱2001被绝缘层2007围绕。所述导电柱2001连接到所述重分布结构1902的通孔2004。所述导电柱2001亦连接到所述芯片1901的有源侧1906。所述导电柱2001可用以在所述重分布结构1902和芯片1901间传输电子信号。在某些实施方式中，所述绝缘层2002所用的材料所述绝缘层2007所用材料相同。在此种情形中，所述绝缘层2007和述绝缘层2002具有相同的化学和物理特性，故使得这两层间不会不相配。举例来说，所述绝缘层2007和绝缘层2002有相同的热膨胀系数，所以当环境温度改变时，这种改必会造成翘曲。
参照附图23，在某些实施方式中，所述绝缘层2007并未和所述绝缘层2002直接接触。模塑材料1918填充于所述重分布结构1902的前表面1908间。所述模塑材料1918围绕所述导电柱2001的上方部分。所述绝缘层2007围绕所述导电柱2001的下方部分。
参照附图24，所述芯片1901包括钝化层2401。所述钝化层2401具有边缘2402。所述边缘2402和所述芯片1901的边缘2403垂直排列。在某些实施方式中，所述绝缘层2007具有向外弯曲的表面2405。所述钝化层2401的上方表面2407和所述模塑材料1918直接接触。在某些实施方式中，所述绝缘层2007具有边缘2408。所述边缘2408并未和所述边缘2402垂直排列。在所述边缘2408和边缘2402间有水平位移2409。
参照附图25，在某些实施方式中，所述绝缘层2007具有向外弯曲的表面2501。所述向外弯曲的表面2501和模塑材料1918直接接触。所述向外弯曲的表面2501具有最远点2502。所述最远点2502并不位于所述绝缘层2007和钝化层2401的介面上。所述最远点2502并不位于所述绝缘层2007和所述重分布结构1902的前表面1908的介面上。所述最远点2502并未和所述钝化层2401的边缘2402垂直排列。所述前表面1908、所述向外弯曲的表面2501以及所述钝化层2401形成一凹部2503。
在某些实施方式中，所述凹部2503中填满了模塑材料1918。在所述最远点2502和所述钝化层2401的边缘2402间有水平位移2504。在某些实施方式中，所述钝化层2401的上方表面2505的一部分和模塑材料1918直接接触。
参照附图26，在某些实施方式中，所述绝缘层2007具有向内弯曲的表面2601。所述向内弯曲的表面2601具有最远点2602。所述最远点2602位于所述向内弯曲的表面2601和所述钝化层2401的上方表面间的边界上。所述最远点2602和所述钝化层2401的边缘2402间有水平位移2603。
所述重分布结构1902的前表面1908、向内弯曲的表面2601以及钝化层2401形成一凹部2604。在某些实施方式中，所述凹部2604中填满了所述模塑材料1918。在某些实施方式中，所述最远点2602位于所述向内弯曲的表面2601和重分布结构的前表面1908间的边界上。在这种情形中，在所述最远点2602和重分布结构的前表面1908间有水平位移2603。在这种情形中，所述所述钝化层2401的上方表面2505的一部分和模塑材料1918直接接触。
参照附图27，在某些实施方式中，所述绝缘层2007并未和所述重分布结构1902的前表面1908直接接触。在所述前表面1908和绝缘层2007间有一缝隙2701。在某些实施方式中，所述模塑材料1918填满于所述缝隙2701中。
参照附图28，在某些实施方式中，所述重分布结构1902包括绝缘层2801、绝缘层2802、绝缘层2803以及绝缘层2804。所述重分布结构1902包括金属层2805、金属层2806以及金属层2807。所述金属层2805并未位于绝缘层2801上方。所述金属层2806位于绝缘层2802上方。所述金属层2807并未位于绝缘层2803上方。在所述绝缘层2804上方形成有多个导电单元2005。所述金属层2805通过通孔2004连接到所述导电柱2001。所述金属层2806通过通孔2004连接到所述金属层2805。所述金属层2807通过通孔2004连接到所述金属层2806。
参照附图28，所述金属层2805包括用以传递信号的金属迹线以及用于电源与接地的金属迹线。所述金属层2806包括用以传递信号的金属迹线以及用于电源与接地的金属迹线。所述金属层2807包括用以传递信号的金属迹线以及用于电源与接地的金属迹线。所述金属层2806位于所述金属层2805和金属层2807间，其具有相对较大的金属迹线部分以供电源与接地连接。也就是说，相较于所述金属层2805和金属层2807，金属层2806有更多的电源及接地区。
所述金属层2805的信号布线金属迹线的总长度比金属层2806长。所述金属层2807的信号布线金属迹线的总长度比金属层2806长。所述金属层2806的电源接地迹线或金属区域比金属层2805长。所述金属层2806的电源接地迹线或金属区域比金属层2807长。藉由在中间位置设置较大的电源与接地区域，所述金属层2806有助于对金属层2805和金属层2807传输的信号维持良好的信号完整度。
参照附图28和附图29，所述金属层2806具有电源接地区2901、电源接地区2902以及电源接地区2903。在某些实施方式中，所述电源接地区2901是由网眼状金属层所形成。所述电源接地区2901具有金属板，其带有多个孔洞2904或狭缝2904。所述孔洞2904的宽度通常大于金属迹线2905的宽度。所述金属迹线2905来自电源接地区2901的边界线。所述金属迹线2905亦来自所述多个孔洞2904间的内部线。所述电源接地区2901连接到电源电平或接地电平。
参照附图28和附图29，在某些实施方式中，所述电源接地区2902是由多个金属迹线2905所形成。所述电源接地区2902的金属迹线2905并未形成封闭的边界。所述金属迹线2905是连接到相同的电源电平或相同的接地电平的金属岛。在某些实施方式中，所述金属层2806包括实作在两个电源接地区间的电性隔离的金属岛。举例来说，多个金属岛2908实作在所述电源接地区2901和电源接地区2902间。多个金属岛2908实作在所述电源接地区2902和电源接地区2903间。所述金属岛2908彼此电性隔离，而使得其其不会和另一金属层垂直连接。
在某些实施方式中，可以再具有较大信号金属迹线部分的两金属层间，设置具有较大电源接地区的金属层。举例来说，参照附图28，相较于金属层2807，金属层2806可具有更多的接地区。相较于金属层2805，金属层2806可具有更多的接地区。藉由在具有显着信号金属迹线的两金属层间设置具有明显接地区的金属层，能够防止信号串音，并保持信号完整性。
参照附图30，在某些实施方式中，所述金属层2806包括多个电源接地区。举例来说，所述电源接地区其中一个是由金属元件3001所形成。所述电源接地区其中一个是由金属元件3002所形成。所述电源接地区其中一个是由金属元件3003所形成。所述电源接地区其中一个是由金属元件3004所形成。在某些实施方式中，每一属元件3001为多边体。在某些实施方式中，所述金属元件3001为六边体。在某些实施方式中，每一多边体有超过一半的内角为约120度。在某些实施方式中，所述金属层2806包括两个电源接地区间的多个金属岛2908。
在某些实施方式中，并非每一金属元件都有相同大小。举例来说，一金属元件3003的大小可以是邻近金属元件3003的两倍大。在两个电源接店区中实作金属岛2908的理由在于，这些金属岛2908可在某种程度上防止具有两种不同电压电平的电源接地区间发生意外短路。金属岛2908的尺寸小于金属元件的尺寸。
在某些实施方式中，可将所述金属岛2908实作成围绕一信号迹线。在某些实施方式中，可将所述金属岛2908实作成位于二相邻信号迹线间。在某些实施方式中，可将所述金属岛2908实作成位于信号迹线和电源接地区间。在某些实施方式中，可将所述金属岛2908实作成位于一信号迹线与另一信号迹线间。
在某些实施方式中，所述金属岛2908为电性隔离，且并未连接至其他电源电平或信号迹线。将金属岛实作为围绕一信号迹线的原因在于，其提供某种程度的遮蔽与绝缘效果，而使得被围绕的信号迹线能够具有较佳的信号完整度。实作所述金属岛2908的另一个原因是能够使得金属层206中金属密度更为均匀，以实现较佳的封装品质。
参照附图31，在某些实施方式中，所述金属层2806包括电源接地区3101、电源接地区3102以及电源接地区3103。所述电源接地区3101具有多个孔洞3104。大多数孔洞3104的宽度或直径大于金属迹线3105的宽度。所述金属迹线3105形成每一电源接地区的边界线和内线。在某些实施方式中，所述孔洞的大小不同。举例来说，孔洞3106的尺寸是邻近孔洞的两倍大。
参照附图19、附图20以及附图21，其揭示根据另一实施方式的半导体器件1900。所述半导体器件1900包括重分布结构1902、芯片1901、DRAM模块1904、印刷电路板2101以及非易失性存储模块2102。所述DRAM模块1904通过焊料凸块1905及导电柱1903连接到所述重分布结构1902。所述芯片1901通过导电柱2001连接到所述重分布结构1902。所述重分布结构1902通过所述焊料凸块2006连接到所述印刷电路板2101。所述非易失性存储模块2102通过焊料凸块2103连接到所述印刷电路板2101。
在某些实施方式中，所述半导体器件1900包括DRAM模块1904、芯片1901、重分布结构1902、印刷电路板2101以及非易失性存储模块2102。所述芯片1901位于所述重分布结构1902和DRAM模块1904间。所述DRAM模块1904的面积大于芯片1901的面积。所述重分布结构的面积大于DRAM模块1904面积。所述重分布结构1902连接到印刷电路板2101。所述非易失性存储模块2102连接到印刷电路板2101。所述重分布结构1902通过印刷电路板2101电性连接到非易失性存储模块2102。
参照附图24，所述钝化层2401可具有单一或多层的氮化硅(Si3N4)、二氧化硅(SiO2)、氮氧化硅(SiON)、SiO2/Si3N4，或其他具有介电性质的材料。参照附图20和附图28，所述绝缘层2002、2801、2802、2803以及2804可以是聚酰亚胺、苯并环丁烯(benzocyclobutene(BCB))、聚苯并二恶唑(PolyBenzobisOxazole(PBO))或具有类似绝缘特性的其他材料。参照附图20，所述焊料凸块2006及所述焊料凸块2006包括但不限于含铅与不含铅焊料，含铅焊料如铅锡(Pb-Sn)组合物，而不含铅焊料则包括锡、铜、银或“SAC”组合物，以及具有共通熔点且可在电子应用中形成导电焊料连接的其他共熔物。
参照附图20，所述导电单元2005包括凸块底层金属(under bump metal(UBM))。在某些实施方式中，UBM结构包括一或多金属层，譬如钛层与铜层。所述UBM可以利用沈积法来形成。所述导电柱2001可以是铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)或银(Ag)，或其他适当的电性传导材料。所述模塑材料1918可以是聚合物复合材料，譬如有填充料的环氧树脂、有填充料的环氧基丙烯酸酯或有适当填充料的聚合物。参照附图20和附图28，所述金属迹线2003、通孔2004、金属层2805、2806以及2807可以是(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)或银(Ag)，或其他适当的电性传导材料。
附图33是具有DRAM模块的半导体封装。附图34绘示较为详细的重分布结构。附图35绘示金属柱的一实施例。附图36绘示金属柱的另一实施例。附图37绘示位于金属柱一端的焊料凸块。附图38绘示位于金属柱一端的焊料凸块。附图39是半导体器件的示意图。
根据一实施方式，参照附图33、附图34以及附图36，半导体封装3300包括重分布结构3302、处理器芯片3303以及金属柱3307。所述金属柱3307的长度大于处理器芯片3303的厚度。所述金属柱3307设置于处理器芯片3303旁。所述处理器芯片3303具有有源侧3304和背侧3305。所述有源侧3304朝向第一方向3306。所述处理器芯片3303的有源侧3304连接到所述重分布结构3302。
所述金属柱3307具有第一端3308以及第二端3309。所述金属柱3307连接到所述第一端3308的重分布结构3302。所述第一端3308朝向第一方向3306。所述第一端3308有第一宽度3502。所述第二端3309有第二宽度3503。所述第一宽度3502大于第二宽度3503。所述金属柱3307具有侧表面3314。所述侧表面3314向内弯曲。
所述金属柱3307可利用镀覆法形成。所述金属柱3307所用材料可以是Cu、Al、W、Au、焊料或其他适当的电性传导材料。在某些实施方式中，所述金属柱3307中的材料均匀分布。也就是说，所述金属柱3307不包含以两种不同金属材料的混合物而形成的不均匀分布。所述处理器芯片3303包括至少一图形处理单元(graphics processing unit(GPU))。
参照附图36，所述金属柱3307的结构可以在两端提供较大的连接区域。此种较大的连接区域使得在所述金属柱3307的两端形成电性接点的工艺较为容易。
在某些实施方式中，参照附图34，所述半导体封装3300还包括一组金属通孔3406。该组金属通孔3406连接于所述处理器芯片3303的有源侧3304和重分布结构3302间。可利用镀覆法来形成所述金属通孔3406。所述金属通孔3406的材料可以是铜或铝或与其相似者。
参照附图37，在某些实施方式中，所述半导体封装3300还包括绝缘层3601，其位于所述半导体封装3300的一表面上。所述绝缘层3601有至少一开口3602。所述绝缘层3601在围绕该开口3602处具有向外弯曲的表面3605。所述绝缘层3601可以是聚酰亚胺、苯并环丁烯(benzocyclobutene(BCB))、聚苯并二恶唑(PolyBenzobisOxazole(PBO))或具有类似绝缘特性的其他材料。
参照附图37，在某些实施方式中，所述半导体封装3300还包括位于开口3602上的焊料凸块3603。在某些实施方式中，所述绝缘层3601是聚酰亚胺层。在某些实施方式中，参照附图38，所述开口3602有一开口宽度3604。所述开口宽度3604小于金属柱3307的第二宽度3503。在某些实施方式中，参照附图33，所述半导体封装3300还包括黏着层3311，其位于所述处理器芯片3303的背侧3305上。所述黏着层3311可以是芯片黏附膜(DAF)或与其相似者。
根据另一实施方式，参照附图33、附图34以及附图36，半导体封装3300包括重分布结构3302、处理器芯片3303以及金属柱3307。所述金属柱3307设置于处理器芯片3303旁。所述金属柱3307的长度大于处理器芯片3303的厚度。所述处理器芯片3303具有有源侧3304和背侧3305。所述有源侧3304朝向第一方向3306。所述处理器芯片3303的有源侧3304连接到重分布结构3302。
所述金属柱3307具有第一端3308、第二端3309和腰部3310。所述金属柱3307以第一端3308连接到所述重分布结构3302。所述第一端3308朝向第一方向3306。所述第一端3308有第一宽度3502。所述第二端3309有第二宽度3503。所述腰部3310有腰部宽度3501。所述第一宽度3502大于腰部宽度3501。所述第二宽度3503大于腰部宽度3501。所述金属柱3307具有侧表面3314。所述侧表面3314向内弯曲。
在某些实施方式中，参照附图33，所述半导体封装3300还包括模塑材料3312，填充于所述处理器芯片3303和金属柱3307间。所述模塑材料3312可以是聚合物复合材料，譬如有填充料的环氧树脂、有填充料的环氧基丙烯酸酯或有适当填充料的聚合物。
在某些实施方式中，在所述处理器芯片3303和重分布结构3302间没有焊料。在某些实施方式中，和所述重分布结构3302平行并穿过处理器芯片3303一侧表面的一假想平面3313不会和焊料相交。
在某些实施方式中，参照附图34，所述重分布结构3302还包括第一子层3401、第二子层3402以及第三子层3403。在某些实施方式中，所述重分布结构3302还包括第四子层3404以及第五子层3405。所述第一子层3401、第二子层3402、第三子层3403、第四子层3404以及第五子层3405的材料可以是聚酰亚胺、苯并环丁烯(benzocyclobutene(BCB))、聚苯并二恶唑(PolyBenzobisOxazole(PBO))或具有类似绝缘特性的其他材料。
在某些实施方式中，所述半导体封装3300还包括绝缘层3601，其位于半导体封装3300的一表面上。所述绝缘层3601有至少一开口3602。所述绝缘层3601在围绕开口3602处有向外弯曲的表面3605。在某些实施方式中，所述半导体封装还包括位于开口3602上的焊料凸块3603。
根据另一实施方式，参照附图33，所述半导体封装3300包括重分布结构3302、处理器芯片3303以及金属柱3307。所述金属柱3307设置于所述处理器芯片3303旁。所述金属柱3307的长度大于处理器芯片3303的厚度。所述处理器芯片3303具有有源侧3304和背侧3305。所述有源侧3304朝向第一方向3306。所述处理器芯片3303的有源侧3304连接到所述重分布结构3302。
参照附图36，所述金属柱3307具有第一端3308、第二端3309和腰部3310。所述金属柱3307的第一端3308连接到所述重分布结构3302。所述第一端3308朝向第一方向3306。所述第一端3308有第一宽度3502。所述第二端3309有第二宽度3503。所述腰部3310有腰部宽度3501。所述第一宽度3502大于第二宽度3503。所述第二宽度3503大于腰部宽度3501。所述金属柱3307具有侧表面3314。所述侧表面3314向内弯曲。
在某些实施方式中，所述半导体封装3300还包括模塑材料3312。所述模塑材料3312围绕所述金属柱3307。在某些实施方式中，所述金属柱3307是铜柱。在某些实施方式中，所述金属柱3307和模塑材料3312直接接触，且在模塑材料3312和金属柱3307间没有绝缘层。所述金属柱3307不会穿过硅基板。
在某些实施方式中，参照附图34，所述重分布结构3302还包括第一子层3401、第二子层3402以及第三子层3403。在某些实施方式中，所述第一子层3401包括一组第一金属迹线3407。所述第二子层3402包括一组第二金属迹线3408。所述第三子层3403包括一组第三金属迹线3409。在某些实施方式中，所述重分布结构3302还包括第四子层3404和第五子层3405。
在某些实施方式中，所述第四子层3404包括一组第四金属迹线3410，且第五子层3405包括一组第五金属迹线3411。所述第一迹线3407、第二迹线3408、第三迹线3409、第四迹线3410以及第五迹线3411的材料可以是铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)或银(Ag)，或其他适当的电性传导材料。
在某些实施方式中，参照附图34，所述半导体封装3300还包括模塑材料3412，其填充于处理器芯片3303和第一子层3401间。在某些实施方式中，所述半导体封装3300还包括一组金属通孔3406，其连接于重分布结构3302和处理器芯片3303间。在某些实施方式中，所述处理器芯片3303还包括一组金属垫3413。该组金属垫3413连接到该组金属通孔3406。
根据一实施方式，参照附图33、附图34、附图36、附图37以及附图39，半导体器件700包括重分布结构3302、处理器芯片3303、金属柱3307、DRAM模块3315、印刷电路板3901以及快闪存储器3902。所述金属柱3307设置于处理器芯片3303旁。所述金属柱3307的长度大于处理器芯片3303的厚度。所述处理器芯片3303具有有源侧3304和背侧3305。所述有源侧3304朝向第一方向3306。所述处理器芯片3303的有源侧3304连接到重分布结构3302。
所述金属柱3307具有第一端3308以及第二端3309。所述金属柱3307的第一端3308连接到重分布结构3302。所述第一端3308朝向第一方向3306。所述第一端3308有第一宽度3502。所述第二端3309有第二宽度3503。所述第一宽度3502大于第二宽度3503。所述金属柱3307具有侧表面3314。所述侧表面3314向内弯曲。
所述DRAM模块3315通过一组第一焊料凸块3603连接到半导体封装3300。所述印刷电路板3901通过一组第二焊料凸块3904连接到重分布结构3302。所述快闪存储器3902通过一组第三焊料凸块3905连接到印刷电路板3901。
在某些实施方式中，所述第一焊料凸块3603的第一尺寸小于第二焊料凸块3904的第二尺寸。在某些实施方式中，所述第一焊料凸块3603的第一尺寸小于第三焊料凸块3905的第三尺寸。
所述第一焊料凸块3603、第二焊料凸块3904以及第三焊料凸块3905的材料可以是任何金属或导电材料，如锡(Sn)、铅(Pb)、金(Au)、银(Ag)、铜(Cu)、锌(Zn)、铋(Bi)及其合金，且有可任选的流动性材料(flux material)。举例来说，所述焊料可以是共熔Sn/Pb、高铅或无铅。
根据另一实施方式，参照附图33、附图34以及附图35，所述半导体封装3300包括重分布结构3302、处理器芯片3303以及金属柱3307。所述处理器芯片3303具有有源侧3304和背侧3305。所述有源侧3304朝向第一方向3306。所述处理器芯片3303的有源侧3304连接到所述重分布结构3302。
所述金属柱3307具有第一端3308、第二端3309和腰部3310。所述金属柱3307的第一端3308连接到重分布结构3302。所述第一端3308朝向第一方向3306。所述第一端3308有第一宽度3502。所述第二端3309有第二宽度3503。所述腰部3310有腰部宽度3501。所述第一宽度3502小于腰部宽度3501。所述第二宽度3503小于腰部宽度3501。所述金属柱3307具有侧表面3314。所述侧表面3314向外弯曲。
参照附图35，在某些实施方式中，所述金属柱3307的材料可以是焊料。可利用雷射开孔或微影技术形成用以容置焊料的空隙。在某些实施方式中，所述金属柱3307的材料可以是铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)或银(Ag)，或其他适当的电性传导材料。
所述半导体封装3300的某些实施方式提出的金属柱3307在两端有较大的连接区域。所述半导体封装的某些实施方式提出的金属柱3307能够通过模塑材料3312连接到DRAM模块3315。所述半导体封装3300的某些实施方式提出的金属柱3307在连接到重分布结构3302的一端有较大的连接区域。
附图40是半导体器件的示意图。附图41绘示较为详细的重分布结构。附图42是导电通孔的上视图和剖视图。附图43是导电通孔的上视图和剖视图。附图44是多个导电通孔的剖视图。附图45是多个导电通孔的剖视图。附图46是导电通孔的上视图。附图47是导电通孔的上视图。附图48是导电通孔的上视图。附图49是导电通孔的上视图。
根据一实施方式，参照附图42，导电通孔4106包括底部4201和环状折边4203。所述底部4201为杯形。所述底部4201具有凸缘4202。所述环状折边4203连接到底部4201的凸缘4202。所述环状折边4203具有第一开口4204。
在某些实施方式中，所述导电通孔4106还包括第二开口4206。所述第一开口4204和第二开口4206相对于底部4201的中心点4205为对称的。在某些实施方式中，所述导电通孔4106是铜通孔。
根据另一实施方式，参照附图41、附图42以及附图43，重分布结构4100包括第一子层4101以及第二子层4102。所述第一子层4101包括第一导电通孔4106。
所述第二子层4102位于第一子层4101上。所述第二子层4102包括第二导电通孔4107。所述第二导电通孔4107的形状和结构与第一导电通孔4106类似。所述第二导电通孔4107包括底部4201和环状折边4203。所述底部4201为杯形。所述底部具有凸缘4202。所述环状折边4203连接到底部4201的凸缘4202。所述环状折边4203具有至少一开口4204。
在某些实施方式中，所述第一导电通孔4106包括底部4201和环状折边4203。所述底部4201为杯形。所述底部具有凸缘4202。所述环状折边4203连接到底部4201的凸缘4202。所述环状折边4203具有至少一开口4204。
在某些实施方式中，参照附图41和附图42，所述重分布结构4100还包括第三子层4103。所述第三子层4103包括第三导电通孔4108。所述第三导电通孔4108和第一导电通孔4106类似，其包括底部4201和环状折边4203。所述底部4201为杯形。所述底部4201具有凸缘4202。所述环状折边4203连接到底部4201的凸缘4202。所述环状折边4203具有至少一开口4204。
参照附图43，所述第一开口4204有第一内边缘4207。所述第二开口有第二内边缘4208。所述第一内边缘4207沿着第一轴4209。所述第二内边缘4208沿着第二轴4210。所述导电通孔4106在第一轴4209和第二轴4210间有一内边缘距离4211。
在某些实施方式中，参照附图43、附图44以及附图45，所述第一导电通孔4106有第一内边缘距离4211。所述第二导电通孔4107有第二内边缘距离4212。所述第三导电通孔4108有第三内边缘距离4213。在某些实施方式中，所述第一内边缘距离4211小于第三内边缘距离4213。
在某些实施方式中，参照附图41和附图42，所述重分布结构4100还包括第四子层4104。所述第四子层4104包括第四导电通孔4109。所述第四导电通孔4109与所一导电通孔4106相似，其包括底部4201和环状折边4203。所述底部4201为杯形。所述底部4201具有凸缘4202。所述环状折边4203连接到底部4201的凸缘4202。所述环状折边4203具有至少一开口4204。
在某些实施方式中，参照附图41和附图42，所述重分布结构4100还包括第五子层4105。所述第五子层4105包括第五导电通孔4110。所述第五导电通孔4110与所述第一导电通孔4106类似，其包括底部4201和环状折边4203。所述底部4201为杯形。所述底部4201具有凸缘4202。所述环状折边4203连接到底部4201的凸缘4202。所述环状折边4203具有至少一开口4204。
在某些实施方式中，参照附图43、附图44以及附图45，所述第四导电通孔4109具有第四内边缘距离4214。所述第五导电通孔4110具有第五内边缘距离4215。在某些实施方式中，所述第一内边缘距离4211小于第二内边缘距离4212。在某些实施方式中，所述第二内边缘距离4212小于第三内边缘距离4213。在某些实施方式中，所述第三内边缘距离4213小于第四内边缘距离4214。在某些实施方式中，所述第四内边缘距离4214小于第五内边缘距离4215。
在某些实施方式中，参照附图41和附图46，所述第一导电4106、第二导电通孔4107、第三导电通孔4108、第四导电通孔4109以及第五导电通孔4110中的至少一个是导电通孔4600。所述导电通孔4600具有开口4601。所述开口4601相对于中心点4602是对称的。
在某些实施方式中，参照附图41和附图47，所述第一导电4106、第二导电通孔4107、第三导电通孔4108、第四导电通孔4109以及第五导电通孔4110中的任一个可以是一导电通孔4700。所述导电通孔4700具有开口4701。所述开口4701相对于中心点4702是对称的。所述开口4702的形状为矩形。
在某些实施方式中，所述第一导电4106、第二导电通孔4107、第三导电通孔4108、第四导电通孔4109以及第五导电通孔4110中的任一个可以是一导电通孔4800。所述导电通孔4800具有开口4801及开口4803。所述开口4801及开口4803相对于中心点4802是对称的。所述开口4803的形状为矩形。所述开口4801的形状为梯形。
在某些实施方式中，参照附图41和附图49，所述第一导电4106、第二导电通孔4107、第三导电通孔4108、第四导电通孔4109以及第五导电通孔4110中的任一个可以是一导电通孔4900。所述导电通孔4900具有开口4901及开口4903。所述开口4901及开口4903相对于中心点4902是对称的。所述开口4903的形状为矩形。
根据另一实施方式，参照附图40、附图41、附图42以及附图46，半导体器件4000包括芯片4001、重分布结构4100、金属柱4007以及存储模块4010。所述芯片4001具有有源侧4003和背侧4004。
所述重分布结构4100具有前侧4005和背侧4006。所述重分布结构4100的前侧4005通过一组金属柱4301接到芯片4001的有源侧4003。所述重分布结构4100包括一导电通孔4600。所述导电通孔4600具有至少一开口4601。
所述金属柱4007具有第一端4008和第二端4009。所述金属柱4007的第一端4008连接到重分布结构4100的前侧4005。所述存储模块4010通过焊料凸块4011连接到金属柱4007。
在某些实施方式中，参照附图47、附图48以及附图49，所述重分布结构4100包括一导电通孔4700。所述导电通孔4700具有至少一开口4701。在某些实施方式中，所述重分布结构4100包括一导电通孔4800。所述导电通孔4800具有至少一开口4801。在某些实施方式中，所述重分布结构4100包括一导电通孔4900。所述导电通孔4900具有至少一开口4901。
在某些实施方式中，参照附图49，所述开口4901具有内端4904和外端4905。所述内端4904具有第一曲度。所述外端4905具有第二曲度。所述第一曲度大于第二曲度。
在某些实施方式中，所述开口4801的形状为梯形。所述开口4801具有内侧4804和外侧4805。所述内侧4804具有第一宽度。所述外侧4805具有第二宽度。所述第一宽度小于第二宽度。
在某些实施方式中，参照附图41和附图46，所述重分布结构4100包括第一子层4101。所述导电通孔4600形成于第一子层4101中。在某些实施方式中，所述第一子层4101包括聚酰亚胺，且聚酰亚胺填满开口4601。在某些实施方式中，所述重分布结构4100还包括第二子层4102。所述导电通孔4600形成于第二子层4102中。
在某些实施方式中，所述第二子层4102包括聚酰亚胺，且聚酰亚胺填满开口4601。在某些实施方式中，所述重分布结构4100还包括第三子层4103。所述导电通孔4600形成于第三子层4103中。在某些实施方式中，所述第三子层4103包括聚酰亚胺，且聚酰亚胺填满开口4601。
在某些实施方式中，所述重分布结构4100还包括第四子层4104。所述导电通孔4600形成于第四子层4104中。在某些实施方式中，所述第四子层4104包括聚酰亚胺，且聚酰亚胺填满开口4601。在某些实施方式中，所述重分布结构4100还包括第五子层4105。所述导电通孔4600形成于第五子层4105中。
在某些实施方式中，所述第五子层4105包括聚酰亚胺，且聚酰亚胺填满开口4601。在某些实施方式中，所述半导体器件4000还包括黏着层4012，其位于芯片4001的背侧4004上。在某些实施方式中，所述半导体器件4000还包括模塑材料4013，其填满于金属柱4007和芯片4001间。
参照附图46、附图47、附图48、附图49以及附图50，可将所述开口4601、4701、4801、4803、4901、4903以及5001的任一个实作成所述第一导电通孔4106、第二导电通孔4107、第三导电通孔4108、第四导电通孔4109以及第五导电通孔4110。
所述第一子层4101、第二子层4102、第三子层4103、第四子层4004以及第五子层4005的材料可以是聚酰亚胺、苯并环丁烯(benzocyclobutene(BCB))、聚苯并二恶唑(PolyBenzobisOxazole(PBO))或具有类似绝缘特性的其他材料。
所述第一导电通孔4106、第二导电通孔4107、第三导电通孔4108、第四导电通孔4109以及第五导电通孔4110的材料可以是铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)或银(Ag)，或其他适当的电性传导材料。
可利用镀覆法形成所述金属柱4007。所述金属柱4007的材料可以是Cu、Al、W、Au、焊料或其他适当的电性传导材料。在某些实施方式中，所述金属柱4007中的材料均匀分布。也就是说，所述金属柱4007不包含以两种不同金属材料的混合物而形成的不均匀分布。
可利用镀覆法形成所述第一导电通孔4106、第二导电通孔4107、第三导电通孔4108、第四导电通孔4109以及第五导电通孔4110。可利用Cu、Al、W、Au、焊料或其他适当的电性传导材料进行镀覆法可。
在某些实施方式中，所述第一子层4101、第二子层4102、第三子层4103、第四子层4104以及第五子层4105中的任一个可包含一导电通孔4700。所述导电通孔4700具有开口4701。所述开口4701相对于中心点4702为对称的。所述开口4701的形状为矩形。聚酰亚胺填满于所述开口4701中。在某些实施方式中，可利用苯并环丁烯(benzocyclobutene(BCB))、聚苯并二恶唑(PolyBenzobisOxazole(PBO))或具有类似绝缘特性的其他材料来取代聚酰亚胺。
在某些实施方式中，所述第一子层4101、第二子层4102、第三子层4103、第四子层4104以及第五子层4105中的任一个可包含一导电通孔4800。所述导电通孔4800具有开口4801和开口4803。所述开口4801和开口4803相对于中心点4802为对称的。聚酰亚胺填满于所述开口4801和开口4803中。在某些实施方式中，可利用苯并环丁烯(benzocyclobutene(BCB))、聚苯并二恶唑(PolyBenzobisOxazole(PBO))或具有类似绝缘特性的其他材料来取代聚酰亚胺。
在某些实施方式中，所述第一子层4101、第二子层4102、第三子层4103、第四子层4104以及第五子层4105中的任一个可包含一导电通孔4900。所述导电通孔4900具有开口4901和开口4903。所述开口4901和开口4903相对于中心点4902为对称的。聚酰亚胺填满于所述开口4901和开口4903中。在某些实施方式中，可利用苯并环丁烯(benzocyclobutene(BCB))、聚苯并二恶唑(PolyBenzobisOxazole(PBO))或具有类似绝缘特性的其他材料来取代聚酰亚胺。
在某些实施方式中，参照附图50，所述第一导电通孔4106、第二导电通孔4107、第三导电通孔4108、第四导电通孔4109以及第五导电通孔4110的任一个可以是一导电通孔5000。所述导电通孔5000具有开口5001。所述开口5001相对于轴5002为对称的。所述开口5001的外型为片段弧状。
在某些实施方式中，参照附图42，所述导电通孔4106包括底部4201和环状折边4203。所述底部4201为杯形。所述底部4201具有凸缘4202、倾斜壁4216以及底侧4217。所述环状折边4203连接到底部4201的凸缘4202。所述环状折边4203具有第一开口4204。在某些实施方式中，所述环状折边4203的第一厚度和底侧4217的第二厚度基本上相同的。
在某些实施方式中，参照附图44和附图45，所述导电通孔4107、导电通孔4108、导电通孔4109以及导电通孔4110的结构和导电通孔4106类似。所述导电通孔4107具有倾斜壁4218和底侧4219。所述导电通孔4108具有倾斜壁4220和底侧4221。所述导电通孔4109具有倾斜壁4222和底侧4223。所述导电通孔4110具有倾斜壁4224和底侧4225。
在某些实施方式中，参照附图41和附图44，所述杯状导电通孔4106的内部4226填满了绝缘材料。所述绝缘材料可以是聚酰亚胺。
在某些实施方式中，参照附图42，在底侧4217上可能存有一应力。所述应力的来源可能是来自折边4203和倾斜壁4216。可通过本处实作的所述开口4204和4206来释放上述应力。亦可利用这些开口避免应力导致的空洞形成。相似地，参照附图46、附图47、附图48、附图49以及附图50，所述开口4601、4701、4801、4803、4901、4903以及5001可释放来自对应凸缘和倾斜侧壁的应力。所述开口4601、4701、4801、4803、4901、4903以及5001可避免应力导致的空洞形成。

Claims (5)

1.一种半导体封装，其特征在于，包括：
重分布结构，所述重分布结构具有前表面和后表面,所述重分布结构至少包括三层的金属层，中间层金属层具有多个孔洞，所述多个孔洞形成网状结构；
处理器芯片，所述处理器芯片具有有源侧和背侧，所述处理器芯片的有源侧连接到所述重分布结构的前表面，所述处理器芯片的有源侧具有钝化层；
绝缘层，所述绝缘层位于所述钝化层和所述重分布结构之间；
电容，所述电容位于所述重分布结构的后表面，所述电容位于所述处理器芯片的垂直投影之内；以及
金属柱，所述金属柱设置在所述处理器芯片旁，所述金属柱具有第一端、第二端和腰部，所述金属柱以所述第一端连接到所述重分布结构，所述第一端具有第一宽度、所述第二端具有第二宽度、所述腰部具有腰部宽度，所述第一宽度大于所述腰部宽度、所述第二宽度大于所述腰部宽度，所述金属柱具有侧表面，所述侧表面向内弯曲；
其中所述重分布结构和所述处理器芯片之间形成凹部，所述处理器芯片的芯片边缘和所述绝缘层的外缘之间有水平位移。
2.根据权利要求1所述的半导体封装，其特征在于，所述中间层金属层包括金属迹线，所述金属迹线位于所述多个孔洞之间，所述孔洞的宽度大于所述金属迹线的宽度。
3.根据权利要求1所述的半导体封装，其特征在于，所述重分布结构包括多个导电通孔，所述多个导电通孔包括底部和环状折边。
4.一种电子器件，其特征在于，包括：
重分布结构，所述重分布结构具有前表面和后表面，所述重分布结构至少包括三层的金属层，中间层金属层包括多个孔洞，所述多个孔洞形成网状结构；
处理器芯片，所述处理器芯片具有有源侧和背侧，所述处理器芯片的有源侧连接到所述重分布结构的前表面，所述处理器芯片的有源侧具有钝化层；
绝缘层，所述绝缘层位于所述钝化层和所述重分布结构之间；
第一组焊料凸块；
第二组焊料凸块,所述第二组焊料凸块连接于所述重分布结构的后表面；
金属柱，所述金属柱连接到所述第一组焊料凸块，所述金属柱连接到所述重分布结构的前表面，所述金属柱设置在所述处理器芯片旁，所述金属柱具有第一端、第二端和腰部，所述金属柱以所述第一端连接到所述重分布结构，所述第一端具有第一宽度、所述第二端具有第二宽度、所述腰部具有腰部宽度，所述第一宽度大于所述腰部宽度、所述第二宽度大于所述腰部宽度，所述金属柱具有侧表面，所述侧表面向内弯曲；以及
DRAM模块，所述DRAM模块连接到第一组焊料凸块；
其中，所述重分布结构的面积大于所述DRAM模块面积；以及
其中，所述重分布结构和所述处理器芯片之间形成凹部，所述处理器芯片的芯片边缘和所述绝缘层的外缘之间有水平位移。
5.根据权利要求4所述的电子器件，其特征在于，所述重分布结构包括多个导电通孔，所述多个导电通孔包括底部和环状折边。
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