CN112953412A - Ultra-wideband power amplifier circuit with active bias - Google Patents
Ultra-wideband power amplifier circuit with active bias Download PDFInfo
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- CN112953412A CN112953412A CN202110263102.2A CN202110263102A CN112953412A CN 112953412 A CN112953412 A CN 112953412A CN 202110263102 A CN202110263102 A CN 202110263102A CN 112953412 A CN112953412 A CN 112953412A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/42—Modifications of amplifiers to extend the bandwidth
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
Abstract
The invention discloses an active bias ultra-wideband power amplifier circuit, which comprises a bias circuit, an amplifying circuit and an inductor L1, wherein the first end of the bias circuit is connected with the first end of the amplifying circuit and is connected with a signal input end through a capacitor C1; the second end of the bias circuit is connected with the second end of the amplifying circuit and is connected with the signal output end through a capacitor C3; the third terminal of the bias circuit and the third terminal of the amplifying circuit are grounded respectively, the first terminal of the inductor L1 is connected with the second terminal of the bias circuit, the second terminal of the amplifying circuit and the first terminal of the capacitor C3, and the second terminal of the inductor L1 is connected with a power supply. The invention can solve the problems of low output power and low linearity of the ultra-wideband power amplifier.
Description
Technical Field
The invention relates to the technical field of radio frequency integrated circuits, in particular to an ultra-wideband power amplifier circuit with active bias.
Background
The ultra-wideband power amplifier is a very important constituent unit in a radio frequency front-end module, and mainly has the functions of amplifying signals and providing certain power gain. The power amplifier is divided into an ultra-wideband power amplifier, a wideband power amplifier and a narrowband power amplifier according to different bandwidths, and the input impedance and the output impedance of the ultra-wideband power amplifier are generally matched with the system impedance of 50 ohms, so that the ultra-wideband power amplifier is widely applied.
The distributed structure can realize extremely wide bandwidth, but the area is large, the efficiency and the gain are low, the cascode Darlington structure becomes a common structure in the design of an ultra-wideband power amplifier due to the excellent broadband characteristic of the cascode Darlington structure, the cascode Darlington structure can realize extremely wide bandwidth, but the traditional cascode Darlington structure has the problems of poor temperature coefficient and poor linearity for a resistance voltage division circuit structure.
Disclosure of Invention
The invention provides an active bias ultra-wideband power amplifier circuit which can solve the problems of low output power and low linearity of an ultra-wideband power amplifier.
In order to solve the technical problem, the technical scheme of the invention is realized as follows.
The embodiment of the invention provides an ultra-wideband power amplifier circuit with active bias, which comprises a bias circuit, an amplifying circuit and an inductor L1, wherein the first end of the bias circuit is connected with the first end of the amplifying circuit and is connected with a signal input end through a capacitor C1; the second end of the bias circuit is connected with the second end of the amplifying circuit and is connected with the signal output end through a capacitor C3; the third terminal of the bias circuit and the third terminal of the amplifying circuit are respectively grounded, the first terminal of the inductor L1 is connected with the second terminal of the bias circuit, the second terminal of the amplifying circuit and the first terminal of the capacitor C3, and the second terminal of the inductor L1 is connected with a power supply; the active bias circuit comprises resistors R1, R2, R3, R4 and R5, and transistors M4 and M5; the first end of the resistor R1 is connected with the second end of the bias circuit, the second end of the resistor R1 is connected with the first end of the resistor R2 and the first end of the transistor M5, the second end of the resistor R2 is connected with the first end of the transistor M4 and the second end of the transistor M5, the second end of the transistor M4 is connected with the third end of the transistor M5, the first end of the resistor R4 and the first end of the resistor R5, the third end of the transistor M4 is connected with the first end of the resistor R3, the second end of the resistor R3 is connected with the second end of the resistor R4 and the third end of the bias circuit, and the second end of the resistor R5 is connected with the first end of the active bias circuit.
In the embodiment provided by the invention, the amplifying circuit comprises transistors M1, M2 and M3, resistors R6, R7, R8 and R9, a capacitor C2; a second terminal of the transistor M1 is connected to the first terminal of the amplifying circuit, a third terminal of the transistor M1 is connected to the first terminal of the resistor R6 and the second terminal of the transistor M2, respectively, a third terminal of the transistor M2 is connected to the first terminal of the resistor R9, a second terminal of the resistor R6 and the second terminal of the resistor R9 are connected to each other and to the third terminal of the amplifying circuit, and a first terminal of the transistor M1 and the first terminal of the transistor M2 are connected to each other and to the third terminal of the transistor M3; a first terminal of the transistor M3 is interconnected with a first terminal of a resistor R7 and with a second terminal of the amplifying circuit; the second terminal of the transistor M3 is connected to the second terminal of the resistor R7, the first terminal of the resistor R8, and the first terminal of the capacitor C2, and the second terminal of the resistor R8 and the second terminal of the capacitor C2 are connected to ground. The transistors M1, M2, M3, M4 and M5 are all FET tubes.
Compared with the prior art, the active bias circuit replaces a resistance voltage division bias circuit structure, so that the active bias circuit still has stable static working points at different temperatures, the stability of the circuit is enhanced, and the linearity is improved. The operating voltage can be increased by a cascode darlington configuration, so that the output power can be increased.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an ultra-wideband power amplifier provided in an embodiment of the present application;
fig. 2 is a schematic circuit diagram of an ultra-wideband power amplifier according to an embodiment of the present disclosure;
fig. 3 is a diagram of a simulation result of a 1dB compression point of a circuit output of an ultra-wideband power amplifier provided in an embodiment of the present application;
fig. 4 is a diagram of a simulation result of a third-order intermodulation point output by a circuit of an ultra-wideband power amplifier according to an embodiment of the present application.
Detailed Description
The present invention is further described in detail below with reference to the attached drawings so that those skilled in the art can implement the invention by referring to the description text.
It will be understood that terms such as "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof.
The terms "first" and "second", and the like, in the description and in the claims of embodiments of the present invention are used to distinguish the connection ends of circuit elements, and are not used to describe a particular order of circuit elements. For example, the first and second terminals, etc. are different connection terminals for distinguishing the same circuit element, rather than for describing a particular order of a plurality of circuit elements.
Currently, in the related art, a distributed structure can achieve an extremely wide bandwidth, but has a large area and low efficiency and gain, while a cascode darlington structure can provide excellent performance in many aspects, such as high gain and wide bandwidth, but the conventional cascode darlington structure has a problem of low linearity. The traditional bias circuit of the ultra-wideband power amplifier is a resistance voltage division structure, when the environmental temperature changes, the parameters of the transistor also change along with the change of the temperature, but the voltage division value generated in the resistance voltage division structure does not change along with the change of the temperature, so that the static working point is possibly deviated, and the output power and the linearity of the ultra-wideband power amplifier are low.
An ultra-wideband power amplifier circuit with active bias provided by the embodiments of the present application is described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the present invention provides an ultra-wideband power amplifier circuit with active bias, which includes a bias circuit, an amplifying circuit, and an inductor L1, wherein a first end of the bias circuit is connected to a first end of the amplifying circuit, and is connected to a signal input end through a capacitor C1; the second end of the bias circuit is connected with the second end of the amplifying circuit and is connected with the signal output end through a capacitor C3; the third terminal of the bias circuit and the third terminal of the amplifying circuit are grounded respectively, the first terminal of the inductor L1 is connected with the second terminal of the bias circuit, the second terminal of the amplifying circuit and the first terminal of the capacitor C3, and the second terminal of the inductor L1 is connected with a power supply.
It will be appreciated that in embodiments provided by the present invention, a radio frequency signal enters the first capacitor C from the signal input terminal RFin1The input is amplified by an amplifying circuit 11 configured by an active bias circuit 10 and then is transmitted by a third capacitor C3And (6) outputting.
As shown in fig. 2, the active bias circuit includes resistors R1, R2, R3, R4, and R5, and transistors M4 and M5; the first end of the resistor R1 is connected with the second end of the bias circuit, the second end of the resistor R1 is connected with the first end of the resistor R2 and the first end of the transistor M5, the second end of the resistor R2 is connected with the first end of the transistor M4 and the second end of the transistor M5, the second end of the transistor M4 is connected with the third end of the transistor M5, the first end of the resistor R4 and the first end of the resistor R5, the third end of the transistor M4 is connected with the first end of the resistor R3, the second end of the resistor R3 is connected with the second end of the resistor R4 and the third end of the bias circuit, and the second end of the resistor R5 is connected with the first end of the active bias circuit.
The amplifying circuit comprises transistors M1, M2 and M3, resistors R6, R7, R8 and R9 and a capacitor C2; a second terminal of the transistor M1 is connected to the first terminal of the amplifying circuit, a third terminal of the transistor M1 is connected to the first terminal of the resistor R6 and the second terminal of the transistor M2, respectively, a third terminal of the transistor M2 is connected to the first terminal of the resistor R9, a second terminal of the resistor R6 and the second terminal of the resistor R9 are connected to each other and to the third terminal of the amplifying circuit, and a first terminal of the transistor M1 and the first terminal of the transistor M2 are connected to each other and to the third terminal of the transistor M3; a first terminal of the transistor M3 is interconnected with a first terminal of a resistor R7 and with a second terminal of the amplifying circuit; the second terminal of the transistor M3 is connected to the second terminal of the resistor R7, the first terminal of the resistor R8, and the first terminal of the capacitor C2, and the second terminal of the resistor R8 and the second terminal of the capacitor C2 are connected to ground.
It is understood that, in the embodiment provided by the present invention, the transistors M1, M2, M3, M4 and M5 are all FET transistors.
As shown in fig. 1 and 2, in the embodiment of the present invention, when the ambient temperature changes, the first transistor M1Produces a slight increment of Δ v such that the first transistor M1While also causing the fourth transistor M to increase in drain current4A small increment Δ i is obtained by the drain current flowing through the second resistor R2Resulting in the fifth transistor M5Produces an increment of Δ v1 due to the fifth transistor M5The gate-source voltage remains substantially constant, so that in the fifth transistor M5Also producing an increment of Δ v 1. Since the sign of Δ v1 is opposite to the sign of Δ v, the first transistor M1The threshold voltage variation of the first transistor M is compensated to a certain extent, so that the first transistor M1The leakage current of (a) remains substantially unchanged. Thereby stabilizing the static operating point and improving the linearity of the circuit.
As shown in fig. 3 and 4, it can be seen that,
the ultra-wideband power amplifier circuit has the advantages of high linearity, high output power, large dynamic range and the like, solves the contradiction between the performance of the ultra-wideband power amplifier circuit such as bandwidth, linearity, output power and the like, and greatly improves the practicability of the ultra-wideband power amplifier circuit.
As shown in fig. 3, it can be seen that OP1dB is always maintained between 26 and 31 with increasing rf frequency at different temperatures.
As shown in fig. 4, it can be seen that the value of OIP3 gradually decreases and stabilizes toward the same value as the rf frequency increases at different temperatures.
Compared with the ultra-wideband power amplifier with the traditional resistance voltage division biasing circuit structure, the ultra-wideband power amplifier provided by the embodiment of the invention has a good temperature coefficient, does not need an external system to additionally provide temperature compensation, and improves the linearity of the circuit. The ultra-wideband power amplifier circuit has the advantages of high linearity, high output power, large dynamic range and the like, solves the contradiction between the performance of the ultra-wideband power amplifier circuit such as bandwidth, linearity, output power and the like, and greatly improves the practicability of the ultra-wideband power amplifier circuit.
While embodiments of the invention have been disclosed above, it is not limited to the applications listed in the description and the embodiments. It can be applied to all kinds of fields suitable for the present invention. Additional modifications will readily occur to those skilled in the art. It is therefore intended that the invention not be limited to the exact details and illustrations described and illustrated herein, but fall within the scope of the appended claims and equivalents thereof.
Claims (3)
1. The ultra-wideband power amplifier circuit with the active bias comprises a bias circuit, an amplifying circuit and an inductor L1, wherein the first end of the bias circuit is connected with the first end of the amplifying circuit and is connected with a signal input end through a capacitor C1; the second end of the bias circuit is connected with the second end of the amplifying circuit and is connected with the signal output end through a capacitor C3; the third terminal of the bias circuit and the third terminal of the amplifying circuit are respectively grounded, the first terminal of the inductor L1 is connected with the second terminal of the bias circuit, the second terminal of the amplifying circuit and the first terminal of the capacitor C3, and the second terminal of the inductor L1 is connected with a power supply; the active bias circuit is characterized by comprising resistors R1, R2, R3, R4 and R5, and transistors M4 and M5; the first end of the resistor R1 is connected with the second end of the bias circuit, the second end of the resistor R1 is connected with the first end of the resistor R2 and the first end of the transistor M5, the second end of the resistor R2 is connected with the first end of the transistor M4 and the second end of the transistor M5, the second end of the transistor M4 is connected with the third end of the transistor M5, the first end of the resistor R4 and the first end of the resistor R5, the third end of the transistor M4 is connected with the first end of the resistor R3, the second end of the resistor R3 is connected with the second end of the resistor R4 and the third end of the bias circuit, and the second end of the resistor R5 is connected with the first end of the active bias circuit.
2. The actively-biased ultra-wideband power amplifier circuit as claimed in claim 1, wherein said amplifying circuit comprises transistors M1, M2, and M3, resistors R6, R7, R8, and R9, a capacitor C2; a second terminal of the transistor M1 is connected to the first terminal of the amplifying circuit, a third terminal of the transistor M1 is connected to the first terminal of the resistor R6 and the second terminal of the transistor M2, respectively, a third terminal of the transistor M2 is connected to the first terminal of the resistor R9, a second terminal of the resistor R6 and the second terminal of the resistor R9 are connected to each other and to the third terminal of the amplifying circuit, and a first terminal of the transistor M1 and the first terminal of the transistor M2 are connected to each other and to the third terminal of the transistor M3; a first terminal of the transistor M3 is interconnected with a first terminal of a resistor R7 and with a second terminal of the amplifying circuit; the second terminal of the transistor M3 is connected to the second terminal of the resistor R7, the first terminal of the resistor R8, and the first terminal of the capacitor C2, and the second terminal of the resistor R8 and the second terminal of the capacitor C2 are connected to ground.
3. The actively biased ultra-wideband power amplifier circuit as claimed in claims 1 and 2, wherein the transistors M1, M2, M3, M4 and M5 are FET transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202110263102.2A CN112953412A (en) | 2021-03-10 | 2021-03-10 | Ultra-wideband power amplifier circuit with active bias |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110263102.2A CN112953412A (en) | 2021-03-10 | 2021-03-10 | Ultra-wideband power amplifier circuit with active bias |
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| CN112953412A true CN112953412A (en) | 2021-06-11 |
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Citations (7)
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| US20060077001A1 (en) * | 2004-10-11 | 2006-04-13 | Wavics Inc. | Temperature-Compensated Bias Circuit for Power Amplifier |
| TW200637139A (en) * | 2005-04-06 | 2006-10-16 | Richwave Technology Corp | Adaptive linear biasing circuit |
| US20070040613A1 (en) * | 2005-08-19 | 2007-02-22 | Chow Yut H | Isolated stable bias circuit |
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| US20110291764A1 (en) * | 2010-05-28 | 2011-12-01 | Rf Micro Devices, Inc. | Linear fet feedback amplifier |
| US20150002224A1 (en) * | 2013-06-28 | 2015-01-01 | Samsung Electro-Mechanics Co., Ltd. | Bias circuit and power amplifier with selection function of power mode |
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2021
- 2021-03-10 CN CN202110263102.2A patent/CN112953412A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060077001A1 (en) * | 2004-10-11 | 2006-04-13 | Wavics Inc. | Temperature-Compensated Bias Circuit for Power Amplifier |
| TW200637139A (en) * | 2005-04-06 | 2006-10-16 | Richwave Technology Corp | Adaptive linear biasing circuit |
| US20070040613A1 (en) * | 2005-08-19 | 2007-02-22 | Chow Yut H | Isolated stable bias circuit |
| US20110291764A1 (en) * | 2010-05-28 | 2011-12-01 | Rf Micro Devices, Inc. | Linear fet feedback amplifier |
| JP2011101405A (en) * | 2010-12-27 | 2011-05-19 | Panasonic Corp | High-frequency power amplifier |
| US20150002224A1 (en) * | 2013-06-28 | 2015-01-01 | Samsung Electro-Mechanics Co., Ltd. | Bias circuit and power amplifier with selection function of power mode |
| CN106230391A (en) * | 2016-07-13 | 2016-12-14 | 锐迪科微电子（上海）有限公司 | A kind of linearisation current biasing circuit of power amplifier |
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| KEVIN W. KOBAYASHI等: "Linearized Darlington Cascode Amplifier Employing GaAs PHEMT and GaN HEMT Technologies", 《IEEE JOURNAL OF SOLID-STATE CIRCUITS》 * |
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Application publication date: 20210611 |