JP3371350B2 - Negative feedback variable gain amplifier circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AG of a wireless receiver.
The present invention relates to a negative feedback variable gain amplifier circuit suitable for a C (Automatic Gain Control) circuit and the like.

[0002]

2. Description of the Related Art In recent years, with the widespread use of wireless telephones and the like, there has been a strong demand for a variable gain amplifier circuit having a wide dynamic range and a high linearity, which converts a received signal having a large amplitude variation into a signal having a substantially constant level. There is.

FIG. 1 shows a conventional general negative feedback amplifier circuit. This negative feedback amplifier circuit includes an amplifier 1 and a feedback circuit 3, and the feedback circuit 3 is composed of a capacitor 3a and a resistor 3b. An input matching circuit 7 is connected between the amplifier 1 and the input terminal 5, and an output matching circuit 9 is connected between the amplifier 1 and the output terminal 11.

Since the feedback circuit 3 transmits the signal bidirectionally, there is a problem that the input signal is transmitted from the input side to the output side of the amplifier 1. In particular, the gain of the amplifier 1 is 1
If it is smaller than this, there is a problem that the influence of the signal transmitted to the output side through the feedback circuit 3 becomes large.

2 and 3 show a conventional variable gain amplifier circuit. The amplifier circuit of FIG. 2 uses a dual gate FET 21 as an amplifier, and uses one of the dual gate terminals as a control terminal 23 to realize a variable gain amplifier circuit. The input matching circuit 7 has an FE
The gate bias voltage Vg is applied to the gate terminal of T via the bias terminal 27, and the output matching circuit 9 has the drain terminal of the FET constituting the output matching circuit 9 and the bias terminal 2
The drain bias voltage Vdd is applied via 9.

The amplifier circuit of FIG. 3 has FETs 31 and 33.
A cascode amplifier is constituted by, and the variable gain amplifier circuit is realized by using the gate terminal of the FET 33 as the control terminal 35. The variable gain amplifier circuits of FIGS. 2 and 3 are equivalent, and both of them control the gain by changing the mutual conductance of the FET.

In FIG. 3, when the level of the input signal to the amplifier circuit is low and the gain of the amplifier must be increased, the voltage applied to the control terminal 35 is set to a positive value and F
The voltage distribution to the drain of ET31 is increased and its mutual conductance gm is increased. Conversely, when the level of the input signal to the amplifier circuit is high and the gain of the amplifier must be reduced, the voltage applied to the control terminal 35 is set to a negative value and the voltage distribution to the drain of the FET 31 is reduced. , The reverse bias between the gate and the source of the FET 33 is deepened to reduce the mutual conductance gm of the FETs 31 and 33.

By the way, the linearity of the FET deteriorates significantly as the transconductance decreases. Therefore, in these amplifier circuits in which the gain is changed by changing the transconductance of the FET, the amplification factor of the FET 31 sharply decreases and the linearity of the FET 33 significantly deteriorates when the gain decreases. As a result, there is a problem that the maximum allowable input level is lowered as the gain is lowered in response to an input signal having a large amplitude. That is, there is a disadvantage that the range of low distortion operation is narrow.

FIG. 4 shows an amplifier circuit developed to solve the drawbacks of these variable gain amplifier circuits. this is,
1991 IEEE MTT-S International Microwave Sym
It was announced at posium. This amplifier circuit uses a source-grounded FET 41 as an amplifier and a series circuit of a capacitor 43a and an FET 43b as a feedback circuit. Further, the gate terminal of the FET 43b is grounded via the bypass capacitor 45, and
This gate terminal is connected to the control terminal 47. Then, by controlling the voltage applied to the control terminal 47, the FET 4
The gain of the amplifier circuit is controlled by changing the resistance value between the drain and the source of 3b.

According to this variable gain amplifier circuit, since the drain bias voltage of the FET 41 which operates as an amplifier is constant, the range of low distortion operation is increased as compared with the variable gain amplifier circuit of FIG. In addition, when the drain-source resistance of the FET 43b is lowered and the gain of the amplifier is lowered in response to the increase in the amplitude of the input signal, the input impedance of the amplifier is lowered. Therefore, the voltage level applied to the gate of the FET 41 can be suppressed to a low level, and the maximum allowable input level can be further increased.

In order to operate this variable gain amplifier circuit with low distortion up to a higher input signal level, it is important to change the input impedance of the amplifier within a wide range.

FIG. 5 is a diagram showing the relationship between the gate control voltage and the drain-source resistance Rds of the feedback FET 43b shown in FIG. The gate width of the FET 43b is 100μ
The minimum resistance value of the FET 43b at that time is several tens of ohms. Therefore, the minimum gain of the amplifier circuit in FIG. 4 is limited to about −10 dB. In order to further reduce the minimum gain of the amplifier circuit, it is necessary to further reduce the drain-source resistance of the feedback FET 43b. For this purpose, the gate width of the FET 43b must be increased. However, the increase in parasitic capacitance due to this is
There is a problem that the performance (gain / bandwidth product) of the amplifier is lowered.

FIG. 6 shows a conventional negative feedback amplifier circuit. This is disclosed in SU543133. The amplifier circuit includes a two-stage amplifier including transistors 51 and 53, and a feedback transistor 52. The base of the feedback transistor 52 is a resistor 54.
Is connected to the collector of the output transistor 53 via the
3 is connected to the base. Further, the emitter of the feedback transistor 52 is connected to the base of the output transistor 53 via the resistor 56. Output transistor 53
The unstable voltage at the collector of the current generator generates a current through the resistor 54 at the base of the feedback transistor 52. This current is amplified by the feedback transistor 52 and the resistance 5
Is supplied to the base of the output transistor 53 via 6,
Compensate for collector instability. As a result, the output loss of the output transistor 53 can be reduced and the maximum output signal can be increased.

However, in the negative feedback amplifier circuit of FIG. 6, the output transistor 53 and the feedback transistor 52 are integrated, and these transistors cannot be controlled independently. Therefore, the gain of the amplifier circuit cannot be changed externally.

FIG. 7 illustrates US Patent Application No. 5,264,80.
It is a conventional negative feedback amplifier circuit by Kobayashi disclosed in No. 6. This amplifier circuit includes a Darlington amplifier 62 and an active feedback circuit 64. This active feedback circuit 64 is
It has a transistor QF and resistors Rte and Rbt, the base of the transistor QF is connected to the output end of the Darlington amplifier 62 via the resistor Rbt, and the emitter is connected to the input end of the Darlington amplifier 62 via the resistor RF. It is connected. In this amplifier circuit, the inductance value of the active feedback circuit 64 is
It can be changed by changing the resistance values of the resistors Rbt and Rte. Thereby, the bandwidth of this amplifier circuit can be made variable. However, the transistor QF of the active feedback circuit 64 cannot operate independently of the amplifier 62. Therefore, the gain of the amplifier circuit cannot be controlled from the outside.

FIG. 8 shows Electronics Letters 14th, Sept.
It is the conventional negative feedback variable gain amplifier circuit announced in ember, 1989, Vol 25, No. 19, pp.1317-1318. This amplifier circuit is a differential amplifier. In the figure, the main amplification section is composed of transistors Q1 and Q2, and transistor Q3
Constitutes a negative feedback circuit. That is, the base of the feedback transistor Q3 is connected to the output terminal of the output transistor Q2, and the emitter of the feedback transistor Q3 is connected to the input terminal of the output transistor Q2 via the resistor RL1. By using the transistor Q3 in the feedback circuit in this way, the bandwidth of the variable gain amplifier circuit can be widened. Further, this variable gain amplifier circuit changes the gain by changing the mutual conductance of the transistor Q1.

However, in this negative feedback variable gain amplifier circuit, the feedback transistor Q3 cannot operate independently of the main amplifier section, and it is impossible to control the amount of feedback to control the gain. . Furthermore, this variable gain amplifier circuit has the above-mentioned drawbacks because the gain is controlled by changing the mutual conductance of the transistor Q1 of the main amplifier section. That is, when the gain of the variable gain amplifier circuit is low, the amplification factor of the transistor Q1 sharply decreases and the linearity of the transistor Q1 significantly deteriorates. Therefore, the lower the gain is, the lower the maximum allowable input level is, and the maximum allowable input level for realizing the low distortion operation is relatively low.

To summarize the above, (1) In the conventional variable gain amplifier circuits shown in FIGS. 2 and 3, the maximum allowable input level was suppressed because the linearity of the amplifier was poor.

(2) In the conventional variable gain amplifier circuit shown in FIG. 4, the maximum allowable input level is limited by the physical dimensions of the FETs that make up the variable gain amplifier.

(3) In the negative feedback amplifier circuit shown in FIGS. 6 and 7, the transistor forming the feedback section cannot operate independently of the main amplifier section, so that the gain of the amplifier circuit is controlled. I couldn't.

(4) In the negative feedback variable gain amplifier circuit shown in FIG. 8, since the transistor forming the feedback section cannot operate independently of the main amplifier section, the gain of the amplifier circuit can be controlled. There wasn't. Moreover, the maximum allowable input level is suppressed because the linearity of the amplifier is poor.

[0022]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a negative feedback variable gain amplifier circuit which is excellent in linearity and has a large allowable maximum input level.

Another object of the present invention is that the input signal is
It is to provide a negative feedback variable gain amplifier circuit which does not transmit from an input side to an output side through a feedback circuit.

[0024]

According to the present invention, an amplifier for amplifying an input signal, a first terminal to which a first voltage is applied, a second terminal to which a second voltage is applied, and a control are provided. A feedback transistor having a terminal connected to the first terminal, a first main current terminal connected to an input terminal of the amplifier, and a second main current terminal connected to the second terminal; and an output of the amplifier. And a capacitor connected between the terminal and the control terminal of the feedback transistor, the gain being changed in response to at least one of the first voltage and the second voltage. .

Further, the negative feedback variable gain amplifier circuit further measures a power of an input signal to the negative feedback variable gain amplifier circuit and outputs a detection signal indicating the power, and a detection means. Based on the above, a control circuit that outputs the first voltage and a constant voltage source that outputs the second voltage may be provided.

Further, the negative feedback variable gain amplifier circuit further measures a constant voltage source for outputting the first voltage and the power of an input signal to the negative feedback variable gain amplifier circuit, and indicates the power. You may comprise the measuring means which outputs a detection signal, and the control circuit which outputs the said 2nd voltage based on the said detection signal.

Further, the negative feedback variable gain amplifier circuit further measures a power of an input signal to the negative feedback variable gain amplifier circuit and outputs a detection signal indicating the power, and a detection means. Based on the above, a control circuit for outputting the first voltage and the second voltage may be provided.

Further, at least one of the first terminal and the second terminal may be grounded via a capacitor.

Further, the amplifier may be a cascode amplifier.

Further, the amplifier may be a multistage amplifier.

The feedback transistor is a field effect transistor, the control terminal is its gate terminal,
The first main current terminal may be its source terminal and the second main current terminal may be its drain terminal.

The feedback transistor is a bipolar transistor, the control terminal is the base terminal thereof, the first main current terminal is the emitter terminal thereof, and the second main current terminal thereof is the second terminal.
The main current terminal may be its collector terminal.

The feedback transistor is a heterojunction bipolar transistor, the control terminal is its base terminal, the first main current terminal is its emitter terminal,
The second main current terminal may be its collector terminal.

[0034]

The negative feedback variable gain amplifier circuit according to the present invention is
Since the feedback amount is controlled by changing the mutual conductance of the feedback transistor, it is possible to realize a variable gain amplifier circuit that does not depend on the physical size of the amplifier transistor. That is, with respect to an input signal having a large amplitude, the transconductance of the feedback transistor is increased to increase the feedback amount and reduce the gain of the amplifier circuit. Conversely, for an input signal with a small amplitude, the mutual conductance of the feedback transistor is reduced to reduce the feedback amount and increase the gain of the amplifier circuit. In this way, a signal whose amplitude level is controlled is output.

In this case, the input impedance of the feedback transistor, that is, the control terminal (F
The impedance looking at the gate of the ET, or the base of the bipolar transistor) is kept approximately constant and high. On the other hand, the output impedance of the feedback transistor,
That is, the impedance of the main current terminal of the feedback transistor (the source of the FET or the emitter of the bipolar transistor) changes in inverse proportion to the mutual conductance of the feedback transistor. In other words, the impedance of the feedback transistor seen from the output terminal of the amplification transistor is maintained at a constant and high value, and the impedance of the feedback transistor seen from the input terminal of the amplification transistor changes in inverse proportion to the mutual conductance of the feedback transistor. To do.

[0037]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 9 is a block diagram showing a negative feedback variable gain amplifier circuit 70 according to the present invention. In the figure, 71 is a source-grounded FET that constitutes an amplifier. The feedback FET 73 is connected to the amplification FET 71. That is, the source of the feedback FET 73 is connected to the gate of the amplification FET 71, and the gate of the feedback FET 73 is connected to the drain of the amplification FET 71 via the capacitor 75. Return FE
The gate of T73 is further connected to the control terminal 79 via the resistor 77, and the drain is connected to the control terminal 81. The control terminals 79 and 81 are grounded via bypass capacitors 83 and 85, respectively. Further, the gate of the amplification FET 71 is connected to the input terminal 91 via the input matching circuit 87, and the drain is connected to the output terminal 95 via the output matching circuit 93.

In such a configuration, when the voltage V1 of the control terminal 79 is changed from the pinch-off voltage to 0V while keeping the voltage V2 of the control terminal 81 constant (3V), the feedback FET 73 having a gate width of 100 μm The input / output impedance and transconductance are shown in FIG.
It changes like (A).

That is, when the gate bias voltage V1 of the feedback FET 73 changes from the pinch-off voltage to 0V, the transconductance of the feedback FET 73 gradually increases and takes a substantially constant value from around -0.6V to 0V. . Further, the input impedance of the feedback FET 73, that is, the gate-side impedance is kept substantially constant at a relatively high value of around 450Ω. On the other hand, feedback FET7
The output impedance of 3, that is, the impedance on the source side decreases in inverse proportion to the mutual conductance of the feedback FET 73.

On the other hand, the voltage V1 at the control terminal 79 is kept constant (-
0.8 V) while keeping the voltage V2 of the control terminal 81 at 0
When changing from V to 3 V, the gate width is 100 μm
The input / output impedance and the transconductance of the feedback FET 73 are changed as shown in FIG. That is, the control voltage V2 is kept constant and the control voltage V1 is changed, and the change is almost the same.

As described above, when the gate voltage or drain voltage of the feedback FET 73 is changed, its mutual conductance also changes. Therefore, the gain of the variable gain amplifier circuit can be controlled by the gate voltage or the drain voltage. For example, if the drain bias voltage is kept constant and the gate bias voltage is deepened, the mutual conductance decreases and the amount of negative feedback decreases, so that the gain of the variable gain amplifier circuit increases. Conversely, when the gate bias voltage is increased, the transconductance increases and the amount of negative feedback increases, so the gain of the variable gain amplifier circuit decreases. The same function can be realized by keeping the gate bias voltage constant and changing the drain bias voltage. In this case, the capacitor 75 prevents the gate bias voltage from being applied to the drain of the amplification FET 71. As a result, the feedback FET 73 is replaced with the amplification FET 71.
It becomes possible to control independently.

Here, the gain of the feedback FET 73 (feedback amount)
S21 is represented by the following equation.

[0044]

[Equation 1]

Here, Z ₀ is the source side load impedance and gate side signal source impedance of the feedback FET 73, and g _mf is the mutual conductance of the feedback FET 73. As seen from this equation, if the Z ₀ substantially constant, when g _mf is sufficiently smaller than 1 / Z ₀ is the feedback amount is increased in proportion to nearly g _mf, from g _mf is 1 / Z ₀ When it is sufficiently large, it is almost constant (= 2).

Further, the gain G _ain of this variable gain amplifier circuit
Is expressed by the following equation.

[0047]

[Equation 2]

However, g _m0 is the mutual conductance of the amplification FET 71. As can be seen from these equations, the smaller the mutual conductance g _mf of the feedback FET 73, the smaller the amount of negative feedback, and the gain of the variable gain amplifier circuit 70 increases. When g _mf = 0, the maximum gain is obtained. Conversely, g _mf
Is maximum, the negative feedback amount is also maximum, and the gain of the variable gain amplifier circuit 70 is minimum. Also, S of the feedback FET 73
12 is always zero, and there is no signal transmission from the input side to the output side through the feedback circuit. Therefore, the negative feedback variable gain amplifier circuit according to the present invention always performs an ideal negative feedback operation.

FIG. 11 shows an output level characteristic and a D / U ratio obtained when the gate bias voltage V1 of the feedback FET 73 is changed in the variable gain amplifier circuit shown in FIG. The D / U ratio is the ratio of the output power of the desired wave D and the unwanted wave U (third-order intermodulation distortion wave). The measurement conditions are 4 GHz and 4 GHz + 10 MHz, and two waves having an input level of -4 dBm / wave are simultaneously supplied to the input terminal 91, and at this time, the third-order intermodulation distortion wave (unwanted wave U is obtained at the output terminal 95). ), And the power of the output wave (desired wave D) of 4 GHz was measured. Also, set the gate width of the feedback FET 73 to 1
The transconductance was 00 μm, the mutual conductance was 17 mS, and the drain control voltage V2 was 3 V.

Gate bias voltage V1 of the feedback FET 73
Is changed from the pinch-off voltage to 0 V, the output of the variable gain amplifier circuit 70 changes from around -2.5 dB to -1.
It gradually decreases to around 6.5 dB. Considering that the input level of the desired wave D is -4 dBm, the gain of the variable gain amplifier circuit 70 is about -1 dB from about 1.5 dB.
It changes to about 2.5 dB, and the amount of decrease is almost -14.
It turns out that it is dB. On the other hand, the D / U ratio is 22 dB
From 61 dB to 61 dB. From these measurement results,
In the variable gain amplifier circuit according to the present invention, the gain is changed by the change of the mutual conductance of the feedback FET 73,
It can be confirmed that when the mutual conductance is large and the gain of the variable gain amplifier circuit is small, the operation is low distortion. That is, it can be seen that this variable gain amplifier circuit performs low distortion operation on an input signal having a large amplitude. By using a high-performance FET having a larger transconductance as a feedback FET, a larger gain change and a higher D / U ratio can be obtained.

FIG. 12 shows the relationship between the input power and the D / U ratio when the output of the variable gain amplifier circuit is constant (-10 dBm). The black circles show the measured values with the variable gain amplifier circuit according to this embodiment, and the white circles show the measured values with the conventional variable gain amplifier circuit shown in FIG. The measurement conditions are the same as in the case of FIG. As can be seen from this figure, the variable gain amplifier circuit according to the present embodiment has an improved D / U ratio as compared with the conventional variable gain amplifier circuit. In particular, when the input power exceeds -5 dBm, the effect is remarkable, and the difference between them is widened to about 20 dB at the maximum.

FIG. 13 shows the input power to D / U ratio of the variable gain amplifier circuit at the minimum gain. Black circles show the characteristics of the variable gain amplifier circuit 70 according to the present embodiment, and white circles show the characteristics.
5 shows characteristics of the conventional variable gain amplifier circuit of FIG. The measurement conditions are the same as in the case of FIG. From this figure, it is understood that the variable gain amplifier circuit according to the present invention can reduce the distortion as compared with the conventional variable gain amplifier circuit. For example, when the D / U ratio = 50 dB, the maximum allowable input level can be increased by 8 dB or more.

In the conventional variable gain amplifier circuit, the maximum allowable input level (D / U ratio = 5) at which the amplifier circuit performs a linear operation.
(Corresponding to the point of 0 dB) was about -10 dBm, but the variable gain amplifier circuit according to the present invention can increase the maximum allowable input level to about 0 dBm. A variable gain amplifier circuit having such high linearity was realized for the first time by the present invention.

Embodiment 2 FIG. 14 shows a second embodiment of the negative feedback variable gain amplifier circuit according to the present invention.
It is a block diagram which shows an Example. The second embodiment differs from the first embodiment in that an active load FET 97 is inserted between the drain of the amplification FET 71 and the capacitor 75 and the amplification section is a cascode amplifier. The gate of the load FET 97 is connected to the control terminal 99.

This variable gain amplifier circuit can perform the same operation as the variable gain amplifier circuit of the first embodiment. Furthermore, the transconductance of the FETs 71 and 97 can be controlled by changing the voltage applied to the control terminal 99. That is, in FIG. 14, when the level of the input signal to the amplifier circuit is low and the gain of the amplifier must be increased, the voltage applied to the control terminal 99 is set to a positive value and the voltage is distributed to the drain of the amplifier FET 71. To increase its transconductance g _m . On the contrary, when the level of the input signal to the amplifier circuit is high and the gain of the amplifier must be reduced, the voltage applied to the control terminal 99 is set to a negative value to reduce the voltage distribution to the drain of the amplification FET 71. With load FE
The reverse bias between the gate and source of T97 is deepened to reduce the transconductance g _m of both FETs 71 and 97. This operation itself regarding the FET 97 is shown in FIG.
This is the same as the conventional example shown in FIG.
By combining with T73, it is possible to perform control with higher accuracy than the negative feedback variable gain amplifier circuit of the first embodiment.

In the above-mentioned Examples 1 and 2,
FET was used for the amplifier and the feedback circuit.
Alternatively, a bipolar transistor or a heterojunction transistor can be used. In this case, the base of these transistors may be replaced with the gate of the FET, the emitter may be replaced with the source, and the collector may be replaced with the drain.

Further, the amplifier may be a multistage amplifier.

Embodiment 3 FIG. 15 shows a third embodiment of the negative feedback variable gain amplifier circuit according to the present invention.
It is a block diagram which shows an Example. In this embodiment, the variable gain amplifier circuit 70 according to the first or second embodiment is replaced with the AGC.
This is an example applied to an (automatic gain control) circuit.

The input signal is the input terminal 101 of the AGC circuit.
Through the power detector 103. The power detector 103 measures the power of the input signal and supplies the result to the control circuit 105. The control circuit 105 supplies the control voltage V1 according to the power of the input signal to the control terminal 79 of the variable gain amplifier circuit 70. On the other hand, a constant control voltage V2 is supplied from the constant voltage source 107 to the control terminal 81.

As described above, by combining the negative feedback variable gain amplifying circuits shown in the first and second embodiments with the control system, the characteristic of these variable gain amplifying circuits is
A GC circuit can be constructed.

Fourth Embodiment FIG. 16 is a block diagram showing a fourth embodiment of the variable gain amplifier circuit according to the present invention. In this embodiment, the control terminal 7
The voltages supplied to 9 and 81 are opposite to those in the third embodiment. That is, the output voltage of the control circuit 105 is applied as the control voltage V2 to the control terminal 81 of the variable gain amplifier circuit, and a constant voltage from the constant voltage source 107 is applied to the control terminal 79.

With such a configuration, as described in the first embodiment, the mutual conductance of the feedback FET can be changed by the control voltage V2. That is,
The gain of the negative feedback variable gain amplifier circuit can be controlled. As a result, an AGC circuit having a wide dynamic range can be realized.

Fifth Embodiment FIG. 17 is a block diagram showing a fifth embodiment of the variable gain amplifier circuit according to the present invention. In this embodiment, the control terminal 7
The voltages V1 and V2 supplied to 9 and 81 are both supplied from the control circuit 105.

With this configuration, as described in the first embodiment, the gain of this variable gain amplifier circuit can be controlled by the two control voltages V1 and V2. Since the target value can be determined with high accuracy by using two control voltages, a highly accurate AGC circuit can be realized.

[0065]

As described above, according to the present invention,
The following effects can be obtained.

(1) As described above, for an input signal having a large amplitude, the mutual conductance of the feedback transistor is increased in order to increase the feedback amount. Therefore, the output impedance of the feedback transistor is lowered. That is, the impedance seen from the input terminal of the amplifier circuit decreases. As a result, when a large-amplitude input signal is supplied, the input voltage applied to the amplification transistor can be suppressed low. Therefore, it is possible to increase the maximum allowable input level and realize a low distortion operation.

(2) Since the input impedance of the feedback transistor is kept substantially constant, the output impedance of the amplifier circuit is also kept substantially constant. Therefore, it is possible to realize a variable gain amplifier circuit in which the output matching does not shift even if the gain is changed.

Further, the transistor (especially FET) is
Generally, due to the unilateral characteristic, the signal transfer from the main current terminal to the control terminal is negligibly small. Therefore, the negative feedback variable gain amplifier circuit according to the present invention can prevent signal transmission from the input side to the output side through the feedback circuit. This can reduce the distortion of the variable gain amplifier circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a conventional negative feedback amplifier circuit.

FIG. 2 is a block diagram showing a conventional variable gain amplifier circuit.

FIG. 3 is a block diagram showing a conventional variable gain amplifier circuit.

FIG. 4 is a block diagram showing an improved conventional variable gain amplifier circuit.

5 is a control voltage applied to the FET 43b of FIG. 4,
It is a graph which shows the relationship with resistance between a drain and a source.

FIG. 6 is a circuit diagram showing a conventional negative feedback amplifier circuit.

FIG. 7 is a circuit diagram showing a conventional negative feedback amplifier circuit.

FIG. 8 is a circuit diagram showing a conventional negative feedback variable gain amplifier circuit.

FIG. 9 is a block diagram of a first embodiment of a negative feedback variable gain amplifier circuit according to the present invention.

10A is a feedback FE in the first embodiment of FIG.
9B is a graph showing the relationship between the gate bias voltage of T and the input / output impedance and transconductance of the feedback FET, FIG. 9B shows the feedback FET in the first embodiment of FIG.
3 is a graph showing the relationship between the drain bias voltage of the FET, the input / output impedance of the feedback FET, and the mutual conductance.

11 is a diagram illustrating a gate bias voltage of a feedback FET, an output of a variable gain amplifier circuit, and D / in the first embodiment of FIG.
It is a graph which shows the relationship with U ratio.

FIG. 12 is a diagram illustrating a negative feedback variable gain amplifier circuit according to the first embodiment of FIG. 9 in which input power and D when output is constant;
It is a graph which shows the relationship with / U ratio.

FIG. 13 is a graph showing the relationship between the output and the D / U ratio during the minimum gain operation in the negative feedback variable gain amplifier circuit according to the first embodiment of FIG. 9.

FIG. 14 is a second negative feedback variable gain amplifier circuit according to the present invention.
It is a block diagram of an Example.

FIG. 15 is a third negative feedback variable gain amplifier circuit according to the present invention.
It is a block diagram of an Example.

FIG. 16 is a fourth example of the negative feedback variable gain amplifier circuit according to the present invention.
It is a block diagram of an Example.

FIG. 17 is a fifth negative feedback variable gain amplifier circuit according to the present invention.
It is a block diagram of an Example.

[Explanation of symbols]

70 Variable gain amplifier circuit 71 amplification FET 73 Feedback FET 75 capacitor 77 Resistance 79 Gate control terminal 81 Drain control terminal 83,85 Bypass capacitor 87 Input matching circuit 91 Input terminal 93 Output matching circuit 95 output terminals 97 Cascade amplifier load FET 99 control terminal 101 input terminal 103 power detector 105 control circuit 107 constant voltage source

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ identifier FI H03H 11/24 H03H 11/24 B (58) Fields investigated (Int.Cl. ⁷ , DB name) H03F 1/34 H03G 3 / 12

Claims (10)

(57) [Claims] 1. An amplifier for amplifying an input signal, a first terminal to which a first voltage is applied, a second terminal to which a second voltage is applied, and a control terminal to the first terminal. A feedback transistor having a first main current terminal connected to the input terminal of the amplifier and a second main current terminal connected to the second terminal; and an output terminal of the amplifier and a control terminal of the feedback transistor. A negative feedback variable gain amplifier circuit, comprising: a capacitor connected between and, and changing its gain in response to at least one of the first voltage and the second voltage. 2. The negative feedback variable gain amplifier circuit further includes a measuring unit that measures the power of an input signal to the negative feedback variable gain amplifier circuit and outputs a detection signal indicating the power, The negative feedback variable gain amplifier circuit according to claim 1, further comprising: a control circuit that outputs the first voltage based on the above, and a constant voltage source that outputs the second voltage. 3. The negative feedback variable gain amplifier circuit further measures a constant voltage source that outputs the first voltage and the power of an input signal to the negative feedback variable gain amplifier circuit, and indicates the power. The negative feedback variable gain amplifier circuit according to claim 1, further comprising: a measuring unit that outputs a detection signal; and a control circuit that outputs the second voltage based on the detection signal. 4. The negative feedback variable gain amplifier circuit further includes a measuring unit that measures the power of the input signal to the negative feedback variable gain amplifier circuit and outputs a detection signal indicating the power, The negative feedback variable gain amplifier circuit according to claim 1, further comprising a control circuit that outputs the first voltage and the second voltage based on the above. 5. The negative feedback variable gain amplifier circuit according to claim 1, wherein at least one of the first terminal and the second terminal is grounded via a capacitor. 6. The negative feedback variable gain amplifier circuit according to claim 1, wherein the amplifier is a cascode amplifier. 7. The negative feedback variable gain amplifier circuit according to claim 1, wherein the amplifier is a multistage amplifier. 8. The feedback transistor is a field effect transistor, the control terminal is its gate terminal, the first main current terminal is its source terminal, and the second main current terminal is its drain terminal. The negative feedback variable gain amplifier circuit according to any one of claims 1 to 7. 9. The feedback transistor is a bipolar transistor, the control terminal is its base terminal, the first main current terminal is its emitter terminal, and the second main current terminal is its collector terminal. The negative feedback variable gain amplifier circuit according to any one of claims 1 to 7. 10. The feedback transistor is a heterojunction bipolar transistor, the control terminal is its base terminal, the first main current terminal is its emitter terminal, and the second main current terminal is its collector terminal. The negative feedback variable gain amplifier circuit according to any one of claims 1 to 7.