CN112951725A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN112951725A
CN112951725A CN201911259682.7A CN201911259682A CN112951725A CN 112951725 A CN112951725 A CN 112951725A CN 201911259682 A CN201911259682 A CN 201911259682A CN 112951725 A CN112951725 A CN 112951725A
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semiconductor layer
substrate
layer
source
sacrificial
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CN112951725B (en
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, wherein the substrate comprises a bottom semiconductor layer, a sacrificial semiconductor layer and a top semiconductor layer which are sequentially stacked from bottom to top, a grid structure is formed on the substrate, source and drain doped regions are formed in the substrate on two sides of the grid structure, and the bottoms of the source and drain doped regions are located above the bottom of the sacrificial semiconductor layer; etching the substrate exposed from the source-drain doped region to form a groove, wherein the groove at least penetrates through the top semiconductor layer and the sacrificial semiconductor layer; transversely etching the sacrificial semiconductor layer exposed from the side wall of the groove to form a first groove surrounded by the bottom semiconductor layer, the sacrificial semiconductor layer and the top semiconductor layer; and forming an isolation structure in the groove, wherein the isolation structure, the bottom semiconductor layer, the sacrificial semiconductor layer and the top semiconductor layer enclose an air gap at the position of the first groove. The air gap is formed to isolate the source-drain doped region from the bottom semiconductor layer, so that leakage current and parasitic capacitance are reduced, and the performance of the semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
MOS (metal-oxide-semiconductor) transistors, are one of the most important components in modern integrated circuits. The basic structure of the MOS transistor includes: the semiconductor device includes a semiconductor substrate, a gate electrode (gate) on the semiconductor substrate, a source (source) region in the semiconductor substrate on one side of the gate electrode, and a drain (drain) region in the semiconductor substrate on the other side of the gate electrode. The source region and the drain region are formed by high doping, and are divided into N-type doping and P-type doping according to different transistor types.
When the MOS transistor is turned on, a conductive channel is formed in the semiconductor substrate between the source region and the drain region. For example, in the case of an N-type MOS transistor, when a voltage between a gate electrode and a source region (i.e., a gate-source voltage Vgs) is greater than a threshold voltage (Vth), a conduction channel is formed and the MOS transistor is turned on.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve the performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a bottom semiconductor layer, a sacrificial semiconductor layer and a top semiconductor layer which are sequentially stacked from bottom to top, a grid structure is formed on the substrate, source drain doped regions are formed in the substrate on two sides of the grid structure, the bottoms of the source drain doped regions are positioned above the bottom of the sacrificial semiconductor layer, and the direction which is vertical to the extending direction of the grid structure and parallel to the surface of the substrate is transverse; etching the substrate which is positioned on one side of the source-drain doped region, which is far away from the grid structure, and is exposed by the source-drain doped region, and forming a groove in the substrate, wherein the groove at least penetrates through the top semiconductor layer and the sacrificial semiconductor layer; the sacrificial semiconductor layer exposed out of the side wall of the groove is transversely etched to form a first groove surrounded by the bottom semiconductor layer, the sacrificial semiconductor layer and the top semiconductor layer, and the projection of the source-drain doped region on the bottom semiconductor layer is positioned in the projection of the first groove on the bottom semiconductor layer, or the projection of the source-drain doped region on the bottom semiconductor layer is partially overlapped with the projection of the first groove on the bottom semiconductor layer; and after the first groove is formed, an isolation structure is formed in the groove, and air gaps are formed by the isolation structure, the bottom semiconductor layer, the sacrificial semiconductor layer and the top semiconductor layer at the position of the first groove.
Accordingly, an embodiment of the present invention provides a semiconductor structure, including: the semiconductor device comprises a substrate, a first substrate and a second substrate, wherein the substrate comprises a bottom semiconductor layer, a sacrificial semiconductor layer and a top semiconductor layer which are sequentially stacked from bottom to top, and a first groove is formed by the bottom semiconductor layer, the sacrificial semiconductor layer and the top semiconductor layer in a surrounding mode; a device gate structure on the substrate; the source-drain doped region is positioned in the substrate on two sides of the device gate structure, the bottom of the source-drain doped region is positioned above the bottom of the sacrificial semiconductor layer, and the projection of the source-drain doped region on the bottom semiconductor layer is positioned in the projection of the first groove on the bottom semiconductor layer, or the projection of the source-drain doped region on the bottom semiconductor layer is partially overlapped with the projection of the first groove on the bottom semiconductor layer; and the isolation structure is positioned on one side of the first groove, which is far away from the device gate structure, in the substrate exposed by the source-drain doped region, the bottom of the isolation structure is in contact with the bottom semiconductor layer, and air gaps are formed by the isolation structure, the bottom semiconductor layer, the sacrificial semiconductor layer and the top semiconductor layer at the position of the first groove.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming a semiconductor structure disclosed by the embodiment of the invention, a substrate with a laminated structure is provided, the substrate comprises a bottom semiconductor layer, a sacrificial semiconductor layer and a top semiconductor layer which are sequentially stacked from bottom to top, and then the substrate which is positioned on one side of the source-drain doped region far away from the grid structure and is exposed by the source-drain doped region is etched, forming a trench in the substrate, the trench extending through at least the top semiconductor layer and the sacrificial semiconductor layer, then, the sacrificial semiconductor layer exposed from the side wall of the groove is transversely etched to form a first groove surrounded by the bottom semiconductor layer, the sacrificial semiconductor layer and the top semiconductor layer, after an isolation structure is formed in the groove, air gaps are formed by the isolation structure, the bottom semiconductor layer, the sacrificial semiconductor layer and the top semiconductor layer in a surrounding mode at the position of the first groove; an air gap is formed below the source-drain doped region to isolate the source-drain doped region from the bottom semiconductor layer, so that leakage current and parasitic capacitance between the source-drain doped region and the bottom semiconductor layer are reduced, and the performance of the semiconductor structure is improved.
Drawings
Fig. 1 to 7 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure according to an embodiment of the present invention;
fig. 8 to 15 are schematic structural diagrams corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
In the current semiconductor structure, source and drain doped regions are located in the substrate at both sides of the gate structure. However, the source-drain doped region is in contact with the substrate, which results in large leakage current and parasitic capacitance, and further results in reduced performance of the semiconductor structure.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a bottom semiconductor layer, a sacrificial semiconductor layer and a top semiconductor layer which are sequentially stacked from bottom to top, a grid structure is formed on the substrate, source drain doped regions are formed in the substrate on two sides of the grid structure, the bottoms of the source drain doped regions are positioned above the bottom of the sacrificial semiconductor layer, and the direction which is vertical to the extending direction of the grid structure and parallel to the surface of the substrate is transverse; etching the substrate which is positioned on one side of the source-drain doped region, which is far away from the grid structure, and is exposed by the source-drain doped region, and forming a groove in the substrate, wherein the groove at least penetrates through the top semiconductor layer and the sacrificial semiconductor layer; the sacrificial semiconductor layer exposed out of the side wall of the groove is transversely etched to form a first groove surrounded by the bottom semiconductor layer, the sacrificial semiconductor layer and the top semiconductor layer, and the projection of the source-drain doped region on the bottom semiconductor layer is positioned in the projection of the first groove on the bottom semiconductor layer, or the projection of the source-drain doped region on the bottom semiconductor layer is partially overlapped with the projection of the first groove on the bottom semiconductor layer; and after the first groove is formed, an isolation structure is formed in the groove, and air gaps are formed by the isolation structure, the bottom semiconductor layer, the sacrificial semiconductor layer and the top semiconductor layer at the position of the first groove. According to the embodiment of the invention, the air gap is formed below the source-drain doped region to isolate the source-drain doped region from the bottom semiconductor layer, so that the leakage current and the parasitic capacitance are reduced, and the performance of the semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 1 to 7 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 1, a substrate 100 is provided, where the substrate 100 includes a bottom semiconductor layer 110, a sacrificial semiconductor layer 120, and a top semiconductor layer 130 stacked in sequence from bottom to top, a gate structure 200 is formed on the substrate 100, source and drain doped regions 220 are formed in the substrate 100 at two sides of the gate structure 200, the bottoms of the source and drain doped regions 220 are located above the bottom of the sacrificial semiconductor layer 120, and a direction perpendicular to an extending direction of the gate structure 200 and parallel to a surface of the substrate 100 is a transverse direction.
In the present embodiment, the formation method is used to form a fin field effect transistor (FinFET). As an example, the bottom semiconductor layer 110 is used as a substrate, and the sacrificial semiconductor layer 120 and the top semiconductor layer 130 are used as fins. In other embodiments, the bottom semiconductor layer and the sacrificial semiconductor layer are used as a substrate and the top semiconductor layer is used as a fin when forming the FinFET.
In other embodiments, the formation method may also be used to form planar transistors or Gate-all-around (GAA) transistors. The semiconductor structure to be formed can be one or two of a P-type transistor and an N-type transistor.
The subsequent process further comprises: etching the substrate 100 which is located on one side of the source-drain doped region 220 away from the gate structure 200 and is exposed by the source-drain doped region 220, and forming a groove in the substrate 100, wherein the groove at least penetrates through the top semiconductor layer 130 and the sacrificial semiconductor layer 120; the sacrificial semiconductor layer 120 exposed at the sidewall of the trench is laterally etched to form a first recess surrounded by the bottom semiconductor layer 110, the sacrificial semiconductor layer 120, and the top semiconductor layer 130. Wherein the first recess is used to prepare for forming an air gap between the source drain doped region 220 and the bottom semiconductor layer 110.
The sacrificial semiconductor layer 120 is used to provide a process base for the formation of the first recess. Therefore, the materials of the bottom semiconductor layer 110, the sacrificial semiconductor layer 120, and the top semiconductor layer 130 need to satisfy: in the step of laterally etching the sacrificial semiconductor layer 120 exposed from the sidewall of the trench, the etching selection ratio between the sacrificial semiconductor layer 120 and the top semiconductor layer 130 is greater than 50:1, and the etching selection ratio between the sacrificial semiconductor layer 120 and the bottom semiconductor layer 110 is greater than 50: 1.
In this embodiment, the bottom semiconductor layer 110 and the top semiconductor layer 130 are both made of Si, and the sacrificial semiconductor layer 120 is made of SiGe. In the subsequent step of performing lateral etching on the sacrificial semiconductor layer 120, the etching selectivity of SiGe and Si is relatively high, and by setting the material of the sacrificial semiconductor layer 120 to be SiGe, the influence of the lateral etching process on the bottom semiconductor layer 110 and the top semiconductor layer 130 can be effectively reduced, so that the influence on the performance of the semiconductor structure is reduced. When the semiconductor structure to be formed is an N-type transistor, the bottom semiconductor layer 110 and the top semiconductor layer 130 are both made of Si, the sacrificial semiconductor layer 120 is made of SiGe, and the SiGe is used for generating compressive stress, so that tensile stress is generated in Si, and the performance of the N-type transistor is further improved.
In other embodiments, the material of the sacrificial semiconductor layer may also be a III-V semiconductor material. The etch selectivity of the III-V semiconductor material to Si is also relatively high and the difference in lattice constant from Si is small. For example, the III-V semiconductor material may be SiC.
The thickness of the sacrificial semiconductor layer 120 should not be too small, nor too large. If the thickness of the sacrificial semiconductor layer 120 is too small, the size of the air gap formed subsequently along the normal direction of the surface of the substrate 100 is too small, and the difficulty of subsequent lateral etching is easily increased; if the thickness of the sacrificial semiconductor layer 120 is too large, the thickness of the bottom semiconductor layer 110 or the top semiconductor layer 130 may not meet the respective performance requirements under the condition that the total thickness of the substrate 100 is constant. For this reason, in the present embodiment, the thickness of the sacrificial semiconductor layer 120 is 5nm to 20 nm. For example, 10nm and 15 nm.
The thickness of the top semiconductor layer 130 should not be too small, nor too large. If the thickness of the top semiconductor layer 130 is too small, it is easy to affect the dimension of the source-drain doped region 220 along the normal direction of the surface of the substrate 100; if the thickness of the top semiconductor layer 130 is too large, the thickness of the sacrificial semiconductor layer 120 or the bottom semiconductor layer 110 may not meet the respective performance requirements if the total thickness of the substrate 100 is constant. For this reason, in the present embodiment, the thickness of the top semiconductor layer 130 is 10nm to 40 nm. For example, 20nm and 30 nm.
In this embodiment, the substrate 100 includes a device region 100a and isolation regions 100b located at two sides of the device region 100 a. In one embodiment, the isolation region 100b is used to define a formation region of an isolation structure, which may be a Single Diffusion Break (SDB) isolation structure. The isolation structure serves to achieve isolation of the adjacent device region 100a in a direction perpendicular to the extending direction of the gate structure 200.
In this embodiment, the gate structure 200 is a dummy gate structure, and the gate structure 200 is used to occupy a space for forming a device gate structure. Specifically, the gate structure 200 is a polysilicon gate structure.
In this embodiment, the substrate 100 includes a device region 100a and an isolation region 100b located at two sides of the device region 100a, and the gate structure 200 is located on the substrate 100 of the device region 100a and the isolation region 100 b. Specifically, the gate structure 200 crosses the fin (not labeled) and covers a portion of the top and a portion of the sidewalls of the fin. The direction perpendicular to the extending direction of the gate structure 200 and parallel to the surface of the substrate 100 is a lateral direction.
The source-drain doped region 220 is used as a source region or a drain region of a semiconductor structure to be formed. In this embodiment, the adjacent gate structures 200 share one source/drain doped region 220.
The type of the doped ions in the source/drain doped region 220 is the same as the conductivity type of the transistor corresponding to the semiconductor structure to be formed. For example: when a P-type transistor is formed, the type of doped ions In the source-drain doped region 220 is P-type, and the P-type ions are B ions, Ga ions or In ions; when forming an N-type transistor, the type of the doped ions in the source/drain doped region 220 is N-type, and the N-type ions are P ions, As ions, or Sb ions.
As an example, the source and drain doped regions 220 are formed by epitaxy, and the source and drain doped regions 220 are correspondingly formed in the epitaxial layer. When a P-type transistor is formed, the epitaxial layer is made of Si or SiGe; when forming an N-type transistor, the material of the epitaxial layer is Si, SiP, or SiC. In other embodiments, the source and drain doped regions may also be formed by performing ion implantation on the substrate on both sides of the gate structure.
It should be noted that, the subsequent process further includes performing lateral etching on the sacrificial semiconductor layer 120 below the source-drain doped region 220, so as to form an air gap between the source-drain doped region 220 and the bottom semiconductor layer 110 below the source-drain doped region 220, and therefore, in this embodiment, in order to form the air gap, the bottom of the source-drain doped region 220 is located above the bottom of the sacrificial semiconductor layer 120. In one embodiment, the bottom of the source/drain doped region 220 is located above the top of the sacrificial semiconductor layer 120, so that the damage to the source/drain doped region 220 is reduced during the lateral etching process of the sacrificial semiconductor layer 120.
In this embodiment, a sidewall 210 is further formed on the sidewall of the gate structure 200. The sidewall spacers 210 are used to protect the sidewalls of the gate structures 200, and the sidewall spacers 210 are further used to define the formation regions of the source and drain doped regions 220, so that a certain distance is formed between the source and drain doped regions 220 and the gate structures 200.
The material of the sidewall spacers 210 may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the sidewall spacers 210 is silicon nitride. The sidewall spacers 210 may have a single-layer structure or a stacked-layer structure. In this embodiment, the sidewall spacers 210 include offset spacers (offset spacers) covering sidewalls of the gate structure 200 and main spacers (main spacers) covering sidewalls of the offset spacers. For convenience of illustration, the offset sidewall and the main sidewall are not distinguished in this embodiment.
In this embodiment, an interlayer dielectric layer 101 is further formed on the substrate 100 exposed by the gate structure 200, and the interlayer dielectric layer 101 covers the sidewall of the gate structure 200. The interlayer dielectric layer 101 is used for realizing electrical isolation between adjacent transistors, and the interlayer dielectric layer 101 is also used for defining the size and the position of a subsequently formed device gate structure. Therefore, the material of the interlayer dielectric layer 101 is an insulating material. In this embodiment, the interlayer dielectric layer 101 is made of silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other dielectric materials such as silicon nitride or silicon oxynitride.
In this embodiment, the interlayer dielectric layer 101 is formed by a deposition process and a planarization process performed in this order. Specifically, after the interlayer dielectric layer 101 is formed, the interlayer dielectric layer 101 exposes the top surface of the gate structure 200.
Before forming the interlayer dielectric layer 101, the forming method further includes: an etch stop layer 102 is formed to conformally cover the substrate 100, the sidewall spacers 210 and the source and drain doped regions 220. Correspondingly, in the process of forming the interlayer dielectric layer 101, the planarization process also removes the etching stop layer 102 higher than the top surface of the gate structure 200, so as to retain the etching stop layer 102 located between the interlayer dielectric layer 101 and the substrate 100, between the interlayer dielectric layer 101 and the source-drain doped region 220, and between the interlayer dielectric layer 101 and the sidewall 210.
When a contact hole plug is formed above the source-drain doped region 220, the process for forming the contact hole plug includes an etching process, and the etching stop layer 102 is used for defining an etching stop position of the etching process, so that damage to the source-drain doped region 220 is reduced. In this embodiment, the material of the etch stop layer 102 is silicon nitride.
Referring to fig. 2 in combination, the gate structure 200 of the isolation region 100b is removed, and a first opening 201 is formed in the dielectric layer 101.
The first opening 201 is used to prepare a process for etching the substrate 100 to form a trench.
In this embodiment, the gate structure 200 is a dummy gate structure, so that the gate structure 200 is easily removed.
Specifically, the step of removing the gate structure 200 of the isolation region 100b includes: forming a shielding layer 202 covering the gate structure 200 of the device region 100a, wherein the shielding layer 202 exposes the gate structure 200 of the isolation region 100 b; the gate structure 200 of the isolation region 100b is etched away using the shielding layer 202 as a mask.
In this embodiment, the shielding layer 202 is made of photoresist. By selecting the photoresist, the patterning can be directly carried out by utilizing the photoetching process, so that the shielding layer 202 is formed at the preset position, and the process is simple. In other embodiments, the shielding layer may also be a laminated structure, for example: including a bottom anti-reflective coating (BARC) and a photoresist layer overlying the BARC. In one embodiment, in order to increase the process window for forming the shielding layer 202 and reduce the process difficulty of the photolithography process, in the device region 100a, the shielding layer 202 also covers the interlayer dielectric layer 101 around the gate structure 200. In other embodiments, the shielding layer may cover only the gate structure of the device region.
In this embodiment, one or both of a dry etching process and a wet etching process may be adopted to etch the gate structure 200 of the isolation region 100b to expose the substrate 100 of the isolation region 100 b.
In this embodiment, after the first opening 201 is formed, the shielding layer 202 is remained. In the subsequent process of etching the substrate 100, the shielding layer 202 can be continuously used as a mask, so that the process steps are simplified, and the process cost is reduced; moreover, by retaining the shielding layer 202, damage to the gate structure 200 of the device region 100a can be reduced in the subsequent etching process of the substrate 100.
Referring to fig. 3, the substrate 100 located on a side of the source-drain doped region 220 away from the gate structure 200 and exposed by the source-drain doped region 220 is etched, and a trench 103 is formed in the substrate 100, where the trench 103 at least penetrates through the top semiconductor layer 130 and the sacrificial semiconductor layer 120.
The trench 103 is used to provide a spatial location for the subsequent formation of an isolation structure (e.g., SDB isolation structure), and moreover, the sidewall of the trench 103 exposes the sacrificial semiconductor layer 120, thereby providing a process basis for the subsequent lateral etching of the sacrificial semiconductor layer 120. In this embodiment, the adjacent gate structures 200 share one source/drain doped region 220, and therefore, the substrate 100 of the isolation region 100b is etched to form the trench 103.
In this embodiment, the substrate 100 is etched along the first opening 201 with the shielding layer 202 as a mask. Specifically, the substrate 100 is etched using a dry etching process (e.g., an anisotropic dry etching process). The dry etching process has anisotropic etching characteristics, is beneficial to improving the sidewall morphology quality of the trench 103, is easy to control the etching amount of the substrate 100, and correspondingly reduces the probability of damage to the source-drain doped region 220.
In this embodiment, the trench 103 penetrates at least the top semiconductor layer 130 and the sacrificial semiconductor layer 120, so that after an isolation structure is formed in the trench 103, the bottom of the isolation structure can be in contact with the bottom semiconductor layer 110, and an air gap can be formed between the isolation structure and the bottom semiconductor layer, the sacrificial semiconductor layer, and the top semiconductor layer. As an example, the bottom of the trench 103 is located in the bottom semiconductor layer 110. In other embodiments, the trench bottom may also be flush with the bottom semiconductor layer top.
In this embodiment, after the trench 103 is formed, the shielding layer 202 is remained. When the sacrificial semiconductor layer 120 exposed from the sidewall of the trench 103 is laterally etched, the shielding layer 202 can be used as a mask, so that damage to the gate structure 200 of the device region 100a is reduced.
Referring to fig. 4, the sacrificial semiconductor layer 120 exposed at the sidewall of the trench 103 is laterally etched to form a first groove 125 surrounded by the bottom semiconductor layer 110, the sacrificial semiconductor layer 120, and the top semiconductor layer 130.
The sacrificial semiconductor layer 120 is laterally etched to retract the end of the sacrificial semiconductor layer 120, so that the bottom semiconductor layer 110, the sacrificial semiconductor layer 120, and the top semiconductor layer 130 form a first groove 125. The first groove 125 is used for preparing for forming an air gap between the source-drain doped region 220 and the bottom semiconductor layer 110 in a subsequent step, so that the source-drain doped region 220 and the bottom semiconductor layer 110 can be isolated through the air gap, and thus, the leakage current and the parasitic capacitance of the semiconductor structure are reduced.
As an embodiment, a projection of the source/drain doped region 220 on the bottom semiconductor layer 110 overlaps a projection of the first groove 125 on the bottom semiconductor layer 110, that is, a part of the source/drain doped region 220 is isolated from the bottom semiconductor layer 110 by an air gap. In other embodiments, the projection of the source-drain doped region on the bottom semiconductor layer is located in the projection of the first groove on the bottom semiconductor layer, that is, the whole source-drain doped region is isolated from the bottom semiconductor layer by an air gap, so that the leakage current and the parasitic capacitance of the semiconductor structure are further reduced.
Wherein, the lateral size of the first groove 125 is controlled by controlling the etching amount of the sacrificial semiconductor layer 120. In this embodiment, the sacrificial semiconductor layer 120 is laterally etched by a wet etching process. The wet etching process has the characteristic of isotropic etching, so that the effect of transverse etching is realized.
Specifically, in the process of laterally etching the sacrificial semiconductor layer 120, the etching rate of the wet etching process to the sacrificial semiconductor layer 120 is greater than the etching rate to the bottom semiconductor layer 110, and the etching rate of the wet etching process to the sacrificial semiconductor layer 120 is greater than the etching rate to the top semiconductor layer 130, so that the loss of the wet etching process to the bottom semiconductor layer 110 and the top semiconductor layer 130 is reduced.
In this embodiment, the sacrificial semiconductor layer 120 exposed from the sidewall of the trench 103 is laterally etched by HCl vapor. The difference between the etching rate of the HCl vapor to the SiGe and the etching rate of the HCl vapor to the Si is large, so that the probability that the bottom semiconductor layer 110 and the top semiconductor layer 130 are damaged can be effectively reduced by etching the sacrificial semiconductor layer 120 with the HCl vapor, and the performance of the semiconductor structure is guaranteed.
It should be noted that the amount of lateral etching on the sacrificial semiconductor layer 120 is not too small, nor too large. If the lateral etching amount is too small, the overlapping part of the projection of the source-drain doped region 220 on the bottom semiconductor layer 110 and the projection of the first groove 125 on the bottom semiconductor layer 110 is too small, even not overlapping, so that the leakage current or parasitic capacitance between the source-drain doped region 220 and the bottom semiconductor layer 110 is too large; if the amount of the lateral etching is too large, a waste of process cost and time is easily caused in the case where the first groove 125 can be used to form an air gap. For this reason, in the present embodiment, the amount of lateral etching of the sacrificial semiconductor layer 120 is 10nm to 40 nm. For example, 20nm, 25nm, 30nm, and 35 nm.
It should be further noted that, in the present embodiment, in the process of laterally etching the sacrificial semiconductor layer 120, the shielding layer 202 is used as a mask, so as to reduce damage to the gate structure 200 in the device region 100 a. Accordingly, after forming the first groove 125, the forming method further includes: the masking layer 202 is removed. Specifically, the material of the blocking layer 202 is photoresist, and therefore, the blocking layer 202 is removed by an ashing process.
Referring to fig. 5, after forming the first recess 125 (shown in fig. 4), an isolation structure 140 is formed in the trench 103 (shown in fig. 4), and the isolation structure 140 surrounds an air gap 150 with the bottom semiconductor layer 110, the sacrificial semiconductor layer 120 and the top semiconductor layer 130 at the position of the first recess 125.
An air gap 150 is formed below the source-drain doped region 220 to isolate the source-drain doped region 220 from the bottom semiconductor layer 110, so that leakage current and parasitic capacitance between the source-drain doped region 220 and the bottom semiconductor layer 110 are reduced, and the performance of the semiconductor structure is improved. The process of forming the air gap 150 is performed after the source/drain doped region 220 is formed, so that the forming process of the source/drain doped region 220 is not affected, and the forming quality of the source/drain doped region 220 is guaranteed. For example: in this embodiment, the source-drain doped region 220 is formed by epitaxy, and during the epitaxy process, the top semiconductor layer 130 is used as a growth base for epitaxial growth, so that the formation quality of the epitaxial layer is improved, and the formation quality of the source-drain doped region 220 is further improved. Since air has a smaller dielectric constant (Kvacuum ═ 1) than a dielectric material, the provision of the air gap 150 can further reduce leakage current and parasitic capacitance.
In this embodiment, the isolation structure 140 serves as a single diffusion blocking SDB isolation structure, thereby achieving isolation of the adjacent device regions 100a in a direction perpendicular to the extending direction of the gate structure 200. Therefore, the isolation structure 140 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, Plasma Enhanced Tetraethoxysilane (PETEOS), plasma enhanced silicon oxide (PEOX), or the like.
In this embodiment, the trench 103 is filled by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process to form the isolation structure 140. The PECVD process has poor hole filling performance, especially when the aspect ratio of the trench 103 is large, thereby reducing the probability of the material of the isolation structure 140 filling into the first groove 125 during the process of filling the trench 103, and further enabling the isolation structure 140 to surround the air gap 150 with the bottom semiconductor layer 110, the sacrificial semiconductor layer 120 and the top semiconductor layer 130. Accordingly, in the present embodiment, the isolation structure 140 is made of pecvd or pecvd silicon oxide. In other embodiments, the isolation structure may be formed by other chemical vapor deposition processes with poor filling performance.
In this embodiment, in the process of filling the trench 103, the material of the isolation structure 140 is also filled in the first opening 201 (as shown in fig. 4), and therefore, the isolation structure 140 is also located in the first opening 201.
In this embodiment, after filling the trench 103 and the first opening 201, the material of the isolation structure 140 further covers the gate structure 200, and therefore, the step of forming the isolation structure 140 further includes: the material of the isolation structure 140 is planarized.
With combined reference to fig. 6, after the isolation structure 140 is formed, the forming method further includes: the gate structure 200 of the device region 100a is removed (as shown in fig. 5), and a second opening 205 is formed in the interlayer dielectric layer 101.
The second opening 205 is used to provide a spatial location for a subsequent formation of a device gate structure in the device region 100 a.
In this embodiment, one or both of a dry etching process and a wet etching process may be used to etch the gate structure 200 of the device region 100 a.
Referring collectively to fig. 7, a device gate structure 250 is formed in the second opening 205 (shown in fig. 6).
In this embodiment, the device gate structure 250 is a metal gate structure, and the device gate structure 250 includes a high-k gate dielectric layer 251 conformally covering the bottom and the sidewall of the second opening 205, and a gate electrode layer 252 covering the high-k gate dielectric layer 251 and filling the second opening 205.
The high-k gate dielectric layer 251 is used to electrically isolate the gate electrode layer 252 from the channel. The material of the high-k gate dielectric layer 251 is a high-k dielectric material. Wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer 251 is HfO2. In other embodiments, the material of the high-k gate dielectric layer can be selected from ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3And the like.
The gate electrode layer 252 serves as an electrode for electrically connecting to an external circuit. In this embodiment, the gate electrode layer 252 is made of W. In other embodiments, the material of the gate electrode layer may also be Al, Cu, Ag, Au, Pt, Ni, Ti, or the like.
Fig. 8 to 15 are schematic structural diagrams corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.
The same parts of this embodiment as those of the previous embodiments will not be described again. The present embodiment differs from the previous embodiments in that: the forming method is used for forming the GAA transistor.
Referring to fig. 11, a substrate 300 is provided, the substrate 300 including a bottom semiconductor layer 310, a sacrificial semiconductor layer 320, and a top semiconductor layer 330 stacked in sequence from bottom to top, the substrate 300 further including one or more stacked channel stacks 500 formed on the top semiconductor layer 330, the channel stacks 500 including a sacrificial layer 510 and a channel layer 520 on the sacrificial layer 510.
The sacrificial layer 510 is used for supporting the channel layer 520, so as to provide a process base for the subsequent spaced-apart suspension of the channel layer 520, and the sacrificial layer 510 is also used for occupying a space position for the subsequent formation of a device gate structure, so that the channel of the formed GAA transistor is located in the channel layer 520. As an example, a channel stack 500 is formed on the top semiconductor layer 330, i.e., a sacrificial layer 510 and a channel layer 520 covering the sacrificial layer 510 are formed on the top semiconductor layer 330. In other embodiments, the number of channel stacks may also be two or more than two, i.e. the top semiconductor layer has a plurality of sacrificial layers and channel layers formed thereon in an alternating manner, according to the process requirements.
In this embodiment, the channel layer 520 is made of Si, and the sacrificial layer 510 is made of SiGe. In the subsequent process of removing the sacrificial layer 510, the etching selectivity of SiGe and Si is high, so that the influence of the removal process of the sacrificial layer 510 on the channel layer 520 can be reduced, and the performance of the semiconductor structure can be improved.
In this embodiment, the substrate 300 includes a device region 300a and isolation regions 300b located at both sides of the device region 300 a.
In this embodiment, a gate structure 400 is formed on the substrate 300, a source/drain doped region 420 is formed in the substrate 300 at two sides of the gate structure 400, and the bottom of the source/drain doped region 420 is located above the bottom of the sacrificial semiconductor layer 320, wherein a direction perpendicular to the extending direction of the gate structure 400 and parallel to the surface of the substrate 300 is a transverse direction.
In this embodiment, the gate structure 400 is located on the substrate 300 of the device region 300a and the isolation region 300b, an interlayer dielectric layer 301 is further formed on the substrate 300 exposed by the gate structure 400, and the interlayer dielectric layer 301 covers the sidewall of the gate structure 400. Specifically, the gate structure 400 crosses over the channel stack 500 and covers a portion of the top and a portion of the sidewalls of the channel stack 500, and the gate structure 400 is a dummy gate structure.
The description of the substrate 300, the gate structure, the source-drain doped region 420 and the interlayer dielectric layer 301 may be combined with the corresponding description in the foregoing embodiments, and will not be repeated herein.
In this embodiment, the source/drain doped region 420 is formed in an epitaxial manner. Therefore, before forming the source-drain doped region 420, a step of etching the substrate 300 on both sides of the gate structure 400 is further included.
The steps for forming the source/drain doped regions 420 will be described in detail with reference to fig. 8 to 11.
As shown in fig. 8, the substrate 300 on both sides of the gate structure 400 is etched, and a source/drain trench 421 is formed in the substrate 300, and the bottom of the source/drain trench 421 is located above the bottom of the sacrificial semiconductor layer 330.
The source drain trench 421 is used to provide a spatial location for forming source drain doped regions. In this embodiment, the substrate 300 on both sides of the gate structure 400 is etched by a dry etching process (e.g., an anisotropic dry etching process).
As shown in fig. 9, the sacrificial layer 510 exposed at the sidewalls of the source-drain trenches 421 is laterally etched to form a second recess 422 between the channel layer 520 and the top semiconductor layer 330.
The second groove 422 is used for providing a spatial position for forming an inner sidewall (inner spacer).
In this embodiment, the material of the top semiconductor layer 130 and the channel layer 520 is Si, and the material of the sacrificial layer 510 is SiGe, so that the sacrificial layer 510 is laterally etched by HCl vapor.
In the present embodiment, the second recess 422 is formed between the channel layer 520 and the top semiconductor layer 330. In other embodiments, the second recess may also be formed between adjacent channel layers when the number of channel stacks is two or more.
As shown in fig. 10, inner sidewalls 425 are formed in the second recesses 422 (shown in fig. 9).
The inner sidewall 425 isolates the source-drain doped region from the device gate structure, thereby reducing the parasitic capacitance between the source-drain doped region and the device gate structure, and further improving the performance of the semiconductor structure.
Therefore, the material of the inner sidewall spacers 425 is a dielectric material, such as silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbide, or silicon oxynitride. In this embodiment, the inner sidewall spacers 425 are made of silicon nitride.
Specifically, the step of forming the inner sidewall spacers 425 includes: forming a side wall material layer (not shown) by using an atomic layer deposition process, wherein the side wall material layer conformally covers the top and the side wall of the gate structure 400, the bottom and the side wall of the source/drain groove 421, and the top of the substrate 300, and is further filled in the second groove 422; the top and the side walls of the gate structure 400, the bottom and the side walls of the source-drain trenches 421, and the side wall material layer on the top of the substrate 300 are removed by etching along a direction perpendicular to the surface of the substrate 300, and the side wall material layer in the second recess 422 is reserved for being used as the inner side wall 425.
In this embodiment, a dry etching process (e.g., an anisotropic dry etching process) is used to etch the spacer material layer. The dry etching process has anisotropic etching characteristics, so that the sidewall material layer in the second groove 422 is retained, and the sidewall and the bottom of the source drain trench 421 are exposed.
Correspondingly, as shown in fig. 11, the step of forming the source/drain doped region 420 includes: after the inner side walls 425 are formed, an epitaxial layer is formed in the source/drain trenches 421 (as shown in fig. 10) by using an epitaxial process, and a source/drain doped region 420 is formed in the epitaxial layer by using a doping method.
Referring to fig. 12, etching the substrate 300 located on a side of the source-drain doped region 420 away from the gate structure 400 and exposed by the source-drain doped region 420, and forming a trench 303 in the substrate 300, where the trench 303 at least penetrates through the top semiconductor layer 330 and the sacrificial semiconductor layer 320; and laterally etching the sacrificial semiconductor layer 320 exposed from the side wall of the trench 303 to form a first groove 325 surrounded by the bottom semiconductor layer 310, the sacrificial semiconductor layer 320 and the top semiconductor layer 330.
In this embodiment, before etching the substrate 300 located on the side of the source-drain doped region 420 away from the gate structure 400 and exposed by the source-drain doped region 420, the forming method further includes: the gate structure 400 of the isolation region 300b is removed and a first opening 401 is formed in the dielectric layer 301. Accordingly, the substrate 300 is etched along the first opening 401 to form the first opening 401.
For a detailed description of the steps of forming the first opening 401, the trench 303 and the first recess 325, reference may be made to the corresponding description in the foregoing embodiments, and further description is omitted here.
It should be noted that the inner sidewalls 425 are formed on the sidewalls of the source and drain doped regions 420, and therefore, although the materials of the sacrificial layer 510 and the sacrificial semiconductor layer 320 are both SiGe, the inner sidewalls 425 can play a role in protection during the process of laterally etching the sacrificial semiconductor layer 320 exposed on the sidewalls of the trench 303, thereby reducing damage to the source and drain doped regions 420.
Referring to fig. 13, after forming the first recess 325 (shown in fig. 12), an isolation structure 340 is formed in the trench 303 (shown in fig. 12), and the isolation structure 340 encloses an air gap 350 with the bottom semiconductor layer 310, the sacrificial semiconductor layer 320 and the top semiconductor layer 330 at the position of the first recess 325.
In this embodiment, the isolation structure 340 is also formed in the first opening 401 (as shown in fig. 12).
For a detailed description of the isolation structure 340 and the forming method thereof, reference may be made to the corresponding description in the foregoing embodiments, and details are not repeated here.
Referring to fig. 14, after forming the isolation structure 340, the method further includes: removing the gate structure 400 (shown in fig. 13) in the device region 300a, and forming a second opening 405 in the interlayer dielectric layer 301; the sacrificial layer 510 exposed by the second opening 405 is removed (as shown in figure 13) to form a gap 515 between the channel layer 520 and the top semiconductor layer 330.
The gate structure 400 crosses over the channel stack 500 (as shown in fig. 13) and covers a portion of the top and a portion of the sidewall of the channel stack 500, so that the second opening 405 exposes a portion of the top and a portion of the sidewall of the channel stack 500 after the gate structure 400 of the device region 300a is removed. In this embodiment, the gate structure 200 in the device region 100a may be removed by etching using one or both of a dry etching process and a wet etching process.
In this embodiment, since the sacrificial layer 510 exposed by the second opening 405 is removed by HCl vapor, the etching rate of the sacrificial layer 510 by the wet etching process is much higher than that of the channel layer 520 and the top semiconductor layer 330.
It is noted that in other embodiments, when the number of channel stacks is two or more, the gap may also be formed between adjacent channel layers.
Referring to fig. 15, a device gate structure 450 is formed in the second opening 405 (shown in fig. 14) and the gap 515 (shown in fig. 14), the device gate structure 450 surrounding the channel layer 520.
In this embodiment, the device gate structure 450 surrounds the channel layer 520 from the periphery of the channel layer 520 exposed in the second opening 405, i.e., the device gate structure 450 covers the upper surface, the lower surface, and the side surfaces of the channel layer 520.
In this embodiment, the device gate structure 450 is a metal gate structure, and the device gate structure 450 includes a high-k gate dielectric layer 251 and a gate electrode layer 252 covering the high-k gate dielectric layer 251. For a detailed description of the device gate structure 450, reference may be made to the corresponding description in the foregoing embodiments, and details are not repeated here.
For a specific description of the forming method in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details are not repeated here.
Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 7, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100, wherein the substrate 100 includes a bottom semiconductor layer 110, a sacrificial semiconductor layer 120, and a top semiconductor layer 130 stacked in sequence from bottom to top, and a first groove 125 (shown in fig. 4) is defined by the bottom semiconductor layer 110, the sacrificial semiconductor layer 120, and the top semiconductor layer 130; a device gate structure 250 on the substrate 100; the source-drain doped region 220 is located in the substrate 100 on two sides of the device gate structure 250, the bottom of the source-drain doped region 220 is located above the bottom of the sacrificial semiconductor layer 120, and the projection of the source-drain doped region 220 on the bottom semiconductor layer 110 is located in the projection of the first groove 125 on the bottom semiconductor layer 110, or the projection of the source-drain doped region 220 on the bottom semiconductor layer 110 is partially overlapped with the projection of the first groove 125 on the bottom semiconductor layer 110; the isolation structure 140 is located on one side of the first groove 125, which is far away from the device gate structure 250, in the substrate 100 exposed by the source-drain doped region 220, the bottom of the isolation structure 140 is in contact with the bottom semiconductor layer 110, and at the position of the first groove 125, the isolation structure 140, the bottom semiconductor layer 110, the sacrificial semiconductor layer 120 and the top semiconductor layer 130 enclose an air gap 150.
At the location of the first recess 125, the isolation structure 140 encloses an air gap 150 with the bottom semiconductor layer 110, the sacrificial semiconductor layer 120 and the top semiconductor layer 130. The air gap 150 is arranged below the source-drain doped region 220 to isolate the source-drain doped region 220 from the bottom semiconductor layer 110, so that leakage current and parasitic capacitance between the source-drain doped region 220 and the bottom semiconductor layer 110 are reduced, and the performance of the semiconductor structure is improved. Since air has a smaller dielectric constant (Kvacuum ═ 1) than a dielectric material, the provision of the air gap 150 can further reduce leakage current and parasitic capacitance.
In this embodiment, the semiconductor structure is a FinFET. As an example, the bottom semiconductor layer 110 is used as a substrate, and the sacrificial semiconductor layer 120 and the top semiconductor layer 130 are used as fins. In other embodiments, when the semiconductor structure is a FinFET, the bottom semiconductor layer and the sacrificial semiconductor layer are used as a substrate and the top semiconductor layer is used as a fin. In other embodiments, the semiconductor structure may also be a planar transistor or a GAA transistor.
The first recess 125 is used to prepare for the formation of the air gap 150. In the method for forming the semiconductor structure, the first groove 125 is obtained by laterally etching the sacrificial semiconductor layer 120.
In this embodiment, the bottom semiconductor layer 110 and the top semiconductor layer 130 are both made of Si, and the sacrificial semiconductor layer 120 is made of SiGe. In other embodiments, the material of the sacrificial semiconductor layer may also be a III-V semiconductor material. The etch selectivity of the III-V semiconductor material to Si is also relatively high and the difference in lattice constant from Si is small. For example, the III-V semiconductor material may be SiC.
In this embodiment, a direction perpendicular to the extending direction of the device gate structure 250 and parallel to the surface of the substrate 100 is a transverse direction, and the transverse dimension of the first groove 125 is not too small or too large. If the lateral dimension of the first groove 125 is too small, it is easy to cause too little or no overlap between the projection of the source-drain doped region 220 on the bottom semiconductor layer 110 and the projection of the first groove 125 on the bottom semiconductor layer 110, thereby causing too large leakage current or parasitic capacitance between the source-drain doped region 220 and the bottom semiconductor layer 110; if the lateral dimension of the first recess 125 is too large, a waste of process costs and time for forming the semiconductor structure is incurred. For this reason, in the present embodiment, the lateral dimension of the first groove 125 is 10nm to 40 nm.
In this embodiment, in order to make the size of the air gap 150 along the normal direction of the surface of the substrate 100 meet the process requirements, and make the thickness of the bottom semiconductor layer 110 or the top semiconductor layer 130 meet the respective performance requirements, the thickness of the sacrificial semiconductor layer 120 is 5nm to 20 nm; similarly, in order to make the dimension of the source/drain doped region 220 along the normal direction of the surface of the substrate 100 meet the process requirement, and make the thickness of the sacrificial semiconductor layer 120 or the bottom semiconductor layer 110 meet the performance requirement, the thickness of the top semiconductor layer 130 is 10nm to 40 nm.
In this embodiment, the substrate 100 includes a device region 100a and isolation regions 100b located at two sides of the device region 100 a. In one embodiment, the isolation region 100b is used to achieve isolation of adjacent device regions 100a in a direction perpendicular to the direction in which the device gate structure 250 extends.
In this embodiment, the device gate structure 250 is located on the substrate 100 of the device region 100 a. Specifically, the device gate structure 250 crosses over the fin (not labeled) and covers a portion of the top and a portion of the sidewall of the fin, the device gate structure 250 is a metal gate structure, and the device gate structure 250 includes a high-k gate dielectric layer 251 and a gate electrode layer 252 covering the high-k gate dielectric layer 251.
The semiconductor structure further includes: and the side walls 210 are positioned on the side walls of the device gate structure 250. The sidewall spacers 210 are used to protect the sidewalls of the gate structures 250 of the devices, and the sidewall spacers 210 are also used to define the formation regions of the source-drain doped regions 220. In this embodiment, the material of the sidewall spacers 210 is silicon nitride.
The source-drain doped region 220 is used as a source region or a drain region of the semiconductor structure. In this embodiment, the adjacent device gate structures 250 share one source/drain doped region 220. As an example, the source and drain doped regions 220 are formed by epitaxy, and the source and drain doped regions 220 are correspondingly located in the epitaxy layer.
In this embodiment, at the position of the first groove 125, the isolation structure 140, the bottom semiconductor layer 110, the sacrificial semiconductor layer 120, and the top semiconductor layer 130 enclose an air gap 150, and in order to form the air gap 150, the bottom of the source-drain doped region 220 is located above the bottom of the sacrificial semiconductor layer 120. In one embodiment, the bottom of the source and drain doped regions 220 is located above the top of the sacrificial semiconductor layer 120, thereby reducing damage to the source and drain doped regions 220 during the formation of the first recess 125.
In this embodiment, the projection of the source-drain doped region 220 on the bottom semiconductor layer 110 overlaps with the projection of the first groove 125 on the bottom semiconductor layer 110. In other embodiments, a projection of the source-drain doped region on the bottom semiconductor layer is located in a projection of the first groove on the bottom semiconductor layer.
In this embodiment, the semiconductor structure further includes: and the interlayer dielectric layer 101 is positioned on the substrate 100 exposed from the device gate structure 250, and the interlayer dielectric layer 101 covers the side wall of the device gate structure 250. In this embodiment, the interlayer dielectric layer 101 is made of silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other dielectric materials such as silicon nitride or silicon oxynitride.
In addition, the semiconductor structure further includes: and the etching stop layer 102 is positioned between the interlayer dielectric layer 101 and the substrate 100, between the interlayer dielectric layer 101 and the source-drain doped region 220, and between the interlayer dielectric layer 101 and the side wall 210. In this embodiment, the material of the etch stop layer 102 is silicon nitride.
In this embodiment, the isolation structure 140 serves as a single diffusion blocking SDB isolation structure, thereby achieving isolation of the adjacent device region 100a in a direction perpendicular to the extending direction of the device gate structure 250. Specifically, the isolation structure 140 is located in the substrate 100 of the isolation region 100b, and the isolation structure 140 further extends into the interlayer dielectric layer 101.
The isolation structure 140 is made of an insulating material. In this embodiment, the isolation structure 140 is formed by using a plasma enhanced chemical vapor deposition process, and therefore, the isolation structure 140 is made of plasma enhanced tetraethoxysilane or plasma enhanced silicon oxide.
The semiconductor structure may be formed by the formation method described in the first embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing first embodiment, which is not repeated herein.
Referring to fig. 15, a schematic structural diagram of another embodiment of a semiconductor structure of the present invention is shown.
The same parts of this embodiment as those of the previous embodiments will not be described again. The present embodiment differs from the previous embodiments in that: the semiconductor structure is a GAA transistor.
In this embodiment, the substrate 300 includes a bottom semiconductor layer 310, a sacrificial semiconductor layer 320, and a top semiconductor layer 330 stacked in sequence from bottom to top, and the substrate 300 further includes a channel structure layer (not shown) located on the top semiconductor layer 330 and spaced apart from the top semiconductor layer 330, where the channel structure layer includes one channel layer 520 or a plurality of channel layers 520 spaced apart from each other.
The channel structure layer is positioned on the top semiconductor layer 330 and spaced apart from the top semiconductor layer 330, and the channel structure layer includes one channel layer 520 or a plurality of channel layers 520 spaced apart such that the device gate structure 450 surrounds the channel layer 520. In this embodiment, the material of the channel layer 520 is Si. As an example, the channel structure layer includes only one channel layer 520. In other embodiments, in the channel structure layer, the number of channel layers is two or more than two.
In this embodiment, the substrate 300 includes a device region 300a and isolation regions 300b located at both sides of the device region 300a, the device gate structure 250 is located on the substrate 300 of the device region 300a, the device gate structure 450 spans across the channel structure layer, and the device gate structure 450 covers a portion of the top and a portion of the sidewalls of the channel structure layer and surrounds the channel layer 520.
The semiconductor structure further includes: and inner sidewalls 425 between adjacent channel layers 520 or between the channel layer 520 and the top semiconductor layer 330, wherein the inner sidewalls 425 cover sidewalls of the source-drain doped regions 420. The source-drain doped region 420 and the device gate structure 250 are isolated by the inner sidewall 425, thereby reducing the parasitic capacitance between the device gate structure 250 and the conductive plug. Therefore, the material of the inner sidewall 425 is a dielectric material. In this embodiment, the inner sidewall spacers 425 are made of silicon nitride.
The semiconductor structure may be formed by the formation method described in the second embodiment, or may be formed by other formation methods. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing second embodiment, which is not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (22)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a bottom semiconductor layer, a sacrificial semiconductor layer and a top semiconductor layer which are sequentially stacked from bottom to top, a grid structure is formed on the substrate, source drain doped regions are formed in the substrate on two sides of the grid structure, the bottoms of the source drain doped regions are positioned above the bottom of the sacrificial semiconductor layer, and the direction which is vertical to the extending direction of the grid structure and parallel to the surface of the substrate is transverse;
etching the substrate which is positioned on one side of the source-drain doped region, which is far away from the grid structure, and is exposed by the source-drain doped region, and forming a groove in the substrate, wherein the groove at least penetrates through the top semiconductor layer and the sacrificial semiconductor layer;
the sacrificial semiconductor layer exposed out of the side wall of the groove is transversely etched to form a first groove surrounded by the bottom semiconductor layer, the sacrificial semiconductor layer and the top semiconductor layer, and the projection of the source-drain doped region on the bottom semiconductor layer is positioned in the projection of the first groove on the bottom semiconductor layer, or the projection of the source-drain doped region on the bottom semiconductor layer is partially overlapped with the projection of the first groove on the bottom semiconductor layer;
and after the first groove is formed, an isolation structure is formed in the groove, and air gaps are formed by the isolation structure, the bottom semiconductor layer, the sacrificial semiconductor layer and the top semiconductor layer at the position of the first groove.
2. The method of forming a semiconductor structure of claim 1, wherein the substrate comprises a device region and isolation regions on both sides of the device region;
in the step of providing the substrate, the gate structure is located on the substrate of the device region and the isolation region, and an interlayer dielectric layer is further formed on the substrate exposed by the gate structure and covers the side wall of the gate structure;
before etching the substrate which is located on one side of the source-drain doped region far away from the gate structure and exposed by the source-drain doped region, the forming method further comprises: removing the grid structure of the isolation region, and forming a first opening in the dielectric layer;
the step of etching the substrate which is positioned on one side of the source-drain doped region, far away from the grid structure and exposed by the source-drain doped region comprises the following steps: etching the substrate along the first opening;
in the step of forming an isolation structure in the trench, the isolation structure is also located in the first opening.
3. The method of claim 1, wherein in the step of providing a base, the bottom semiconductor layer is used as a substrate, and the sacrificial semiconductor layer and the top semiconductor layer are used as fins;
or the bottom semiconductor layer and the sacrificial semiconductor layer are used as substrates, and the top semiconductor layer is used as a fin part;
the gate structure crosses over the fin and covers part of the top and part of the side wall of the fin.
4. The method for forming a semiconductor structure according to claim 3, wherein the gate structure is a dummy gate structure;
after the isolation structure is formed, the forming method further comprises: removing the grid structure of the device region, and forming a second opening in the interlayer dielectric layer; and forming a device gate structure in the second opening.
5. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, the substrate further comprises one or more stacked channel stacks formed on the top semiconductor layer, the channel stacks comprising a sacrificial layer and a channel layer on the sacrificial layer;
the gate structure spans across the channel stack and covers a portion of the top and a portion of the sidewalls of the channel stack.
6. The method for forming a semiconductor structure according to claim 5, further comprising, before forming the source-drain doped region: etching the substrate on two sides of the grid structure, and forming a source drain groove in the substrate, wherein the bottom of the source drain groove is positioned above the bottom of the sacrificial semiconductor layer; transversely etching the sacrificial layer exposed from the side wall of the source drain groove, and forming a second groove between the adjacent channel layers or between the channel layers and the top semiconductor layer; forming an inner side wall in the second groove;
the step of forming the source-drain doped region comprises the following steps: and after the inner side wall is formed, an epitaxial layer is formed in the source drain groove by adopting an epitaxial process, and a source drain doped region is formed in the epitaxial layer in a doping mode.
7. The method for forming a semiconductor structure according to claim 5, wherein the gate structure is a dummy gate structure;
after the isolation structure is formed, the forming method further comprises: removing the grid structure of the device region, and forming a second opening in the interlayer dielectric layer; removing the sacrificial layer exposed by the second opening to form a gap between adjacent channel layers or between the channel layer and the top semiconductor layer; forming a device gate structure in the second opening and the gap, the device gate structure surrounding the channel layer.
8. The method for forming the semiconductor structure according to claim 1, wherein a bottom of the source-drain doped region is located above a top of the sacrificial semiconductor layer.
9. The method of claim 1, wherein the bottom semiconductor layer and the top semiconductor layer are both Si, and the sacrificial semiconductor layer is SiGe or a III-V semiconductor material.
10. The method of forming a semiconductor structure of claim 1, wherein the sacrificial semiconductor layer exposed at the trench sidewalls is laterally etched by HCl vapor.
11. The method of claim 1, wherein the isolation structure is formed by filling the trench with a plasma enhanced chemical vapor deposition process.
12. The method of forming a semiconductor structure of claim 1, wherein the sacrificial semiconductor layer has a thickness of 5nm to 20nm and the top semiconductor layer has a thickness of 10nm to 40 nm.
13. The method of forming a semiconductor structure according to any one of claim 1, wherein in the step of laterally etching the sacrificial semiconductor layer exposed at the side wall of the trench, a lateral etching amount of the sacrificial semiconductor layer is 10nm to 40 nm.
14. A semiconductor structure, comprising:
the semiconductor device comprises a substrate, a first substrate and a second substrate, wherein the substrate comprises a bottom semiconductor layer, a sacrificial semiconductor layer and a top semiconductor layer which are sequentially stacked from bottom to top, and a first groove is formed by the bottom semiconductor layer, the sacrificial semiconductor layer and the top semiconductor layer in a surrounding mode;
a device gate structure on the substrate;
the source-drain doped region is positioned in the substrate on two sides of the device gate structure, the bottom of the source-drain doped region is positioned above the bottom of the sacrificial semiconductor layer, and the projection of the source-drain doped region on the bottom semiconductor layer is positioned in the projection of the first groove on the bottom semiconductor layer, or the projection of the source-drain doped region on the bottom semiconductor layer is partially overlapped with the projection of the first groove on the bottom semiconductor layer;
and the isolation structure is positioned on one side of the first groove, which is far away from the device gate structure, in the substrate exposed by the source-drain doped region, the bottom of the isolation structure is in contact with the bottom semiconductor layer, and air gaps are formed by the isolation structure, the bottom semiconductor layer, the sacrificial semiconductor layer and the top semiconductor layer at the position of the first groove.
15. The semiconductor structure of claim 14, wherein the substrate comprises a device region and isolation regions on both sides of the device region;
the device gate structure is positioned on the substrate of the device region;
the semiconductor structure further includes: the interlayer dielectric layer is positioned on the substrate exposed out of the device gate structure and covers the side wall of the device gate structure;
the isolation structure is located in the substrate of the isolation region and further extends into the interlayer dielectric layer.
16. The semiconductor structure of claim 14, wherein the bottom semiconductor layer is to serve as a substrate, the sacrificial semiconductor layer and top semiconductor layer are to serve as fins;
or the bottom semiconductor layer and the sacrificial semiconductor layer are used as substrates, and the top semiconductor layer is used as a fin part;
the device gate structure crosses over the fin and covers part of the top and part of the side wall of the fin.
17. The semiconductor structure of claim 14, wherein the substrate further comprises a channel structure layer on and spaced apart from the top semiconductor layer, the channel structure layer comprising one channel layer or a plurality of spaced apart channel layers;
the device gate structure crosses over the channel structure layer, covers part of the top and part of the side wall of the channel structure layer, and surrounds the channel layer.
18. The semiconductor structure of claim 17, wherein the semiconductor structure further comprises: and the inner side wall is positioned between the adjacent channel layers or between the channel layers and the top semiconductor layer, and covers the side wall of the source-drain doped region.
19. The semiconductor structure of claim 14, wherein a bottom of the source drain doped region is above a top of the sacrificial semiconductor layer.
20. The semiconductor structure of claim 14, wherein the bottom and top semiconductor layers are both Si, and the sacrificial semiconductor layer is SiGe or a III-V semiconductor material.
21. The semiconductor structure of claim 14, wherein the sacrificial semiconductor layer has a thickness of 5nm to 20nm and the top semiconductor layer has a thickness of 10nm to 40 nm.
22. The semiconductor structure of claim 14, wherein a direction perpendicular to an extending direction of the device gate structure and parallel to the substrate surface is a lateral direction, and a lateral dimension of the first recess is 10nm to 40 nm.
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