CN112930041A - Manufacturing method of secondary etching printed circuit board - Google Patents
Manufacturing method of secondary etching printed circuit board Download PDFInfo
- Publication number
- CN112930041A CN112930041A CN202110125063.XA CN202110125063A CN112930041A CN 112930041 A CN112930041 A CN 112930041A CN 202110125063 A CN202110125063 A CN 202110125063A CN 112930041 A CN112930041 A CN 112930041A
- Authority
- CN
- China
- Prior art keywords
- copper
- pattern
- outer layer
- dry film
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0047—Drilling of holes
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
Abstract
The invention discloses a manufacturing method of a secondary etching printed circuit board, which comprises the following steps: cutting, drilling, copper deposition, outer layer pattern plating, etching, secondary outer layer pattern etching, secondary etching and the process after manufacturing the outer layer circuit pattern by using the prior art; then solder mask, characters, surface treatment, molding, testing and FQC are manufactured by the prior art; the copper spreading treatment is carried out at the position of the outer layer pattern circuit, the spread copper sheet is used for dispersing the current of the outer layer isolated pattern position in pattern electroplating, the short circuit problem caused by the fact that the copper plating copper feeding speed is high due to high current density distribution of the outer layer isolated pattern in the pattern electroplating and the film clamping is caused is solved, the open circuit problem caused by tin burning due to high tin plating tin feeding speed and poor tin compactness caused by high current density distribution of the outer layer isolated pattern in the pattern electroplating is solved, the yield of the printed circuit board is improved finally, the waste of the board is reduced, and the production cost is reduced.
Description
Technical Field
The invention relates to the field of printed circuit boards, in particular to a manufacturing method of a secondary etching printed circuit board.
Background
Printed circuit boards are one of the important components in the electronic industry, and almost all electronic devices need to be used, including electronic watches, mobile phones, communication electronic devices and airplane control systems, and the printed circuit boards are indispensable elements of the electronic devices, are transmission carriers of current and signals, play a very important role in the electronic devices, and therefore have higher requirements on the printed circuit boards. Under the traditional printed circuit board manufacturing process, the phenomena of open circuit and short circuit often appear in the manufacturing process of some printed circuit boards with isolated outer lines, the defects can be detected through AOI optical inspection, mainly because the graphs are too isolated, the copper plating and copper plating speed of the isolated outer graphs in the graph electroplating due to high current density distribution is high, the short circuit problem is caused by film clamping, the tin plating and tin plating speed of the isolated outer graphs in the graph electroplating due to high current density distribution is high, the tin compactness is poor, the open circuit problem caused by tin burning is caused, the yield of the printed circuit board is seriously influenced, the defective products are increased, and the manufacturing cost of the printed circuit board is seriously influenced.
Accordingly, the prior art is deficient and needs improvement.
Disclosure of Invention
The invention aims to solve the technical problems in the prior art. Therefore, the invention provides a manufacturing method of a secondary etching printed circuit board, which can solve the problems of open circuit and short circuit caused by tin burning and film clamping in pattern electroplating due to the isolation of the outer layer circuit pattern of the printed circuit board and improve the yield of the printed circuit board.
In order to solve the above problems, the technical scheme provided by the invention is as follows: a manufacturing method of a secondary etching printed circuit board comprises the following steps:
s1, cutting: cutting the copper-clad plate into a production-size core plate suitable for processing;
s2, drilling: drilling a through hole;
s3, copper deposition: the copper deposition is the hole wall copper deposition, and the surface copper is thickened;
s4, outer layer pattern: manufacturing an outer layer dry film pattern through exposure and development;
s5, pattern electroplating: electroplating a layer of copper and a layer of tin in the circuit pattern and the through hole after passing through the outer layer dry film pattern, wherein the position of the dry film can form an anti-plating layer; exposing the circuit pattern of the copper and the position in the hole after developing at a certain current and time;
s6, etching: removing the anti-plating layer on the copper surface, exposing the copper surface below the anti-plating layer, producing a circuit pattern by etching, wherein tin is remained on the circuit pattern, and then removing the tin by chemical tin stripping to form an outer layer circuit pattern;
s7, secondary outer layer pattern: covering the photosensitive dry film for the second time, simultaneously carrying out the second exposure and development, developing the copper sheet laid in the open area in the outer layer pattern, and covering all the dry films at the rest positions;
s8, secondary etching: etching the copper sheet in the open area, etching the exposed copper surface, and removing the photosensitive dry film;
and S9, manufacturing solder mask, characters, surface treatment, molding, testing and FQC by the prior art.
The preferable technical scheme further comprises the setting of the outer layer pattern isolated copper points, wherein the setting of the outer layer pattern isolated copper points refers to the circuit pattern without copper existing within 50mm of one side of the circuit pattern such as copper wires or hole rings in the circuit pattern.
The preferable technical scheme also comprises the arrangement of a vacant area of the outer layer pattern, and the vacant area is designed for copper paving, wherein the distance between the copper paving and the line pattern is 2-4 mm.
According to the preferable technical scheme, the open area of the secondary outer layer pattern is opened to form a window 0.2-0.4mm larger than the whole spread copper sheet, the rest positions are integrally covered, and the whole dry film covering is 2-3.5mm larger than the circuit pattern.
According to the preferable technical scheme, a dry film of a circuit part in the secondary outer layer graph is covered, and the dry film is 0.025-0.05mm larger than a single side of the circuit.
According to the preferable technical scheme, the secondary outer layer pattern further comprises post-lamination air pressure, and the post-lamination air pressure speed is controlled to be 1-2 m/min.
Compared with the prior art, the invention has the beneficial effects that: the method has the advantages that copper paving treatment is carried out on the positions without other circuit patterns within 50mm of one side of the patterns such as the outer-layer pattern circuit or the hole ring, the distance between the paved copper sheet and the circuit patterns is 2-4mm, the paved copper sheet is used for dispersing the current of the positions of the outer-layer isolated patterns in pattern electroplating, the problem of short circuit caused by film clamping due to high copper plating speed caused by high current density distribution of the outer-layer isolated patterns in pattern electroplating is solved, the problem of open circuit caused by tin burning due to high tin plating speed and poor tin compactness caused by high current density distribution of the outer-layer isolated patterns in pattern electroplating is solved, the yield of the printed circuit board is improved finally, the waste of the board is reduced, and the production cost is reduced.
Drawings
For a clearer explanation of the embodiments or technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained from the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for manufacturing a printed circuit board by secondary etching according to an embodiment of the invention.
Detailed Description
In order to facilitate an understanding of the invention, the invention is described in more detail below with reference to the accompanying drawings and specific examples. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The use of the terms "fixed," "integrally formed," "left," "right," and the like in this specification is for illustrative purposes only, and elements having similar structures are designated by the same reference numerals in the figures.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Referring to fig. 1, the invention discloses a method for manufacturing a secondary etching printed circuit board, comprising the following steps:
s1, cutting: cutting the copper-clad plate into a production-size core plate suitable for processing;
s2, drilling: drilling a through hole; and drilling a through hole between layers and a compression joint device fixing hole by using a numerical control drilling machine.
S3, copper deposition: the copper deposition is the hole wall copper deposition, and the surface copper is thickened; and depositing a layer of copper on the drilled through holes between the layers in a chemical deposition mode to achieve the function of circuit conduction between the layers, and increasing the thickness of surface copper to meet the requirement of current passing.
S4, outer layer pattern: manufacturing an outer layer dry film pattern through exposure and development; the method specifically comprises the steps of grinding and cleaning a plate with deposited copper on the plate, cleaning the copper surface of the plate and garbage, roughening the outer copper surface to achieve the effect of increasing the binding force with a photosensitive dry film, pressing a layer of photosensitive dry film on the treated plate at a certain pressure, speed and temperature, exposing the photosensitive dry film through a negative film, carrying out polymerization reaction on the photosensitive dry film in a light transmission area on the negative film, keeping the photosensitive dry film in a developing step, and removing the photosensitive dry film in a light blocking area on the negative film to expose the copper below to form an outer dry film pattern.
S5, pattern electroplating: electroplating a layer of copper and a layer of tin in the circuit pattern and the through hole after passing through the outer layer dry film pattern, wherein the position of the dry film can form an anti-plating layer; exposing the circuit pattern of the copper and the position in the hole after developing at a certain current and time; specifically, a layer of copper is electroplated on a circuit pattern and a hole position exposed out of copper after development at a certain current for a certain time, and then a layer of tin is electroplated, so that an anti-plating layer is formed on the position of a dry film.
S6, etching: removing the anti-plating layer on the copper surface, exposing the copper surface below the anti-plating layer, producing a circuit pattern by etching, wherein tin is remained on the circuit pattern, and then removing the tin by chemical tin stripping to form an outer layer circuit pattern; the tin surface has corrosion resistance, copper under tin cannot be etched, and tin is removed through chemical tin stripping to form an outer layer circuit pattern.
S7, secondary outer layer pattern: cleaning the etched plate, oxidizing the copper surface of the plate and cleaning garbage, pressing a layer of photosensitive dry film at a certain pressure, speed and temperature, performing air compression once after film pressing to form a secondary covering photosensitive dry film, simultaneously performing secondary exposure and development, developing the copper sheet laid in the open area in the outer layer pattern, and covering all the dry films at the rest positions;
s8, secondary etching: etching the copper sheet in the open area, etching away the exposed copper surface, forming a corrosion-resistant protective layer at the position covered by the dry film, and soaking the acid-etched plate with sodium hydroxide with certain concentration to remove the photosensitive dry film to form the final required outer layer circuit pattern.
And S9, and manufacturing an outer layer circuit pattern by using the prior art. Then the solder mask, characters, surface treatment, molding, testing and FQC are manufactured by the prior art.
The preferable technical scheme further comprises the setting of the outer layer pattern isolated copper points, wherein the setting of the outer layer pattern isolated copper points refers to the circuit pattern without copper existing within 50mm of one side of the circuit pattern such as copper wires or hole rings in the circuit pattern.
The preferable technical scheme further comprises the step of arranging a vacant area of the outer layer pattern, wherein copper paving is conducted in the vacant area, and the distance between the copper paving and the line pattern is 2-4mm, preferably 3 mm.
According to the preferable technical scheme, the open area of the secondary outer layer pattern is opened to form a window 0.2-0.4mm larger than the whole spread copper sheet, the rest positions are integrally covered, and the whole coverage of a dry film is 2-3.5mm larger than that of the circuit pattern, preferably 2.7 mm.
According to the preferable technical scheme, a dry film of a circuit part in the secondary outer layer graph is covered, and the dry film is 0.025-0.05mm larger than a single side of the circuit.
According to the preferable technical scheme, the secondary outer layer pattern further comprises post-lamination air pressure, and the post-lamination air pressure speed is controlled to be 1-2m/min, preferably 1.5 m/min.
The technical features mentioned above are combined with each other to form various embodiments which are not listed above, and all of them are regarded as the scope of the present invention described in the specification; also, modifications and variations may be suggested to those skilled in the art in light of the above teachings, and it is intended to cover all such modifications and variations as fall within the true spirit and scope of the invention as defined by the appended claims.
Claims (6)
1. The manufacturing method of the secondary etching printed circuit board is characterized by comprising the following steps:
s1, cutting: cutting the copper-clad plate into a production-size core plate suitable for processing;
s2, drilling: drilling a through hole;
s3, copper deposition: the copper deposition is the hole wall copper deposition, and the surface copper is thickened;
s4, outer layer pattern: manufacturing an outer layer dry film pattern through exposure and development;
s5, pattern electroplating: electroplating a layer of copper and a layer of tin in the circuit pattern and the through hole after passing through the outer layer dry film pattern, wherein the position of the dry film can form an anti-plating layer; exposing the developed copper circuit pattern and the position in the hole with a certain current and time
S6, etching: removing the anti-plating layer on the copper surface, exposing the copper surface below the anti-plating layer, producing a circuit pattern by etching, wherein tin is remained on the circuit pattern, and then removing the tin by chemical tin stripping to form an outer layer circuit pattern;
s7, secondary outer layer pattern: covering the photosensitive dry film for the second time, simultaneously carrying out the second exposure and development, developing the copper sheet laid in the open area in the outer layer pattern, and covering all the dry films at the rest positions;
s8, secondary etching: etching the copper sheet in the open area, etching the exposed copper surface, and removing the photosensitive dry film;
and S9, manufacturing solder mask, characters, surface treatment, molding, testing and FQC by the prior art.
2. The method of claim 1, wherein the method further comprises: the method further comprises the step of setting the isolated copper points of the outer layer graph, wherein the set of the isolated copper points of the outer layer graph refers to the circuit graph without copper existing within 50mm of one side of the circuit graph such as a copper wire or a hole ring in the circuit graph.
3. The method of claim 1, wherein the method further comprises: and the method also comprises the step of arranging an open area of the outer layer pattern, wherein copper paving design is carried out in the open area, and the copper paving distance is 2-4mm from the line pattern.
4. A method of fabricating a double-etched printed circuit board according to any one of claims 1 to 3, characterized in that: the open area of the secondary outer layer pattern is opened with a window 0.2-0.4mm larger than the whole copper sheet, the rest positions are covered with the whole dry film, and the whole dry film is covered with a circuit pattern 2-3.5mm larger.
5. A method of fabricating a double-etched printed circuit board according to any one of claims 1 to 3, characterized in that: and covering a dry film of the circuit part in the secondary outer layer graph, wherein the dry film is 0.025-0.05mm larger than the single side of the circuit.
6. The method of manufacturing a double-etched printed circuit board as claimed in claim 5, wherein: and the secondary outer layer pattern also comprises post-lamination air pressure, and the post-lamination air pressure speed is controlled to be 1-2 m/min.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110125063.XA CN112930041A (en) | 2021-01-29 | 2021-01-29 | Manufacturing method of secondary etching printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110125063.XA CN112930041A (en) | 2021-01-29 | 2021-01-29 | Manufacturing method of secondary etching printed circuit board |
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| Publication Number | Publication Date |
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| CN112930041A true CN112930041A (en) | 2021-06-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202110125063.XA Pending CN112930041A (en) | 2021-01-29 | 2021-01-29 | Manufacturing method of secondary etching printed circuit board |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114980562A (en) * | 2022-06-28 | 2022-08-30 | 珠海中京电子电路有限公司 | Manufacturing method of pure tin plated plate, PCB and terminal equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04276081A (en) * | 1991-03-01 | 1992-10-01 | C Uyemura & Co Ltd | Method for electroless plating of tin, lead, or alloy |
| US20110016709A1 (en) * | 2009-07-24 | 2011-01-27 | Ibiden Co., Ltd. | Manufacturing method for printed wiring board |
| CN104780710A (en) * | 2014-01-15 | 2015-07-15 | 深圳崇达多层线路板有限公司 | PCB (Printed circuit board) and manufacturing method thereof |
| CN108419376A (en) * | 2018-05-14 | 2018-08-17 | 星河电路（福建）有限公司 | A kind of production method of the high thick copper pcb board of selective local plating |
| CN111867266A (en) * | 2020-07-14 | 2020-10-30 | 江门崇达电路技术有限公司 | Circuit design method for preventing short circuit of isolated circuit of PCB |
-
2021
- 2021-01-29 CN CN202110125063.XA patent/CN112930041A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04276081A (en) * | 1991-03-01 | 1992-10-01 | C Uyemura & Co Ltd | Method for electroless plating of tin, lead, or alloy |
| US20110016709A1 (en) * | 2009-07-24 | 2011-01-27 | Ibiden Co., Ltd. | Manufacturing method for printed wiring board |
| CN104780710A (en) * | 2014-01-15 | 2015-07-15 | 深圳崇达多层线路板有限公司 | PCB (Printed circuit board) and manufacturing method thereof |
| CN108419376A (en) * | 2018-05-14 | 2018-08-17 | 星河电路（福建）有限公司 | A kind of production method of the high thick copper pcb board of selective local plating |
| CN111867266A (en) * | 2020-07-14 | 2020-10-30 | 江门崇达电路技术有限公司 | Circuit design method for preventing short circuit of isolated circuit of PCB |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114980562A (en) * | 2022-06-28 | 2022-08-30 | 珠海中京电子电路有限公司 | Manufacturing method of pure tin plated plate, PCB and terminal equipment |
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| PB01 | Publication | ||
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| CB02 | Change of applicant information |
Address after: 518000 101-401, building A-1, Fufa Industrial Park, No.3, Fuyuan 1st Road, Heping community, Fuhai street, Bao'an District, Shenzhen City, Guangdong Province Applicant after: Shenzhen Qiangda circuit Co.,Ltd. Address before: 518000 101-401, building A-1, Fufa Industrial Park, No.3, Fuyuan 1st Road, Heping community, Fuhai street, Bao'an District, Shenzhen City, Guangdong Province Applicant before: Q&D CIRCUITS Co.,Ltd. |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210608 |
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| RJ01 | Rejection of invention patent application after publication |