CN112928207A - Method for improving voltage resistance of capacitor - Google Patents
Method for improving voltage resistance of capacitor Download PDFInfo
- Publication number
- CN112928207A CN112928207A CN201911240661.0A CN201911240661A CN112928207A CN 112928207 A CN112928207 A CN 112928207A CN 201911240661 A CN201911240661 A CN 201911240661A CN 112928207 A CN112928207 A CN 112928207A
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- CN
- China
- Prior art keywords
- capacitor
- etching
- dielectric
- layer
- voltage resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 27
- 125000006850 spacer group Chemical group 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 230000003287 optical effect Effects 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000010953 base metal Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000002715 modification method Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
Abstract
The invention provides a method for improving the voltage resistance of a capacitor, which comprises the following four steps: the method comprises the following steps: correcting the corner of the square upper polar plate of the capacitor from a right angle to an arc angle; step two: etching the upper polar plate by two steps of metal etching and dielectric etching; step three: depositing an oxide spacer layer on the upper plate; and step four, performing integral etching on the dielectric layer. By the method, the voltage resistance of the metal dielectric metal capacitor is effectively improved.
Description
Technical Field
The invention relates to the field of capacitors, in particular to a method for improving the voltage resistance of a capacitor.
Background
In the production process of the metal dielectric metal capacitor in the prior art, an upper polar plate of the capacitor is usually square, more charges are easily accumulated on a right angle of the upper polar plate, and the corner of the upper polar plate generates a melting point due to point discharge; in the prior art, metal etching is usually performed only in one step, which easily causes the remaining thickness of the dielectric layer to be difficult to control, and the remaining thickness of the dielectric layer is strongly related to the voltage resistance of the capacitor, and affects the subsequent process of the capacitor.
For the above reasons, it is necessary to provide a method capable of improving the voltage resistance of the capacitor.
Disclosure of Invention
The invention discloses a method for improving the voltage resistance of a capacitor, which comprises the following steps:
the method comprises the following steps: correcting the corner of the square upper polar plate of the capacitor from a right angle to an arc angle;
step two: etching the upper plate by two steps of metal etching and dielectric etching;
step three: depositing an oxide spacer layer on the upper plate;
and step four, performing integral etching on the dielectric layer.
According to an embodiment of the present invention, the capacitor is a dielectric metal capacitor.
According to an embodiment of the method for improving the voltage resistance of the capacitor of the present invention, the correction in the step one is performed by an optical correction method.
According to an embodiment of the method for improving the voltage resistance of the capacitor of the present invention, the capacitor is formed by the base metal layer, the dielectric layer and the top metal layer.
In an embodiment of the method for improving the voltage endurance of the capacitor according to the present invention, the oxide deposited on the oxide spacer in step three is silicon dioxide.
According to an embodiment of the method for improving the voltage resistance of the capacitor of the present invention, the bulk etching in step three etches the oxide spacer as a ramp.
According to an embodiment of the method for improving the voltage resistance of the capacitor, the slope extends from the top metal layer to the bottom metal layer.
By the method provided by the invention, the following beneficial effects can be obtained:
(1) after the corners of the upper polar plate are changed into arc corners from right angles, point discharge of the corners of the upper polar plate of the capacitor is reduced, and therefore the upper polar plate is guaranteed not to have a melting point;
(2) the one-step metal etching is changed into two steps of metal etching and dielectric etching, so that the reserved thickness of the dielectric can be accurately controlled, and the voltage resistance of the capacitor is improved;
(3) the oxide spacing layer is added after the two-step etching, so that the oxide spacing layer can be integrally etched into a slope shape, and the voltage resistance of the capacitor is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for improving the voltage resistance of a capacitor according to the present invention.
Detailed Description
In view of the above, the present invention provides an embodiment of a method for improving the voltage resistance of a capacitor. Fig. 1 is a schematic flow chart of an embodiment of a method for improving the voltage resistance of a capacitor according to the present invention.
In an embodiment of the method for improving the voltage resistance of the capacitor of the present invention, the method at least includes the following steps:
step S1, correcting the corner of the square upper polar plate of the capacitor from a right angle to an arc angle;
step S2, etching the upper plate by two steps of metal etching and dielectric etching;
step S3, depositing an oxide spacer on the upper plate;
in step S4, the dielectric layer is entirely etched.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The production process of the dielectric metal capacitor is as follows:
and modifying the right angle of the square upper polar plate into a circular arc angle by an optical modification method, then carrying out metal etching on the upper polar plate, and etching the dielectric layer by adopting dielectric etching after the metal etching is finished. By using the two-step etching method, the dielectric layer can be etched more precisely than by using the one-step etching method of the prior art.
After the two-step etching is completed, the top metal layer and the dielectric layer of the capacitor are subjected to oxide deposition to form an oxide spacing layer on the top metal layer and the dielectric layer, and then the oxide spacing layer is subjected to integral etching. A bulk etch is performed on the oxide spacer layer by which the oxide layer is etched to a slope, which in this embodiment extends from the top metal layer towards the dielectric layer, wherein the sloped bottom region on the dielectric layer is larger than the sloped top region on the top metal layer. The slope wraps the side surfaces of the upper plate and the dielectric layer, so that the produced capacitor has good voltage resistance.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. Although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of an embodiment of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (7)
1. A method of improving capacitance tolerance, comprising the steps of:
the method comprises the following steps: correcting the corner of the square upper polar plate of the capacitor from a right angle to an arc angle;
step two: etching the upper polar plate by two steps of metal etching and dielectric etching;
step three: depositing an oxide spacer layer on the upper plate;
and step four, performing integral etching on the dielectric layer.
2. The method of claim 1,
the capacitor is a dielectric metal capacitor.
3. The method of claim 1,
the correction in the first step is implemented by an optical correction method.
4. The method of claim 1,
the capacitor is composed of a substrate metal layer, a dielectric layer and a top metal layer.
5. The method of claim 1,
the oxide deposited for the oxide spacer layer in step three is silicon dioxide.
6. The method of claim 1,
the bulk etch in step three etches the oxide spacer layer as a ramp.
7. The method of claim 6,
the ramp extends from the top metal layer to the bottom metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911240661.0A CN112928207A (en) | 2019-12-06 | 2019-12-06 | Method for improving voltage resistance of capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911240661.0A CN112928207A (en) | 2019-12-06 | 2019-12-06 | Method for improving voltage resistance of capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112928207A true CN112928207A (en) | 2021-06-08 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911240661.0A Pending CN112928207A (en) | 2019-12-06 | 2019-12-06 | Method for improving voltage resistance of capacitor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112928207A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW465014B (en) * | 1999-02-01 | 2001-11-21 | Taiwan Semiconductor Mfg | Manufacturing method for capacitor of metal layer/ dielectric layer/metal layer and its structure after CMOS manufacturing process |
| US6430028B1 (en) * | 2000-11-22 | 2002-08-06 | Newport Fab, Llc | Method for fabrication of an MIM capacitor and related structure |
| US20090021888A1 (en) * | 2007-07-16 | 2009-01-22 | Dong Jin Jung | Capacitor, method of manufacturing a capacitor and method of manufacturing a semiconductor device |
| CN103378066A (en) * | 2012-04-24 | 2013-10-30 | Nxp股份有限公司 | Interface for communication between voltage domains |
| CN103779181A (en) * | 2012-10-18 | 2014-05-07 | 中芯国际集成电路制造(上海)有限公司 | MIM capacitor and manufacturing method thereof |
-
2019
- 2019-12-06 CN CN201911240661.0A patent/CN112928207A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW465014B (en) * | 1999-02-01 | 2001-11-21 | Taiwan Semiconductor Mfg | Manufacturing method for capacitor of metal layer/ dielectric layer/metal layer and its structure after CMOS manufacturing process |
| US6430028B1 (en) * | 2000-11-22 | 2002-08-06 | Newport Fab, Llc | Method for fabrication of an MIM capacitor and related structure |
| US20090021888A1 (en) * | 2007-07-16 | 2009-01-22 | Dong Jin Jung | Capacitor, method of manufacturing a capacitor and method of manufacturing a semiconductor device |
| CN103378066A (en) * | 2012-04-24 | 2013-10-30 | Nxp股份有限公司 | Interface for communication between voltage domains |
| CN103779181A (en) * | 2012-10-18 | 2014-05-07 | 中芯国际集成电路制造(上海)有限公司 | MIM capacitor and manufacturing method thereof |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210608 |