CN103515350B - Vertical metal/insulating barrier/metal M IM electric capacity and manufacture method thereof - Google Patents
Vertical metal/insulating barrier/metal M IM electric capacity and manufacture method thereof Download PDFInfo
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- CN103515350B CN103515350B CN201210202078.2A CN201210202078A CN103515350B CN 103515350 B CN103515350 B CN 103515350B CN 201210202078 A CN201210202078 A CN 201210202078A CN 103515350 B CN103515350 B CN 103515350B
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Abstract
The invention discloses a kind of vertical metal/insulating barrier/metal M IM electric capacity, comprising: two grooves be parallel to each other formed in insulating barrier, this groove stops on a certain lower metal; Insulating barrier between described two grooves forms the insulating barrier of described electric capacity; At the metal level that the insulating barrier both sides of this electric capacity are formed respectively, this metal level forms two metal guide electrodes of described electric capacity, forms complete vertical metal/insulating barrier/metal M IM capacitance structure; The two end electrodes of described electric capacity is drawn at the described a certain lower metal being positioned at described metal level lower end.The invention also discloses a kind of manufacture method of described vertical metal/insulating barrier/metal M IM electric capacity.When the electric capacity that making capacitance is larger, adopt the present invention can avoid strengthening chip area, and the precision of energy holding capacitor.
Description
Technical field
The present invention relates to semiconductor integrated circuit field, particularly relate to a kind of vertical MIM (metal/insulator/metal, insulator/metal layer/metal) electric capacity.The invention still further relates to a kind of manufacture method of described electric capacity.
Background technology
Different electric capacity is usually used in semiconductor integrated circuit.Wherein MIM capacitor, because its good frequency and temperature characterisitic are often selected to radio frequency, in the integrated circuits such as in-line memory.
As shown in Figure 1, wherein, the part gone out by dotted line collimation mark is MIM capacitor body to traditional MIM capacitor cross sectional representation; Comprise X-1 layer metal (the lower step as electric capacity) 102, top crown metal level (top crown as electric capacity) 113, and be positioned at the insulating barrier 104 in the middle of it.The upper bottom crown of this electric capacity, for being horizontally disposed with, because the size of electric capacity is directly proportional to the area of upper bottom crown, when the capacity ratio required is larger time, needing very large-area upper bottom crown, will add the area of large chip like this.And during the making of this electric capacity, one deck mask plate must be set, add cost.In Fig. 1 103 is X layer metal level, and 109 is metal in X-1 layer contact hole, and 101 is the first insulating barrier, and 111 is the second insulating barrier.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of vertical MIM capacitor, when the electric capacity that making capacitance is larger, also can avoid strengthening chip area, and the precision of energy holding capacitor; For this reason, the present invention also will relate to a kind of manufacture method of described MIM capacitor.
For solving the problems of the technologies described above, vertical MIM capacitor of the present invention, comprising: two grooves be parallel to each other formed in insulating barrier, and this groove stops on a certain lower metal; Insulating barrier between described two grooves forms the insulating barrier of described electric capacity; At the metal level that the insulating barrier both sides of this electric capacity are formed respectively, this metal level forms two metal guide electrodes of described electric capacity, forms complete vertical mim capacitor structure; The two end electrodes of described electric capacity is drawn at the described a certain lower metal being positioned at described metal level lower end.
Described insulating barrier is IMD (intermetaldielectric, the insulating barrier between metal level).
The manufacture method of described vertical MIM capacitor, comprises the steps:
Step 1, forms a certain lower metal line in the first insulating barrier upper end, and wherein, the described a certain lower metal of part is used in electrode lower end, the both sides lead-in wire of described vertical metal/insulating barrier/metal M IM electric capacity;
Step 2, forms the second insulating barrier in described first insulating barrier upper end and a certain lower metal upper end, deposit one deck hard mask layer on this second insulating barrier;
Step 3, successively forms X-1 layer contact hole and groove respectively in the second insulating barrier;
Step 4, adopts lithographic method to remove described hard mask layer;
Step 5, carries out the deposit of metal in X-1 layer contact hole;
Step 6, carries out returning of metal in isotropic described X-1 layer contact hole and carves;
Step 7, the upper surface of metal in described second insulating barrier and X-1 layer contact hole, and the surface deposition X layer metal in described groove;
Step 8, at described X layer metal upper end coating photoresist, carries out the photoetching of X layer metal, makes described vertical MIM capacitor region be exposed simultaneously;
Step 9, carries out the dry etching of anisotropic X layer metal, then adopts dry method and/or wet etching to remove photoresist, forms the structure of described vertical MIM capacitor;
Step 10, carries out the deposit of follow-up 3rd insulating barrier, and the 3rd insulating barrier covers described second insulating barrier and X layer metal, and fills described groove.
Present invention utilizes the material of the intrinsic vertical direction of chip, even if when the electric capacity that making Capacity Ratio is larger, also can avoid adding large chip (in the horizontal direction) area.Particularly the present invention has only used the two end electrodes that one deck lower metal is used for drawing described electric capacity, and the capacitance of the described vertical capacitor overwhelming majority is determined by the insulating barrier part be positioned in the middle of the metal level of electric capacity both sides.Although the electric capacity between described a certain lower metal also can have impact to total capacitance value, because its area proportion in whole vertical capacitor is less, impact is also little.Especially, can use the metal of local interconnect in some technique, this layer of metal is general thinner, such as
left and right.If do described a certain lower metal with the metal of thinner local interconnect layer, so, relative to the height of whole vertical MIM capacitor, such as, between 1 micron to 10 microns, described in it, the height of a certain lower metal almost can be ignored.At this moment, the electric capacity described in it between a certain lower metal is also just very little on the impact of whole vertical MIM capacitor, such as < 10%, even < 1%.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is the cross-sectional structure schematic diagram of existing horizontal MIM capacitor;
Fig. 2 is the cross-sectional structure schematic diagram of vertical MIM capacitor;
Fig. 3 is 3 dimension structural representations of vertical MIM capacitor;
Fig. 4 is the cross sectional representation after a certain lower metal of embodiment one is formed;
Fig. 5 is the cross sectional representation after embodiment one deposit hard mask layer;
Fig. 6 is the cross sectional representation after embodiment one X-1 layer contact hole is formed;
Fig. 7 is the schematic diagram of embodiment one photoetching, definition recess region;
Fig. 8 is the schematic diagram that embodiment one forms groove;
Fig. 9 is the cross sectional representation after embodiment one removes hard mask layer;
Figure 10 is the schematic diagram that embodiment one carries out Metal deposition in X-1 layer contact hole;
Figure 11 is that embodiment one is carried out metal in X-1 layer contact hole and returned the schematic diagram at quarter;
Figure 12 is the schematic diagram that embodiment one carries out X layer Metal deposition;
Figure 13 is the schematic diagram that embodiment one carries out X layer metal lithographic;
Figure 14 is the schematic diagram that embodiment one carries out X layer metal etch;
Figure 15 is the schematic diagram that embodiment one carries out follow-up 3rd insulating barrier deposit;
Figure 16 is the schematic diagram that embodiment two carries out X-1 layer contact hole and groove photoetching.
Embodiment
Fig. 2 is the cross-sectional structure schematic diagram of described vertical MIM capacitor one embodiment, this electric capacity comprises three grooves 110, at sidewall deposit one deck X layer metal level 103 of each groove 110, a certain lower metal 105 is formed in the lower end of X layer metal level 103, after said structure completes, with top deposit the 3rd insulating barrier 112 of the second insulating barrier 111 in groove 110, and fill up groove 110.Vertical MIM capacitor described in such Fig. 2 comprises two groups of electric capacity, and what wherein gone out by thick dashed line collimation mark is first group of MIM capacitor, and what gone out by dot-dash dotted line collimation mark is second group of MIM capacitor.First group of MIM capacitor is made up of the second insulating barrier (i.e. the insulating barrier of described electric capacity) 111 and the X layer metal level 103 being positioned at this second insulating barrier 111 two side ends; Second group of MIM capacitor is made up of with the 3rd insulating barrier 112 being filled in groove the X layer metal level 103 being positioned at same groove 110 two side.Fig. 3 is 3 dimension structural representations of described vertical MIM capacitor.
Groove 110 in Fig. 2 and Fig. 3 is seen from top to bottom, can be three rectangular grooves be parallel to each other, and also can be three semicircular grooves be parallel to each other.
In Fig. 2,101 is the first insulating barrier, and 109 is metal in X-1 layer contact hole, and 102 is X-1 layer metal level, 107 be connect upper and lower two metal layers contact hole in metal.
Embodiment one
The manufacture method of described vertical MIM capacitor comprises the steps:
Step 1, see Fig. 4, forms a certain lower metal 105 in the first insulating barrier 101 upper end.Wherein, the described a certain lower metal 105 of part is used in electrode lower end, the both sides lead-in wire of described vertical MIM capacitor.
Step 2, see Fig. 5, forms the second insulating barrier 111 in described first insulating barrier 101 upper end and a certain lower metal 105 upper end, deposit one deck hard mask layer 115 on the second insulating barrier 111.The thickness of described hard mask layer 115 is 1000 dust ~ 10000 dusts.
Step 3, see Fig. 6, is positioned at above X-1 layer metal level 102 and forms X-1 layer contact hole 106 in the second insulating barrier 111.
Step 4, see Fig. 7, applies photoresist 108, utilizes lithographic definition to go out the position of groove above described second insulating barrier 111 He in X-1 layer contact hole 106, makes needing the position of the groove forming vertical MIM capacitor to be exposed.The width of this groove is greater than the width of this layer X-1 layer contact hole 106.
Step 5, see Fig. 8, is formed groove 110 by anisotropic being dry-etched in described second insulating barrier 111, is then removed by residual photoresist 108 by dry method or wet etching.Must to be insulating barrier have high selectivity for the etch rate of hard mask layer and metal level to described dry etching, such as, be greater than 10:1.Such dry etching just can stop at a certain lower metal 105, determines the degree of depth of groove 110 thus.
Step 6, see Fig. 9, adopts lithographic method to remove described hard mask layer 115.The lithographic method of described lithographic method should to be described hard mask layer 115 for the etch rate of the second insulating barrier 111 and X-1 layer metal level 102 all have high selectivity.
Step 7, see Figure 10, carries out the deposit of metal 109 in X-1 layer contact hole in X-1 layer contact hole 106.Width due to the groove 110 of vertical MIM capacitor is greater than the width of this X-1 layer contact hole 106, will fill up X-1 layer contact hole 106, but can not fill up groove 110 in deposit X-1 layer contact hole after metal 109.
Step 8, see Figure 11, carries out returning of metal 109 in isotropic X-1 layer contact hole and carves.Because metal fills up X-1 layer contact hole 106, but do not fill up groove 110, in X-1 layer contact hole, metal 109 meetings have residual in X-1 layer contact hole 106.
Step 9, see Figure 12, carries out the deposit of X layer metal.The upper surface of metal 109 in described second insulating barrier 111 and X-1 layer contact hole, and surface (i.e. sidewall and bottom) the deposit X layer metal 103 in described groove 110.
Step 10, see Figure 13, at described X layer metal 103 upper end coating photoresist 108, carries out the photoetching of X layer metal 103, makes vertical MIM capacitor region be exposed simultaneously.
Step 11, see Figure 14, carries out the dry etching of anisotropic X layer metal 103, then adopts dry method and/or wet etching to remove photoresist 108.So just form the structure of described vertical MIM capacitor.After carrying out the dry etching of described anisotropic X layer metal 103, outside the insulating barrier both sides of vertical MIM capacitor, form side wall by X layer metal 103; This dry etching adopts the etch rate of X layer metal 103 to the second insulating barrier 111 to have the lithographic method of high selectivity.
Step 12, see Figure 15, carry out the deposit of follow-up 3rd insulating barrier 112, the 3rd insulating barrier 112 covers the second insulating barrier 111 and X layer metal 103, and filling groove 110.
Embodiment two
The difference of the present embodiment and embodiment one is, shown in Figure 16, utilizes the photoetching of normal X-1 layer contact hole 106, and make is needing the position of the groove forming vertical MIM capacitor to be exposed simultaneously.The width of this groove 110 is greater than the width of the contact hole of this layer, and then form groove 110 by anisotropic dry etching, remainder is identical with embodiment one.
Embodiment one needs to increase one deck mask plate, and embodiment two does not need to increase any mask plate.
Above by embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (13)
1. vertical metal/insulating barrier/metal M IM electric capacity, is characterized in that, comprising: two grooves be parallel to each other formed in insulating barrier, and this groove stops on a certain lower metal; Insulating barrier between described two grooves forms the insulating barrier of described electric capacity; At the metal level that the insulating barrier both sides of this electric capacity are formed respectively, this metal level forms two metal guide electrodes of described electric capacity, forms complete vertical metal/insulating barrier/metal M IM capacitance structure; The two end electrodes of described electric capacity is drawn at the described a certain lower metal being positioned at described metal level lower end.
2. electric capacity as claimed in claim 1, is characterized in that: described insulating barrier is the insulating barrier IMD between metal level.
3. electric capacity as claimed in claim 1, is characterized in that: described groove is the rectangular groove be parallel to each other, or the semicircular groove be parallel to each other.
4. electric capacity as claimed in claim 1, is characterized in that: also comprise deposit and fill up the 3rd insulating barrier of the groove of described vertical MIM capacitor, and forms another by the metal level that the two side of same groove is formed with the 3rd insulating barrier and organize vertical MIM capacitor.
5. as described in as arbitrary in claim 1-4, a manufacture method for electric capacity, is characterized in that, comprise the steps:
Step 1, forms a certain lower metal in the first insulating barrier upper end, and wherein, the described a certain lower metal of part is used in electrode lower end, the both sides lead-in wire of described vertical metal/insulating barrier/metal M IM electric capacity;
Step 2, forms the second insulating barrier in described first insulating barrier upper end and a certain lower metal upper end, deposit one deck hard mask layer on this second insulating barrier;
Step 3, successively forms X-1 layer contact hole and groove respectively in the second insulating barrier;
Step 4, adopts lithographic method to remove described hard mask layer;
Step 5, carries out the deposit of metal in X-1 layer contact metal;
Step 6, carries out returning of metal in isotropic described X-1 layer contact hole and carves;
Step 7, the upper surface of metal in described second insulating barrier and X-1 layer contact hole, and the surface deposition X layer metal in described groove;
Step 8, at described X layer metal upper end coating photoresist, carries out the photoetching of X layer metal, makes described vertical metal/insulating barrier/metal M IM capacitor regions be exposed simultaneously;
Step 9, carries out the dry etching of anisotropic X layer metal, then adopts dry method and/or wet etching to remove photoresist, forms the structure of described vertical metal/insulating barrier/metal M IM electric capacity;
Step 10, carries out the deposit of the 3rd insulating barrier, and the 3rd insulating barrier covers described second insulating barrier and X layer metal, and fills described groove.
6. method as claimed in claim 5, is characterized in that: described hard mask layer adopts the material different from insulating barrier.
7. method as claimed in claim 5, is characterized in that: the thickness of described hard mask layer is 1000 dust ~ 10000 dusts.
8. method as claimed in claim 5, is characterized in that: the width of described groove is greater than the width of this layer of contact hole.
9. method as claimed in claim 5, is characterized in that: adopt anisotropic dry etching when implementation step 3 forms groove, and described dry etching is described insulating barrier all has high selectivity for the etch rate of hard mask layer and metal level.
10. method as claimed in claim 5, is characterized in that: during implementation step 4, adopts described hard mask layer all to have the lithographic method of high selectivity for the etch rate of insulating barrier and X-1 layer metal level.
11. methods as claimed in claim 5, is characterized in that: during implementation step 5, fill up X-1 layer contact hole, and do not fill up described groove in described X-1 layer contact hole after Metal deposition.
12. methods as claimed in claim 5, is characterized in that: in X-1 layer contact hole described in the Hui Kehou that implementation step 6 carries out metal in isotropic contact hole, metal only has residual in described X-1 layer contact hole.
13. methods as claimed in claim 5, is characterized in that: implementation step 9 forms side wall by X layer metal after carrying out the dry etching of anisotropic described X layer metal outside the insulating barrier both sides of vertical metal/insulating barrier/metal M IM electric capacity; This dry etching adopts the etch rate of X layer metal pair insulating barrier to have the lithographic method of high selectivity.
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| CN201210202078.2A CN103515350B (en) | 2012-06-18 | 2012-06-18 | Vertical metal/insulating barrier/metal M IM electric capacity and manufacture method thereof |
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| CN103515350B true CN103515350B (en) | 2016-02-10 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6593185B1 (en) * | 2002-05-17 | 2003-07-15 | United Microelectronics Corp. | Method of forming embedded capacitor structure applied to logic integrated circuit |
| CN1751367A (en) * | 2003-02-20 | 2006-03-22 | 因芬尼昂技术股份公司 | Capacitor and method of manufacturing a capacitor |
| JP2010045378A (en) * | 2000-12-21 | 2010-02-25 | Infineon Technologies North America Corp | Self-aligned double-sided vertical mim-capacitor |
| CN101673619A (en) * | 2009-08-21 | 2010-03-17 | 上海宏力半导体制造有限公司 | Columnar capacitor, stacking-type coaxial columnar capacitor and preparation method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100536109C (en) * | 2003-12-30 | 2009-09-02 | 中芯国际集成电路制造(上海)有限公司 | Method and structure for manufacturing high-capacitance capacitor by using copper |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010045378A (en) * | 2000-12-21 | 2010-02-25 | Infineon Technologies North America Corp | Self-aligned double-sided vertical mim-capacitor |
| US6593185B1 (en) * | 2002-05-17 | 2003-07-15 | United Microelectronics Corp. | Method of forming embedded capacitor structure applied to logic integrated circuit |
| CN1751367A (en) * | 2003-02-20 | 2006-03-22 | 因芬尼昂技术股份公司 | Capacitor and method of manufacturing a capacitor |
| CN101673619A (en) * | 2009-08-21 | 2010-03-17 | 上海宏力半导体制造有限公司 | Columnar capacitor, stacking-type coaxial columnar capacitor and preparation method thereof |
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