CN101494195B - Preparation method of capacitance - Google Patents
Preparation method of capacitance Download PDFInfo
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- CN101494195B CN101494195B CN2008100330453A CN200810033045A CN101494195B CN 101494195 B CN101494195 B CN 101494195B CN 2008100330453 A CN2008100330453 A CN 2008100330453A CN 200810033045 A CN200810033045 A CN 200810033045A CN 101494195 B CN101494195 B CN 101494195B
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Abstract
The invention provides a method for producing a capacitor. The method comprises the steps: 1: a substrate is provided and an electrode layer and an initial dielectric layer are deposited on the substrate in sequence; 2: after an ion implantation mask layer is formed on the initial dielectric layer, the ion implantation is used to form another dielectric layer; 3: after the ion implantation mask layer is removed, another electrode layer and a corrosion-resisting layer are deposited in sequence and an etching mask layer is formed on the corrosion-resisting layer; 4: the corrosion-resisting layer beyond the coverage of the etching mask layer and part of the other electrode are etched; and 5: after the etching mask layer is removed, a conductive hole, which penetrates the corrosion-resisting layer and the initial dielectric layer, is formed. The adoption of the ion implementation in the initial dielectric layer can realize the production of a capacitor with larger capacity and solve the problems such as massive leakage current, over occupancy of the area of a chip and high production cost when the larger-capacity capacitor is produced by the traditional method.
Description
Technical field
The present invention designs the making field of integrated component in the IC device, especially designs the manufacture method of electric capacity in the IC device.
Background technology
Electric capacity is the commonly used and important element of analog IC device and memory device.The utilization of electric capacity is also more common in requiring high-performance and high frequency at a high speed and DA combination circuit.The design meeting of these high frequencies and high performance IC device is with low series resistance, low-loss, and high-quality-factor and low RC time constant are purpose.Yet these designing requirements are all relevant with electric capacity in the device.
Electric capacity is made up of the dielectric layer between two battery lead plates and two battery lead plates up and down in the IC device.The manufacture method of conventional electric capacity sees also Fig. 1.Deposit bottom electrode layer successively 2 on the substrate of having made 1, dielectric layer 3 and top electrode layer 4, corrosion barrier layer 5 and etch mask layer 6; Carry out etching then, etch away etch mask layer 6 corrosion barrier layer 5 and top electrode layer 4 in addition; Pass the via hole 7 that metal that corrosion barrier layer 5 and dielectric layer 3 form bottom electrode layer 2 and top electrode layer 4 is connected at last.Before making electric capacity, made the circuit layer that is complementary with electric capacity on the substrate 1.Bottom electrode layer 2 and top electrode layer 4 adopt metallic aluminium, copper or other metal material usually, and thin one deck dielectric layer 3 adopts the method for chemical vapor deposition to make between bottom electrode 2 and the top electrodes 4.This dielectric layer 3 is the dielectric constant materials with smaller, and commonly used is silicon nitride and silica material.
Along with the development of integrated device performance, the capacitance that requires usually to make surpasses 100nf (1nf=10
-9F).For satisfying the making requirement of capacitance, not only to adopt the ultra-thin medium layer, also need to increase the size of chip simultaneously.So not only increased the area of IC device, super thin oxide layer causes the leakage current generating of IC device simultaneously, and manufacture process is difficult to control.These factors have brought the problem of power consumption and thermal control for the IC device, have increased the cost of entire I C element manufacturing simultaneously.Adopting the capacity of the dielectric layer increase electric capacity of big dielectric constant is a present feasible way.If adopt conventional capacitor manufacturing method to make the big dielectric layer of dielectric constant, in the deposition process higher temperature can make the circuit layer related with electric capacity just in the substrate 1 performance of circuit layer be affected and very likely suffer damage.Electric capacity with the big dielectric layer of dielectric constant make have its manufacture craft can't with the problem of the manufacturing process compatibility of entire I C device.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of electric capacity, the leakage current that exists with the making that solves large bulk capacitance in the present IC device is big and cost of manufacture is high and have the big dielectric layer of dielectric constant the electric capacity making can't with the problem of the manufacturing process compatibility of entire I C device.
For solving the problems of the technologies described above, capacitor manufacturing method of the present invention, it may further comprise the steps: step 1: a substrate is provided, and a top electrode layer and the initial medium layer of being deposited with successively; Step 2: after forming an ion injecting mask layer on the initial medium layer of described step 1, adopt ion to inject and form another dielectric layer; Step 3: after removing ion injecting mask layer, another electrode layer of deposit and corrosion barrier layer form etch mask layer on corrosion barrier layer successively; Step 4: the part of the unlapped corrosion barrier layer of the described etch mask layer of etching and another electrode layer; Step 5: form the conductive via that passes corrosion barrier layer respectively and pass the initial medium layer after removing described etch mask layer.Wherein, the electrode layer of deposit is the bottom electrode layer of electric capacity in the step 1, and another electrode layer of deposit is the top electrode layer of electric capacity in the step 3.The dielectric constant of another dielectric layer in the step 2 is greater than the dielectric constant of the initial medium layer in the step 1.The ion injecting mask layer in the step 1 and the pattern of the etch mask layer in the step 3 are anti-phase mask pattern, and ion injecting mask layer and etch mask layer form by photoresist.Ion injecting mask layer and described etch mask layer adopt two mask making of reverse tone each other respectively; Or ion injecting mask layer and described etch mask layer adopt same mask to make, and the polarity of the photoresist of ion injecting mask layer is opposite with the polarity of the photoresist of etch mask layer.Initial medium is generally silicide material, another medium be dielectric constants such as tantalum oxide, hafnium oxide, scandium oxide, silicon oxidation hafnium, aluminium oxide, barium strontium titanate or piezoelectric bigger mix silicon composite.Etching in the step 4 adopts dry etching.
Compare with the manufacture method of existing electric capacity, the present invention injects the ion that carries out big dielectric constant by employing ion in the initial medium layer and injects the electric capacity making that can realize having the big dielectric layer of dielectric constant, the manufacture craft compatibility of this and entire I C device, by adopting the big medium of dielectric constant effectively to improve capacitance, the leakage current the problem includes: of avoiding traditional fabrication high power capacity electric capacity problem greatly, too much takies the problem and the high problem appearance of cost of manufacture of area of chip.
Description of drawings
Below in conjunction with the drawings and specific embodiments the manufacture method of electric capacity of the present invention is done further concrete description in detail.
Fig. 1 is the manufacture method schematic diagram of traditional capacitance.
Fig. 2 is the manufacture method schematic diagram of electric capacity of the present invention.
Embodiment
See also the manufacture method of Fig. 2 electric capacity of the present invention, it comprises step 1: a substrate 1 is provided, and a top electrode layer 11 and the initial medium layer 13 of being deposited with successively.Step 2: after forming an ion injecting mask layer 8 on the initial medium layer 13 that step 1 forms, adopt ion to inject and form another dielectric layer 9; Step 3: after removing ion injecting mask layer 8, another electrode layer 12 of deposit and corrosion barrier layer 5 form etch mask layer 6 on corrosion barrier layer 5 successively; Step 4: the part of etching etch mask layer 6 unlapped corrosion barrier layers 5 and another electrode layer 12; Step 5: remove etch mask layer 6 backs and form the conductive via 10 that passes corrosion barrier layer 5 respectively and pass initial medium layer 13.
The electrode layer 11 of deposit in the step 1 is the bottom electrode layer of electric capacity, and another electrode layer 12 of deposit is a top electrode layer in the step 3.The dielectric constant of another dielectric layer 9 in the step 2 is greater than the dielectric constant of the initial medium layer 13 in the step 1.The material of initial medium layer 13 is a silicide material commonly used in the conventional method, and another dielectric layer 9 is tantalum oxide (Ta
2O
5), hafnium oxide (HfO
2), zirconia (ZrO
2), silicon oxidation hafnium (HfSiO), aluminium oxide (Al
2O
3), barium strontium titanate (BST) or piezoelectric dielectric constants such as (PZT) bigger mix silicon composite.The ion injecting mask layer 8 in the step 1 and the pattern of the etch mask layer 6 in the step 3 are anti-phase mask pattern, and ion injecting mask layer 8 and etch mask layer 6 form by photoresist.Ion injecting mask layer 8 and etch mask layer 6 adopt two mask making of reverse tone each other respectively.Or ion injecting mask layer 8 and the same mask making of etch mask layer 6 employings, and the polarity of the photoresist of ion injecting mask layer 8 is opposite with the polarity of the photoresist of etch mask layer 6.If adopt the pattern of etch mask layer 6 to unify to make ion injecting mask layer 8 and etch mask layer 6, then etch mask layer 6 adopts positive photoresistance, and ion injecting mask layer adopts negative photoresistance; If adopt the pattern of ion injecting mask layer 8 to unify to make ion injecting mask layer 8 and etch mask layer 6, then ion injecting mask layer 8 adopts positive photoresistance, and etch mask layer 6 adopts negative photoresistance.The etching that adopts in the step 4 is a dry etching, and anisotropic characteristics are feasible to reach the purpose of removing etch mask layer 6 unlapped corrosion barrier layers 5 and top electrode layer 12 parts preferably because dry etching has.
By adopting ion injection method can realize the making of the dielectric layer of high dielectric constant of electric capacity at the initial medium layer, traditional relatively manufacture method, do not need the extra making mask of requiring great effort, the manufacture craft of whole capacitor all with the manufacture craft compatibility of entire I C device, avoiding occurring the circuit part that is associated with electric capacity that the manufacturing process influence of electric capacity made is the problem of substrate.Carry out ion by the dielectric material that adopts high-k and inject and make high power capacity electric capacity, avoided relying in traditional high capacitance manufacture method leakage current that the change of the attenuate of dielectric layer and pole plate size brings greatly, too much taken the high problem of area of chip and cost of manufacture and produce.
Claims (8)
1. the manufacture method of an electric capacity is characterized in that, it may further comprise the steps:
Step 1: a substrate is provided, and a top electrode layer and the initial medium layer of being deposited with successively;
Step 2: after forming an ion injecting mask layer on the initial medium layer of described step 1, adopt ion to inject and form another dielectric layer;
Step 3: after removing ion injecting mask layer, another electrode layer of deposit and corrosion barrier layer form etch mask layer on described corrosion barrier layer successively;
Step 4: the part of the unlapped corrosion barrier layer of the described etch mask layer of etching and another electrode layer;
Step 5: form the conductive via that passes corrosion barrier layer respectively and pass the initial medium layer after removing described etch mask layer,
Wherein, the dielectric constant of another dielectric layer in the described step 2 is greater than the dielectric constant of the initial medium layer in the described step 1.
2. the manufacture method of electric capacity as claimed in claim 1 is characterized in that, the electrode layer of deposit is the bottom electrode layer of electric capacity in the described step 1, and another electrode layer of deposit is the top electrode layer of electric capacity in the described step 3.
3. the manufacture method of electric capacity as claimed in claim 1 is characterized in that, described initial medium is a silicide material.
4. the manufacture method of electric capacity as claimed in claim 1 is characterized in that, described another medium is tantalum oxide, hafnium oxide, scandium oxide, silicon oxidation hafnium, aluminium oxide or piezoelectric.
5. the manufacture method of electric capacity as claimed in claim 1, it is characterized in that, the ion injecting mask layer in the described step 2 and the pattern of the etch mask layer in the described step 3 are anti-phase mask pattern, and described ion injecting mask layer and etch mask layer form by photoresist.
6. the manufacture method of electric capacity as claimed in claim 5 is characterized in that, described ion injecting mask layer and described etch mask layer adopt two mask making of reverse tone each other respectively.
7. the manufacture method of electric capacity as claimed in claim 5, it is characterized in that, described ion injecting mask layer and described etch mask layer adopt same mask to make, and the polarity of the photoresist of described ion injecting mask layer is opposite with the polarity of the photoresist of described etch mask layer.
8. the manufacture method of electric capacity as claimed in claim 1 is characterized in that, dry etching is adopted in the etching in the described step 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100330453A CN101494195B (en) | 2008-01-24 | 2008-01-24 | Preparation method of capacitance |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100330453A CN101494195B (en) | 2008-01-24 | 2008-01-24 | Preparation method of capacitance |
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| Publication Number | Publication Date |
|---|---|
| CN101494195A CN101494195A (en) | 2009-07-29 |
| CN101494195B true CN101494195B (en) | 2010-10-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100330453A Expired - Fee Related CN101494195B (en) | 2008-01-24 | 2008-01-24 | Preparation method of capacitance |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10601397B2 (en) * | 2017-03-24 | 2020-03-24 | Zhuhai Crystal Resonance Technologies Co., Ltd. | RF resonator electrode and membrane combinations and method of fabrication |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1129354A (en) * | 1994-12-28 | 1996-08-21 | 松下电子工业株式会社 | Capacity element of integrated circuit and manufacturing method thereof |
| US6720607B1 (en) * | 1999-03-01 | 2004-04-13 | Micron Technology, Inc. | Method for improving the resistance degradation of thin film capacitors |
| US20040209423A1 (en) * | 2003-04-15 | 2004-10-21 | Weidong Tian | Methods for reducing capacitor dielectric absorption and voltage coefficient |
| US6952029B1 (en) * | 1999-01-08 | 2005-10-04 | Micron Technology, Inc. | Thin film capacitor with substantially homogenous stoichiometry |
-
2008
- 2008-01-24 CN CN2008100330453A patent/CN101494195B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1129354A (en) * | 1994-12-28 | 1996-08-21 | 松下电子工业株式会社 | Capacity element of integrated circuit and manufacturing method thereof |
| US6952029B1 (en) * | 1999-01-08 | 2005-10-04 | Micron Technology, Inc. | Thin film capacitor with substantially homogenous stoichiometry |
| US6720607B1 (en) * | 1999-03-01 | 2004-04-13 | Micron Technology, Inc. | Method for improving the resistance degradation of thin film capacitors |
| US20040209423A1 (en) * | 2003-04-15 | 2004-10-21 | Weidong Tian | Methods for reducing capacitor dielectric absorption and voltage coefficient |
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| CN101494195A (en) | 2009-07-29 |
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