CN112928164A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN112928164A CN112928164A CN201911236067.4A CN201911236067A CN112928164A CN 112928164 A CN112928164 A CN 112928164A CN 201911236067 A CN201911236067 A CN 201911236067A CN 112928164 A CN112928164 A CN 112928164A
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- 238000000034 method Methods 0.000 title claims abstract description 157
- 239000004065 semiconductor Substances 0.000 title claims abstract description 71
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 69
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 239000000463 material Substances 0.000 claims description 40
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 24
- 239000001301 oxygen Substances 0.000 claims description 24
- 229910052760 oxygen Inorganic materials 0.000 claims description 24
- 239000007789 gas Substances 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 20
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 7
- 229910001882 dioxygen Inorganic materials 0.000 claims description 7
- 238000009832 plasma treatment Methods 0.000 claims description 4
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 claims description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 21
- 230000015572 biosynthetic process Effects 0.000 abstract description 16
- 239000010410 layer Substances 0.000 description 300
- 239000010408 film Substances 0.000 description 24
- 230000003647 oxidation Effects 0.000 description 17
- 238000007254 oxidation reaction Methods 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 230000007547 defect Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 5
- 239000006227 byproduct Substances 0.000 description 5
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- IFYDWYVPVAMGRO-UHFFFAOYSA-N n-[3-(dimethylamino)propyl]tetradecanamide Chemical compound CCCCCCCCCCCCCC(=O)NCCCN(C)C IFYDWYVPVAMGRO-UHFFFAOYSA-N 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 2
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- 239000002356 single layer Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 238000010420 art technique Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
-
- H01L21/205—
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method of the semiconductor structure comprises the following steps: providing a base, wherein the base comprises a substrate and a fin part protruding out of the substrate; forming a first oxide layer on the top and the side wall of the fin part and the surface of the substrate by adopting a plasma enhanced atomic layer deposition process, wherein the output power adopted by the plasma enhanced atomic layer deposition process for forming the first oxide layer is first power; and forming a second oxide layer on the first oxide layer by adopting a plasma enhanced atomic layer deposition process, wherein the output power adopted by the plasma enhanced atomic layer deposition process for forming the second oxide layer is a second power, the second power is greater than the first power, and the second oxide layer and the first oxide layer are used for forming a gate oxide layer. The embodiment of the invention is beneficial to improving the formation quality of the gate oxide layer, further is beneficial to improving the electrical property of the gate oxide layer and correspondingly optimizes the property of the semiconductor structure.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
In Semiconductor manufacturing, with the trend of ultra-large scale integrated circuits, the feature size of the integrated circuit is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is also continuously shortened correspondingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the control capability of the gate structure to the channel is deteriorated, and the difficulty of the gate voltage pinching off the Pinch off channel is increased, so that the sub-threshold leakage (Subthreshold leakage) phenomenon, namely the so-called short channel effect (SCE: short-channel effects) occur more easily.
Therefore, in order to reduce the impact of short channel effects, semiconductor processing is gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit a short-channel effect; and finfets have better compatibility with existing integrated circuit fabrication relative to other devices.
Disclosure of Invention
The embodiment of the invention provides a semiconductor structure and a forming method thereof, which can improve the forming quality of a gate oxide layer.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a substrate and a fin part protruding out of the substrate; forming a first oxide layer on the top and the side wall of the fin part and the surface of the substrate by adopting a plasma enhanced atomic layer deposition process, wherein the output power adopted by the plasma enhanced atomic layer deposition process for forming the first oxide layer is first power; and forming a second oxide layer on the first oxide layer by adopting a plasma enhanced atomic layer deposition process, wherein the output power adopted by the plasma enhanced atomic layer deposition process for forming the second oxide layer is a second power, the second power is greater than the first power, and the second oxide layer and the first oxide layer are used for forming a gate oxide layer.
Optionally, the method for forming the semiconductor structure further includes: after the first oxide layer is formed and before a second oxide layer is formed on the first oxide layer, first ultraviolet irradiation treatment is performed on the first oxide layer, so that the compactness of the first oxide layer is improved.
Optionally, the method for forming the semiconductor structure further includes: after the first oxide layer is formed and before the second oxide layer is formed on the first oxide layer, the first oxide layer is subjected to microwave treatment, so that the compactness of the first oxide layer is improved.
Optionally, the first power is 50W to 200W.
Optionally, the second power is 300W to 500W.
Optionally, the thickness of the first oxide layer is
To
Optionally, the process parameters of the first ultraviolet irradiation treatment include: the temperature is 0-100 ℃, and the irradiation time is 1-120 min.
Optionally, in the step of forming the second oxide layer, the thickness of the second oxide layer is
To
Optionally, after forming the second oxide layer, the method for forming the semiconductor structure further includes: and carrying out second ultraviolet irradiation treatment on the second oxide layer, wherein the second ultraviolet irradiation treatment is suitable for improving the density of the second oxide layer.
Optionally, performing a second ultraviolet irradiation treatment on the second oxide layer in an oxygen-containing gas atmosphere; alternatively, after the second ultraviolet irradiation treatment, the method for forming a semiconductor structure further includes: and performing a second plasma treatment on the second oxide layer in an oxygen-containing gas atmosphere.
Optionally, the process parameters of the second ultraviolet irradiation treatment include: the temperature is 0-100 ℃, and the irradiation time is 1-120 min.
Optionally, in an oxygen-containing gas atmosphere, performing a second ultraviolet irradiation treatment on the second oxide layer, where the oxygen-containing gas is oxygen, and a gas flow rate of the oxygen is 0 seem to 500 seem.
Optionally, the material of the first oxide layer includes silicon oxide.
Optionally, the material of the second oxide layer includes silicon oxide.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: the substrate comprises a substrate and a fin part protruding out of the substrate; the first oxide layer is positioned on the top and the side wall of the fin part and on the surface of the substrate, the first oxide layer is formed through a plasma enhanced atomic layer deposition process, and the output power adopted by the plasma enhanced atomic layer deposition process for forming the first oxide layer is first power; and the second oxide layer is positioned on the first oxide layer and is formed through a plasma enhanced atomic layer deposition process, the output power adopted by the plasma enhanced atomic layer deposition process for forming the second oxide layer is a second power, the second power is greater than the first power, and the second oxide layer and the first oxide layer form a gate oxide layer.
Optionally, the thickness of the first oxide layer is
To
Optionally, the thickness of the second oxide layer is
To
Optionally, the material of the first oxide layer includes silicon oxide.
Optionally, the material of the second oxide layer includes silicon oxide.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming the semiconductor structure, the first oxide layer and the second oxide layer are both formed through a plasma enhanced atomic layer deposition process, the first oxide layer and the second oxide layer are in the same growth mode, so that the properties (such as internal stress, density and the like) of the materials of the first oxide layer and the second oxide layer are relatively close, the first oxide layer and the second oxide layer are good in adhesion and few in interface defects, the formation quality of the gate oxide layer is improved, the electrical performance of the gate oxide layer is improved, and the performance of the semiconductor structure is optimized correspondingly.
In addition, the output power adopted by the plasma enhanced atomic layer deposition process for forming the first oxide layer is the first power, the output power adopted by the plasma enhanced atomic layer deposition process for forming the second oxide layer is the second power, the second power is higher than the first power, and the embodiment of the invention forms the first oxide layer by adopting the lower output power and then forms the second oxide layer by adopting the higher output power, so that the consumption of the fin part is less when the first oxide layer is formed, and the first oxide layer can play a role of blocking oxygen-containing gas used when the second oxide layer is formed, thereby being capable of adopting larger output power to form the second oxidation layer, being beneficial to improving the forming quality of the second oxidation layer, and the loss generated on the fin part is small, so that the consumption of the fin part is reduced, and the size of the fin part is accurately controlled.
In the alternative scheme, the first oxidation layer is subjected to the first ultraviolet irradiation treatment before the second oxidation layer is formed, so that the compactness of the first oxidation layer is improved, the formation quality of the first oxidation layer is improved, the higher compactness of the first oxidation layer is also favorable for improving the blocking effect of the first oxidation layer on oxygen-containing gas during the formation of the second oxidation layer, the consumption of the fin portion is further prevented, the loss of the fin portion is reduced, and the accurate control of the size of the fin portion is further facilitated.
Drawings
Fig. 1 to 3 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure;
FIGS. 4 to 8 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention;
FIG. 9 is a TDDB Weibull plot of a semiconductor structure formed using a method of an embodiment of the invention;
FIG. 10 is a graph of the etch rate of a wet etch process per unit time for a gate oxide layer formed using a method of an embodiment of the invention;
fig. 11 is a schematic view of a partial structure of a fin portion and a gate oxide layer formed by the forming method of the embodiment of the invention, and consumption of the fin portion.
Detailed Description
The devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.
Referring to fig. 1 to 3, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, a base is provided, and the base includes a substrate 1 and a fin portion 2 protruding from the substrate 1.
Referring to fig. 2, a thermal oxidation growth process is used to convert the top and sidewalls of the fin 2, and a portion of the thickness of the material on the surface of the substrate 1 into a first oxide layer 3.
Referring to fig. 3, a second oxide layer 4 is formed on the first oxide layer 3 by a plasma enhanced atomic layer deposition process, and the second oxide layer 4 and the first oxide layer 3 form a gate oxide layer 5.
In the forming method of the semiconductor structure, the first oxidation layer 3 is formed through a thermal oxidation growth process, and the first oxidation layer 3 material formed through the thermal oxidation growth process has high density and few impurity defects, so that the quality of a thin film of the gate oxide layer 5 is improved; the second oxide layer 4 is formed by a plasma enhanced atomic layer deposition process, which is beneficial to reducing the consumption of the fin portion 2.
However, the formation processes of the first oxide layer 3 and the second oxide layer 4 are different, and the characteristics of the materials of the first oxide layer 3 and the second oxide layer 4 are also different, for example: compactness, internal stress and the like, which easily cause interface defects at the interface of the first oxide layer 3 and the second oxide layer 4, resulting in poor formation quality of the gate oxide layer 5, and further easily affecting the electrical properties of the gate oxide layer 5, for example: insulation properties, resistance to breakdown, etc., leading to poor device performance.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a substrate and a fin part protruding out of the substrate; forming a first oxide layer on the top and the side wall of the fin part and the surface of the substrate by adopting a plasma enhanced atomic layer deposition process, wherein the output power adopted by the plasma enhanced atomic layer deposition process for forming the first oxide layer is first power; and forming a second oxide layer on the first oxide layer by adopting a plasma enhanced atomic layer deposition process, wherein the output power adopted by the plasma enhanced atomic layer deposition process for forming the second oxide layer is a second power, the second power is greater than the first power, and the second oxide layer and the first oxide layer are used for forming a gate oxide layer.
In the method for forming the semiconductor structure, the first oxide layer and the second oxide layer are both formed through a plasma enhanced atomic layer deposition process, the first oxide layer and the second oxide layer are in the same growth mode, so that the properties (such as internal stress, density and the like) of the materials of the first oxide layer and the second oxide layer are relatively close, the first oxide layer and the second oxide layer are good in adhesion and few in interface defects, the formation quality of the gate oxide layer is improved, the electrical performance of the gate oxide layer is improved, and the performance of the semiconductor structure is optimized correspondingly.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 4 to 8 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 4, a base is provided, and the base includes a substrate 100 and a fin 110 protruding from the substrate 100.
The substrate 100 provides a process platform for a process.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The fin 110 is used to provide a conductive channel for a fin field effect transistor (FinFET) during operation.
In this embodiment, the material of the fin portion 110 is the same as that of the substrate 100, and the material of the fin portion 110 is silicon. In other embodiments, the material of the fin may also be a semiconductor material suitable for forming a fin, such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the fin may also be different from that of the substrate.
Referring to fig. 5, a first oxide layer 120 is formed on the top and sidewalls of the fin 110 and the surface of the substrate 100 by using a plasma enhanced atomic layer deposition process, and an output power used by the plasma enhanced atomic layer deposition process for forming the first oxide layer 120 is a first power.
The first oxide layer 120 is used to form a gate oxide layer.
In this embodiment, the material of the first oxide layer 120 is silicon oxide. Silicon oxide is a commonly used gate oxide layer material in a semiconductor process, and is beneficial to improving process compatibility.
In this embodiment, the first oxide layer 120 is formed by an atomic layer deposition process. The atomic layer deposition process is a Self-limiting (Self-limiting) reaction process based on the atomic layer deposition process, the deposited film can reach the thickness of a single layer of atoms, and because the atomic layer deposition process can accurately deposit one atomic layer in each period, the atomic layer deposition process is selected to be beneficial to accurately controlling the thickness of the first oxide layer 120 and enabling the thickness of the first oxide layer 120 to be smaller so as to meet the process requirements, in addition, the film prepared by the ALD process has the characteristics of good bonding strength, consistent film thickness, good component uniformity, good conformality and the like, and is beneficial to improving the thickness uniformity and the film quality of the first oxide layer 120.
Specifically, the first oxide layer 120 is formed by a Plasma Enhanced Atomic Layer Deposition (PEALD) process. By using a plasma enhanced atomic layer deposition process, the consumption of the fin portion 110 can be further reduced.
The output power adopted by the plasma enhanced atomic layer deposition process for forming the first oxide layer 120 is a first power. The first power is not suitable to be too large, the output power is used for controlling the energy carried by the plasma, if the first power is too large, the energy of the plasma reaching the surface of the fin 110 is large, on one hand, the consumption of the fin 110 is easily excessive, on the other hand, the plasma hitting the fin 110 is directional, if the first power is too large, the anisotropy of the plasma is strong, and compared with the plasma contacting the top surface of the fin 110, the plasma contacting the side wall of the fin 110 is less, so that the thickness uniformity of the first oxide layer 120 formed on the top of the fin 110 and the side wall of the fin 110 is easily low. For this reason, in the present embodiment, the first power is less than or equal to 200W, so as to improve the thickness uniformity of the first oxide layer 120 while reducing the consumption of the fin 110.
Specifically, in this embodiment, the first power is 50W to 200W.
The thickness of the first oxide layer 120 should not be too small or too large. If the thickness of the first oxide layer 120 is too small, the film quality of the first oxide layer 120 is easily poor, for example: the film continuity is poor, the defect density is high, and the like, and the output power adopted when a second oxide layer is formed on the first oxide layer 120 through a plasma enhanced atomic layer deposition process is a second power, wherein the second power is higher than the first power, and the blocking effect of the first oxide layer 120 on the oxygen-containing gas during the formation of the second oxide layer is easily reduced due to the over-small thickness of the first oxide layer 120; if the thickness of the first oxide layer 120 is too large, a second oxide layer is formed on the first oxide layer 120 subsequently, the second oxide layer and the first oxide layer 120 are used for forming a gate oxide layer, the thickness of the gate oxide layer is easily too large due to the too large thickness of the first oxide layer 120, the consumption of the fin portion 110 is also easily too much due to the too large thickness of the first oxide layer 120, in addition, the density of the first oxide layer 120 is improved by performing ultraviolet irradiation treatment on the first oxide layer 120 subsequently, the ultraviolet ray is easily difficult to penetrate through the first oxide layer 120 due to the too large thickness of the first oxide layer 120, and further, the incomplete treatment or poor treatment uniformity of the first oxide layer 120 is easily caused. For this reason, in this embodiment, the thickness of the first oxide layer 120 is
To
For example:
and the like.
With combined reference to fig. 6, the method for forming the semiconductor structure further includes: after the first oxide layer 120 is formed, a first ultraviolet radiation (UV cure) treatment 130 is performed on the first oxide layer 120, which is suitable for increasing the density of the first oxide layer 120.
By performing the first ultraviolet irradiation (UV cure) treatment 130 on the first oxide layer 120, the density of the first oxide layer 120 is improved, which is beneficial to improving the film quality of the first oxide layer 120, and the density of the first oxide layer 120 is higher, so that in the subsequent step of forming the second oxide layer, the blocking effect of the first oxide layer 120 on the oxygen-containing gas is improved, and further, the consumption of the fin portion 110 during the subsequent formation of the second oxide layer is reduced.
Furthermore, the ultraviolet radiation has high energy, and the ultraviolet radiation can irradiate the first oxide layer 120 with ultraviolet radiation 130 to generate byproducts (e.g., -CH) in the first oxide layer 120 with less consumption of the fin 1102CH3By-products) is broken, and the by-products are diffused from the first oxide layer 120, so that the content of impurities such as by-products in the first oxide layer 120 is reduced, the bonding probability of silicon-oxygen bonds in the first oxide layer 120 is increased, the density of the first oxide layer 120 is correspondingly increased, and the film quality of the first oxide layer 120 is improved.
In addition, the first ultraviolet radiation (UV cure) treatment 130 is also beneficial to improving the compactness of the first oxide layer 120 without consuming the fin portion 110.
The temperature of the first ultraviolet irradiation treatment 130 is not preferably too low or too high. If the temperature of the first ultraviolet irradiation treatment 130 is too low, the treatment rate and treatment effect of the first ultraviolet irradiation treatment 130 are easily reduced; if the temperature of the first uv irradiation treatment 130 is too high, the structure of the fin 110 may be damaged. For this reason, in the present embodiment, if the temperature of the first ultraviolet irradiation treatment 130 is 0 ℃ to 100 ℃, for example: 10 ℃, 20 ℃, 30 ℃ and the like
In this embodiment, the irradiation time of the first ultraviolet irradiation treatment 130 is 1min to 120 min.
In this embodiment, after the first oxide layer 120 is formed, a first ultraviolet irradiation (UV cure) treatment 130 is performed on the first oxide layer 120, which is suitable for increasing the density of the first oxide layer 120.
In other embodiments, the method for forming the semiconductor structure further includes: after the first oxide layer is formed and before the second oxide layer is formed on the first oxide layer, the first oxide layer is subjected to microwave treatment, so that the compactness of the first oxide layer is improved.
The microwave treatment can generate high-energy microwaves, break the connecting bonds of byproducts in the buffer layer and remove impurities in the buffer layer, so that the density and the film quality of the first oxidation layer are improved.
Referring to fig. 7, a second oxide layer 140 is formed on the first oxide layer 120 by using a plasma enhanced atomic layer deposition process, and an output power used by the plasma enhanced atomic layer deposition process for forming the second oxide layer 140 is a second power, where the second power is greater than the first power, and the second oxide layer 140 and the first oxide layer 120 are used to form a gate oxide layer 150.
In the embodiment of the present invention, the first oxide layer 120 and the second oxide layer 140 are both formed by a plasma enhanced atomic layer deposition process, and the first oxide layer 120 and the second oxide layer 140 have the same growth mode, so that the properties (for example, internal stress, quality, and the like) of the materials of the first oxide layer 120 and the second oxide layer 140 are relatively close, the adhesion between the first oxide layer 120 and the second oxide layer 140 is relatively good, and interface defects are relatively few, thereby facilitating to improve the formation quality of the gate oxide layer 150, further facilitating to improve the electrical performance of the gate oxide layer 150, and correspondingly optimizing the performance of the semiconductor structure.
In this embodiment, the material of the second oxide layer 140 is the same as the material of the first oxide layer 120, and the material of the second oxide layer 140 is silicon oxide, which is beneficial to improving process compatibility.
In this embodiment, the second oxide layer 140 is formed by an atomic layer deposition process. The atomic layer deposition process is a Self-limiting (Self-limiting) reaction process based on the atomic layer deposition process, the deposited film can reach the thickness of a single layer of atoms, and because the atomic layer deposition process can accurately deposit one atomic layer in each period, the atomic layer deposition process is selected to be beneficial to accurately controlling the thickness of the second oxide layer 140 and enabling the thickness of the second oxide layer 140 to be smaller so as to meet the process requirements, in addition, the film prepared by the ALD process has the characteristics of good bonding strength, consistent film thickness, good component uniformity, good conformality and the like, and is beneficial to improving the thickness uniformity and the film quality of the second oxide layer 140.
In this embodiment, the second oxide layer 140 is formed by a Plasma Enhanced Atomic Layer Deposition (PEALD) process. By using a plasma enhanced atomic layer deposition process, the consumption of the fin portion 110 can be further reduced.
By making the second power larger than the first power, the second power is larger, that is, by forming the first oxide layer 120 with a lower output power, and then forming the second oxide layer 140 with a higher output power, compared with the method of directly forming the gate oxide layer by adopting the plasma enhanced atomic layer deposition process and the plasma enhanced atomic layer deposition process adopting larger output power, the method is beneficial to improving the forming quality of the second oxide layer 140, and the first oxide layer 120 can block the oxygen-containing gas when the second oxide layer 140 is formed, even if a large output power is used to form the second oxide layer 140, the loss of the fin 110 is also small, and the oxygen-containing gas used in forming the second oxide layer 140 can also react with the first oxide layer 120, thereby further improving the compactness of the first oxide layer 120.
Therefore, the second power is not too low, otherwise it is difficult to ensure a high formation quality of the second oxide layer 140. For this reason, in this embodiment, the second power is at least 300W.
Specifically, in the embodiment, the second power is 300W to 500W, so that the second oxide layer 140 has higher film quality, the process compatibility is improved, and the consumption of the fin 110 is reduced.
In this embodiment, the thickness of the second oxide layer 140 is set according to the required thickness of the gate oxide layer 150 and the thickness of the first oxide layer 120
To
For example:
and the like.
Referring to fig. 8 in combination, after forming the second oxide layer 140, the method for forming the semiconductor structure further includes: the second ultraviolet irradiation treatment 160 is performed on the second oxide layer 140, which is suitable for increasing the density of the second oxide layer 140.
The temperature of the second ultraviolet irradiation treatment 160 is not preferably too low or too high. If the temperature of the second ultraviolet irradiation treatment 160 is too low, the treatment rate and treatment effect of the second ultraviolet irradiation treatment 160 are easily reduced; if the temperature of the second uv irradiation treatment 160 is too high, the structure of the fin 110 may be damaged. For this reason, in this embodiment, the temperature of the second ultraviolet irradiation treatment 160 is 0 ℃ to 100 ℃, for example: 10 ℃, 20 ℃, 30 ℃ and the like
In this embodiment, the irradiation time of the second ultraviolet irradiation treatment 160 is 1min to 120 min.
In this embodiment, the second ultraviolet irradiation treatment 160 is performed on the second oxide layer 140 in an oxygen-containing gas atmosphere.
By performing the second ultraviolet irradiation treatment 160 in an oxygen-containing gas atmosphere, the bonding amount of silicon and oxygen in the second oxide layer 140 is advantageously increased, and the density of the second oxide layer 140 is advantageously further increased.
In this embodiment, the second ultraviolet irradiation treatment 160 is performed on the second oxide layer 140 in an atmosphere containing oxygen, and the flow rate of oxygen is not necessarily too small or too large. If the flow rate of the oxygen gas is too small, the effect of improving the density of the second oxide layer 140 is not significant; if the oxygen gas flow is too large, the fin 110 is easily consumed. Therefore, in the present embodiment, the flow rate of the oxygen gas is 0sccm to 500sccm, for example: 100sccm, 150sccm, 200sccm, 300sccm, etc.
In the present embodiment, the second ultraviolet irradiation treatment 160 is performed on the second oxide layer 140 in an oxygen-containing gas atmosphere. In other embodiments, after performing the second ultraviolet irradiation treatment, the method for forming a semiconductor structure may further include: and performing a second plasma treatment on the second oxide layer in an oxygen-containing gas atmosphere.
By performing the second plasma treatment on the second oxide layer in the oxygen-containing gas atmosphere after the second ultraviolet irradiation treatment is performed, it is also advantageous to improve the density of the second oxide layer.
The subsequent steps further include forming a gate structure on the gate oxide layer 150 and crossing the fin 110, and forming source-drain doped regions in the fin 110 on both sides of the gate structure. The following process steps are not repeated herein.
Referring to fig. 9 in combination, curve # 2 in fig. 9 shows a TDDB (Time Dependent Dielectric Breakdown) Weibull Distribution (Weibull Distribution) plot of a semiconductor structure formed using the method of an embodiment of the present invention, and curve # 1 shows a TDDB Weibull Distribution plot of a semiconductor structure formed according to the prior art. Wherein, the abscissa is the Time to Failure (unit: seconds). As can be seen from FIG. 9, the TDDB Weibull distribution curve of the semiconductor structure formed in accordance with the embodiments of the present invention is comparable to that of the prior art semiconductor structureIs greater than the slope of2The Coefficient of determination is closer to 1, and the reliability of the semiconductor structure formed by the embodiment of the invention is better.
Referring collectively to table 1, there is shown a portion of the electrical parameters of a semiconductor structure formed using the method of an embodiment of the present invention, and a portion of the electrical parameters of a semiconductor structure formed using the prior art technique.
As can be seen from table 1, compared with the semiconductor structure formed by the prior art, the semiconductor structure of the embodiment of the present invention has a smaller equivalent electrical thickness (EOT), a smaller interface trap Density (DIT) and a smaller Contact potential difference (Vcpd), which indicates that the gate oxide layer 150 formed by the embodiment of the present invention has a better film quality and a better electrical property, and the method of the embodiment of the present invention is favorable for improving the performance of the semiconductor structure.
| Electrical parameter | Examples of the invention | Prior Art |
| EOT[50A] | 40.52 | 42.80 |
| DIT[1/cm2*eV] | 1.08E+12 | 2.15E+12 |
| Vcpd[V]Avg | -0.05 | -0.33 |
TABLE 1
Referring to fig. 10 in combination, a Wet Etch Rate (WER) of the Wet etching process for the gate oxide layer formed by the method of the embodiment of the present invention per unit time and a Wet etch rate of the Wet etching process for the gate oxide layer formed by the prior art per unit time are shown, and as can be seen from fig. 10, an etching rate of hydrofluoric acid (DHF) for the gate oxide layer of the embodiment of the present invention per unit time is shown as
The etching rate of hydrofluoric acid on the gate oxide layer formed by the prior art in unit time is
Compared with the prior art, the etching rate of hydrofluoric acid (DHF) to the gate oxide layer in the embodiment of the invention is lower in unit time, which shows that the gate oxide layer formed in the embodiment of the invention is more resistant to etching, and the film quality (such as compactness) of the gate oxide layer formed in the embodiment of the invention is better.
Referring to fig. 11 in combination, a schematic diagram of a local structure of a fin portion and a gate oxide layer formed by using the forming method of the embodiment of the present invention and a consumption amount generated for the fin portion 110 are shown, and fig. 11 further shows a schematic diagram of a structure of a fin portion and a gate oxide layer formed by using the first and second prior arts, respectively, and a consumption amount generated for the fin portion. Taking silicon as a material of the fin and silicon oxide as an example, wherein Bare Si represents the fin; oxidation represents a natural oxide layer formed on the surface of the fin; in the first prior art, Thermal OX indicates a silicon oxide formed by a Thermal oxidation growth process in the first prior art, and High Power ALDOX indicates a silicon oxide formed by a plasma enhanced atomic layer deposition process with higher output Power in the first prior art; in the second prior art, High Power ALDOX indicates that the second prior art adopts a plasma enhanced atomic layer deposition process with higher output Power to form silicon oxide; in the embodiment of the present invention, Low Power ALDOX indicates that silicon oxide formed by a plasma enhanced atomic layer deposition process with lower output Power is used as the first oxide layer in the embodiment of the present invention, and High Power ALDOX indicates that silicon oxide formed by a plasma enhanced atomic layer deposition process with higher output Power is used as the second oxide layer in the embodiment of the present invention.
As can be seen from FIG. 11, the gate oxide layer is formed by the method of the first prior art, and the loss to silicon (SiLoss) is
That is, the gate oxide layer formed by the method of the first prior art generates the loss of the fin portion
Forming a gate oxide layer by the method of the second prior art, wherein the Loss of silicon (Si Loss) is
That is, the gate oxide layer formed by the second method of the prior art generates the loss of the fin portion
The gate oxide layer 160 is formed by the method of the embodiment of the present invention, and the silicon loss (Siloss) is
That is, the loss generated by the gate oxide layer 160 formed by the method of the embodiment of the invention to the fin 110 is about the same as that generated by the gate oxide layer 160 formed by the method of the embodiment of the invention
The method of the embodiment of the invention can obviously reduce the consumption of the fin part 110.
Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 8, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: a base including a substrate 100 and a fin 110 protruding from the substrate 100; the first oxide layer 120 is located on the top and the side wall of the fin portion 110 and the surface of the substrate 100, the first oxide layer 120 is formed through a plasma enhanced atomic layer deposition process, and the output power adopted by the plasma enhanced atomic layer deposition process for forming the first oxide layer 120 is a first power; and a second oxide layer 140 on the first oxide layer 120, wherein the second oxide layer 140 is formed by a plasma enhanced atomic layer deposition process, an output power adopted by the plasma enhanced atomic layer deposition process for forming the second oxide layer 140 is a second power, the second power is greater than the first power, and the second oxide layer 140 and the first oxide layer 120 form a gate oxide layer 150.
In the embodiment of the present invention, the first oxide layer 120 and the second oxide layer 140 are both formed by a plasma enhanced atomic layer deposition process, and the first oxide layer 120 and the second oxide layer 140 have the same growth mode, so that the properties (for example, internal stress, quality, and the like) of the materials of the first oxide layer 120 and the second oxide layer 140 are relatively close, the adhesion between the first oxide layer 120 and the second oxide layer 140 is relatively good, and interface defects are relatively few, thereby facilitating to improve the formation quality of the gate oxide layer 150, further facilitating to improve the electrical performance of the gate oxide layer 150, and correspondingly optimizing the performance of the semiconductor structure.
The substrate 100 provides a process platform for a process.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The fin 110 is used to provide a conductive channel for a fin field effect transistor (FinFET) during operation.
In this embodiment, the material of the fin portion 110 is the same as that of the substrate 100, and the material of the fin portion 110 is silicon. In other embodiments, the material of the fin may also be a semiconductor material suitable for forming a fin, such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the fin may also be different from that of the substrate.
In this embodiment, the material of the first oxide layer 120 is silicon oxide. Silicon oxide is a commonly used gate oxide layer material in a semiconductor process, and is beneficial to improving process compatibility.
The first oxide layer 120 is formed through a plasma enhanced atomic layer deposition process, which is beneficial to accurately controlling the thickness of the first oxide layer 120 and enabling the thickness of the first oxide layer 120 to be smaller so as to meet the process requirements, and in addition, the film prepared through the ALD process has the characteristics of good bonding strength, consistent film thickness, good component uniformity, good shape retention and the like, and is beneficial to improving the thickness uniformity and the film quality of the first oxide layer 120.
The first power is smaller than the second power, and the first power is smaller, which is beneficial to reducing consumption of the fin portion 110 when the first oxide layer 120 is formed and improving thickness consistency of the first oxide layer 120.
The thickness of the first oxide layer 120 should not be too small or too large. If the thickness of the first oxide layer 120 is too small, the film quality of the first oxide layer 120 is easily poor, for example: the film continuity is not good, the defect density is large, and the output power of the plasma enhanced atomic layer deposition process when the second oxide layer 140 is formed is a second power, the second power is larger than the first power, and the blocking effect of the first oxide layer 120 on the oxygen-containing gas when the second oxide layer 140 is formed is easily reduced when the thickness of the first oxide layer 120 is too small; if the thickness of the first oxide layer 120 is too large, the thickness of the gate oxide layer 150 is too large, and the consumption of the fin 110 is too high due to the too large thickness of the first oxide layer 120. For this reason, in this embodiment, the thickness of the first oxide layer 120 is
To
For example:
and the like.
In this embodiment, the material of the second oxide layer 140 is the same as the material of the first oxide layer 120, and the material of the second oxide layer 140 is silicon oxide, which is beneficial to improving process compatibility.
The second oxide layer 140 is formed through a plasma enhanced atomic layer deposition process, which is beneficial to accurately controlling the thickness of the second oxide layer 140 and enabling the thickness of the second oxide layer 140 to be smaller so as to meet the process requirements, and in addition, the film prepared through the ALD process has the characteristics of good bonding strength, consistent film thickness, good component uniformity, good conformality and the like, and is beneficial to improving the thickness uniformity and the film quality of the second oxide layer 140.
The second power is larger than the first power, so that the second power is larger, which is beneficial to improving the formation quality of the second oxide layer 140, and in addition, the oxygen-containing gas adopted in the formation of the second oxide layer 140 can also react with the first oxide layer 120, thereby further improving the compactness of the first oxide layer 120.
In this embodiment, the thickness of the second oxide layer 140 is set according to the required thickness of the gate oxide layer 150 and the thickness of the first oxide layer 120
To
For example:
and the like.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (19)
1. A method of forming a semiconductor structure, comprising:
providing a base, wherein the base comprises a substrate and a fin part protruding out of the substrate;
forming a first oxide layer on the top and the side wall of the fin part and the surface of the substrate by adopting a plasma enhanced atomic layer deposition process, wherein the output power adopted by the plasma enhanced atomic layer deposition process for forming the first oxide layer is first power;
and forming a second oxide layer on the first oxide layer by adopting a plasma enhanced atomic layer deposition process, wherein the output power adopted by the plasma enhanced atomic layer deposition process for forming the second oxide layer is a second power, the second power is greater than the first power, and the second oxide layer and the first oxide layer are used for forming a gate oxide layer.
2. The method of forming a semiconductor structure of claim 1, further comprising: after the first oxide layer is formed and before a second oxide layer is formed on the first oxide layer, first ultraviolet irradiation treatment is performed on the first oxide layer, so that the compactness of the first oxide layer is improved.
3. The method of forming a semiconductor structure of claim 1, further comprising: after the first oxide layer is formed and before the second oxide layer is formed on the first oxide layer, the first oxide layer is subjected to microwave treatment, so that the compactness of the first oxide layer is improved.
4. The method of forming a semiconductor structure of claim 1, wherein the first power is 50W to 200W.
5. The method of claim 1, wherein the second power is 300W to 500W.
6. The method of claim 1, wherein the first oxide layer has a thickness of
To
7. The method of forming a semiconductor structure of claim 2, wherein the process parameters of the first ultraviolet irradiation treatment comprise: the temperature is 0-100 ℃, and the irradiation time is 1-120 min.
8. The method of claim 1, wherein in the step of forming the second oxide layer, the second oxide layer has a thickness of
To
9. The method of forming a semiconductor structure of claim 1, wherein after forming the second oxide layer, the method of forming a semiconductor structure further comprises: and carrying out second ultraviolet irradiation treatment on the second oxide layer, wherein the second ultraviolet irradiation treatment is suitable for improving the density of the second oxide layer.
10. The method for forming a semiconductor structure according to claim 9, wherein the second oxide layer is subjected to second ultraviolet irradiation treatment in an oxygen-containing gas atmosphere;
alternatively, after the second ultraviolet irradiation treatment, the method for forming a semiconductor structure further includes: and performing a second plasma treatment on the second oxide layer in an oxygen-containing gas atmosphere.
11. The method of claim 9, wherein the process parameters of the second uv irradiation treatment comprise: the temperature is 0-100 ℃, and the irradiation time is 1-120 min.
12. The method for forming a semiconductor structure according to claim 10, wherein the second ultraviolet irradiation treatment is performed on the second oxide layer in an atmosphere containing oxygen gas, wherein the oxygen gas is oxygen gas, and a gas flow rate of the oxygen gas is 0 seem to 500 seem.
13. The method of forming a semiconductor structure of claim 1, wherein a material of the first oxide layer comprises silicon oxide.
14. The method of forming a semiconductor structure of claim 1, wherein a material of the second oxide layer comprises silicon oxide.
15. A semiconductor structure, comprising:
the substrate comprises a substrate and a fin part protruding out of the substrate;
the first oxide layer is positioned on the top and the side wall of the fin part and on the surface of the substrate, the first oxide layer is formed through a plasma enhanced atomic layer deposition process, and the output power adopted by the plasma enhanced atomic layer deposition process for forming the first oxide layer is first power;
and the second oxide layer is positioned on the first oxide layer and is formed through a plasma enhanced atomic layer deposition process, the output power adopted by the plasma enhanced atomic layer deposition process for forming the second oxide layer is a second power, the second power is greater than the first power, and the second oxide layer and the first oxide layer form a gate oxide layer.
16. The semiconductor structure of claim 15, wherein the first oxide layer has a thickness of
To
17. The semiconductor structure of claim 15, wherein the second oxide layer has a thickness of
To
18. The semiconductor structure of claim 15, wherein a material of the first oxide layer comprises silicon oxide.
19. The semiconductor structure of claim 15, in which a material of the second oxide layer comprises silicon oxide.
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