CN112151379B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN112151379B CN112151379B CN201910577101.8A CN201910577101A CN112151379B CN 112151379 B CN112151379 B CN 112151379B CN 201910577101 A CN201910577101 A CN 201910577101A CN 112151379 B CN112151379 B CN 112151379B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein the substrate comprises a substrate, a gate structure positioned on the substrate, source and drain doped regions positioned in the substrate at two sides of the gate structure and an interlayer dielectric layer positioned on the source and drain doped regions; the substrate comprises a device region and an isolation region, a grid structure positioned on the device region is used as a device grid structure, and the grid structure positioned on the isolation region is a pseudo grid structure; etching the substrate between the dummy gate structure and the source-drain doped region below the dummy gate structure to form an opening; forming an isolation layer and a stress dielectric layer on the isolation layer in the opening; the compressive stress of the stress dielectric layer on the source-drain doped region is greater than that of the isolation layer on the source-drain doped region. When the semiconductor structure works, the stress dielectric layer can generate stress on the source-drain doped region, and the source-drain doped region can provide stress for a channel below the device grid structure, so that the carrier migration rate in the channel is improved, and the electrical performance of the semiconductor structure is further improved.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device is shortened, the distance between the source region and the drain region of the device is shortened, so that the control capability of the gate structure on the channel is further and further reduced, and the difficulty of pinching off (pin off) the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely so-called short-channel effects (SCE), is more likely to occur.
Accordingly, to reduce the impact of short channel effects, semiconductor processes are gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) from at least two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit short channel effect; and finfets have better compatibility with existing integrated circuit fabrication than other devices.
Disclosure of Invention
The problem to be solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are used for optimizing the performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate, a gate structure positioned on the substrate, source and drain doped regions positioned in the substrate at two sides of the gate structure, and an interlayer dielectric layer positioned on the source and drain doped regions; the substrate comprises a device region and an isolation region, wherein the gate structure positioned on the device region is used as a device gate structure, and the gate structure positioned on the isolation region is a pseudo gate structure; etching the substrate between the dummy gate structure and the source-drain doped region below the dummy gate structure to form an opening; forming an isolation layer and a stress dielectric layer on the isolation layer in the opening; alternatively, forming a stressed dielectric layer and an isolation layer on the stressed dielectric layer in the opening; the compressive stress of the stress dielectric layer on the source-drain doped region is larger than that of the isolation layer on the source-drain doped region.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate comprising a device region and an isolation region; a device gate structure located on the substrate of the device region; the source-drain doped regions are positioned in the substrate at two sides of the grid structure of the device; the interlayer dielectric layer is positioned on the source-drain doped region; the stress dielectric layer is positioned on the substrate of the isolation region and between the source-drain doped regions; an isolation layer on the stressed dielectric layer; or, an isolation layer is positioned on the substrate of the isolation region and between the source-drain doped regions; a stress dielectric layer on the isolation layer; the compressive stress of the stress dielectric layer on the source-drain doped region is larger than that of the isolation layer on the source-drain doped region.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a substrate, which comprises a substrate, a grid structure positioned on the substrate, and source-drain doped regions positioned in the substrate at two sides of the grid structure; etching the substrate between the dummy gate structure and the source-drain doped region below the dummy gate structure to form an opening; a stressed dielectric layer is formed in the opening. The compressive stress of the stress dielectric layer on the source-drain doped region is larger than that of the isolation layer on the source-drain doped region, and compared with the situation that the stress dielectric layer is not filled in the opening, the stress dielectric layer in the opening is higher in hardness, and the deformation amount of the stress dielectric layer is smaller when the stress dielectric layer is extruded, so that the stress dielectric layer can generate compressive stress on the source-drain doped region, the source-drain doped region can provide stress for a channel below a device grid structure, carrier migration rate in the channel is improved, and the electrical performance of the semiconductor structure is improved.
Drawings
Fig. 1 and 2 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
fig. 3 to 9 are schematic structural views corresponding to steps in a first embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention;
fig. 10 and 11 are schematic structural views corresponding to steps in a second embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As can be seen from the background art, the devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed by combining a forming method of a semiconductor structure.
Fig. 1 and 2 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
As shown in fig. 1, a substrate is provided, and the substrate includes a substrate 1, a fin 5 on the substrate 1, a gate structure 2 crossing the fin 5, source-drain doped regions 3 in the fin 5 at two sides of the gate structure 2, and an interlayer dielectric layer 4 on the source-drain doped regions 3. Wherein the substrate 1 comprises a device region I and an isolation region II; the gate structure 2 located on the device region I serves as a device gate structure 21, and the gate structure 2 located on the isolation region II is a dummy gate structure 22.
As shown in fig. 2, the dummy gate structure 22 (shown in fig. 1) and the fin portion 5 and a portion of the thickness of the substrate 1 under the dummy gate structure 22 are etched to form an opening (not shown in the figure); after the openings are formed, a dielectric layer 6 is formed in the openings, and the dielectric layer 6 is used for realizing isolation between adjacent device regions I.
After the openings are formed, the openings expose the sidewalls of the source-drain doped regions 3, so that compressive stress of the fin 5 (shown in fig. 1) on the sidewalls of the source-drain doped regions 3 is released, and compressive stress of the corresponding source-drain doped regions 3 on the channel under the device gate structure 21 is reduced. A dielectric layer 6 is formed in the opening, the material of the dielectric layer 6 typically being silicon oxide. Compared with the original fin portion 5 material at the opening position, the silicon oxide has smaller hardness and loose structure, the dielectric layer 6 is larger in deformation quantity when being extruded, and the compressive stress on the source-drain doped region 3 is smaller, so that the compressive stress of the source-drain doped region 3 on a channel below the device gate structure 21 is reduced when the semiconductor structure works, the carrier migration rate in the channel is reduced, and the electrical property of the semiconductor structure is correspondingly poor.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a substrate, a grid structure positioned on the substrate and source-drain doped regions positioned in the substrate at two sides of the grid structure; etching the substrate between the dummy gate structure and the source-drain doped region below the dummy gate structure to form an opening; a stressed dielectric layer is formed in the opening. The compressive stress of the stress dielectric layer on the source-drain doped region is larger than that of the isolation layer on the source-drain doped region, and compared with the situation that the stress dielectric layer is not filled in the opening, the stress dielectric layer in the opening is higher in hardness, and the deformation amount of the stress dielectric layer is smaller when the stress dielectric layer is extruded, so that the stress dielectric layer can generate compressive stress on the source-drain doped region, the source-drain doped region can provide stress for a channel below a device grid structure, carrier migration rate in the channel is improved, and the electrical performance of the semiconductor structure is improved.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of specific embodiments of the present invention is provided below with reference to the accompanying drawings.
Fig. 3 to 9 are schematic structural views corresponding to each step in the first embodiment of the method for forming a semiconductor structure according to the embodiment of the present invention.
Referring to fig. 3, a base is provided, where the base includes a substrate 100, a gate structure 103 located on the substrate 100, source and drain doped regions 102 located in the substrate 100 at two sides of the gate structure 103, and an interlayer dielectric layer 104 located on the source and drain doped regions 102, where the interlayer dielectric layer 104 covers sidewalls of the gate structure 103; wherein the substrate 100 includes a device region I and an isolation region II, the gate structure 103 located on the device region I is used as a device gate structure 1031, and the gate structure 103 located on the isolation region II is a dummy gate structure 1032.
In this embodiment, the device region I is used to form a transistor, and the isolation region II is used to isolate the transistor.
The substrate provides a process basis for the subsequent formation of the semiconductor structure.
In this embodiment, the semiconductor structure is a fin field effect transistor (FinFET), and the substrate 100 is a substrate 100 with a fin 101. In other embodiments, the semiconductor structure may be a planar structure, and the base is a planar substrate.
In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate 100 may also have an interface layer formed on the surface thereof, and the interface layer may be made of silicon oxide, silicon nitride, silicon oxynitride, or the like.
In this embodiment, the material of the fin 101 is the same as the material of the substrate 100. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
The gate structure 103 is used to control the opening and closing of the channel during operation of the semiconductor structure.
The gate structure 103 spans across the fin 101, and the gate structure 103 covers portions of the sidewalls and top wall of the fin 101.
The gate structure 103 is a polysilicon gate structure or a metal gate structure. In this embodiment, the gate structure 103 is a polysilicon gate structure.
In this embodiment, the gate structure 103 is a stacked structure, and includes a gate oxide layer (not labeled in the figure) conformally covering a portion of the top surface and a portion of the sidewall of the fin 101, and a gate layer (not labeled in the figure) on the gate oxide layer. In other embodiments, the gate structure may also be a single layer structure, i.e., the gate structure includes only a gate layer.
In this embodiment, the gate oxide layer is made of silicon oxide. In other embodiments, the gate oxide layer may also be silicon oxynitride.
In this embodiment, the gate layer is made of polysilicon. In other embodiments, the material of the gate layer may also be amorphous carbon.
The source-drain doped region 102 is used to apply stress to the channel during operation of the semiconductor structure, thereby increasing the mobility of carriers in the channel.
Specifically, the source-drain doped region 102 is located in the fin 101 at two sides of the gate structure 103.
In this embodiment, the source-drain doped region 102 is used as a source and a drain of PMOS (Positive Channel Metal Oxide Semiconductor). In operation of the semiconductor structure, the source drain doped region 102 applies compressive stress (compression stress) to the channel under the device gate structure 1031, which can improve hole mobility.
Specifically, the source-drain doped region 102 is made of silicon germanium doped with P-type ions. In this embodiment, by doping P-type ions in the silicon germanium, the P-type ions replace the positions of silicon atoms in the crystal lattice, and the more P-type ions are doped, the higher the concentration of the polynomials is, and the stronger the conductivity is. Specifically, the P-type ions include one or more of B, ga and In.
The interlayer dielectric layer 104 is located on the source-drain doped region 102, and the interlayer dielectric layer 104 covers the sidewall of the gate structure 103, exposing the top of the gate structure 103.
The material of the interlayer dielectric layer 104 is an insulating material, and the interlayer dielectric layer 104 is used for realizing electrical isolation between adjacent transistors.
In this embodiment, the material of the interlayer dielectric layer 104 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer is one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
Referring to fig. 4 and 5, the dummy gate structure 1032 and the substrate 100 between the source and drain doped regions 102 under the dummy gate structure 1032 are etched to form an opening 105 (as shown in fig. 5).
Forming the opening 105, and providing space for forming an isolation layer and a stress dielectric layer in the opening 105 later; and because the isolation layer and the stress dielectric layer are both dielectric layers, the device region I can be isolated.
Specifically, the step of forming the opening 105 includes: forming a mask layer 106 exposing the dummy gate structure 1032; and etching the dummy gate structure 1032, the fin 101 under the dummy gate structure 1032 and the substrate 100 with a partial thickness by using the mask layer 106 as a mask to form an opening 105.
In this embodiment, in the process of etching to form the opening 105, the etched rate of the mask layer 106 is smaller than the etched rates of the dummy gate structure 1032, the fin 101, and the substrate 100.
Specifically, the material of the mask layer 106 includes one or more of silicon nitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the mask layer 106 is silicon nitride.
In this embodiment, the opening 105 is formed by a dry etching process. The dry etching process is an anisotropic etching process, has good etching profile controllability, is favorable for enabling the shape of the opening 105 to meet the process requirements, and can reduce damage to other film structures, so that the source-drain doped region 102 is not easy to etch by mistake in the etching process. In the dry etching, by changing the etching gas, the dummy gate structure 1032, the fin portion 101 under the dummy gate structure 1032, and the substrate 100 with a partial thickness can be etched in the same etching apparatus, simplifying the process steps.
The opening 105 should not be too deep or too shallow. If the openings 105 are too deep, it takes too much process time to form, and the structure composed of the device gate structure 1031, the interlayer dielectric layer 104 and the source-drain doped region 102 between the openings 105 is not stable enough, and is prone to tilting or collapse, so that the electrical performance of the semiconductor structure is poor. Forming an isolation layer and a stress dielectric layer in the opening 105 later, wherein if the opening 105 is too shallow, the isolation layer and the stress dielectric layer cannot isolate a depletion region formed by an adjacent source-drain doped region 102 when the semiconductor structure works, so that electric leakage of the semiconductor structure is easy to generate; and the stress dielectric layer formed in the opening 105 is located above the source-drain doped region 102, so that the compressive stress generated by the stress dielectric layer on the source-drain doped region 102 is low, and the source-drain doped region 102 is not easy to generate larger stress on a channel, and the migration rate of carriers is low. In this embodiment, the depth of the opening 105 is 2.5 times to 3 times the thickness of the source/drain doped region 102.
After forming the opening 105, the mask layer 106 is removed.
Specifically, the mask layer 106 is removed using a phosphoric acid solution.
Referring to fig. 6 to 9, an isolation layer 107 and a stressed dielectric layer 108 (shown in fig. 8) on the isolation layer 107 are formed in the opening 105 (shown in fig. 5); the compressive stress of the stress dielectric layer 108 on the source-drain doped region 102 is greater than the compressive stress of the isolation layer 107 on the source-drain doped region 102.
When the semiconductor structure works, the stress dielectric layer 108 located in the opening 105 has higher hardness, and the stress dielectric layer 108 has smaller deformation when being extruded, so that the stress dielectric layer 108 can generate compressive stress on the source-drain doped region 102, thereby enabling the source-drain doped region 102 to provide stress for a channel below the device gate structure 1031, further improving the carrier migration rate in the channel, and correspondingly improving the electrical performance of the semiconductor structure.
Specifically, the step of forming the isolation layer 107 and the stress dielectric layer 108 includes:
as shown in fig. 6, a spacer 107 is formed in the opening 105.
The stress dielectric layer 108 is made of a high stress material, and the isolation layer 107 makes the stress dielectric layer 108 not directly contact with the source-drain doped region 102 and the substrate 100, so that the stress dielectric layer 108 is not easy to crack or fall off, the formation quality of the stress dielectric layer 108 is improved, and accordingly, when the semiconductor structure works, the compressive stress of the stress dielectric layer 108 on the source-drain doped region 102 is facilitated to be enhanced, and the migration rate of carriers in a channel below the device gate structure 1031 is improved. In addition, the isolation layer 107 is further used to isolate the depletion layer adjacent to the source-drain doped region 102.
In this embodiment, the material of the isolation layer 107 is a dielectric material.
Specifically, the material of the isolation layer 107 includes silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the isolation layer 107; in addition, the dielectric constant of the silicon oxide is small, which is beneficial to isolating adjacent devices.
In this embodiment, the step of forming the isolation layer 107 includes: the isolation layer 107 is formed using a flow-through chemical vapor deposition process (Flowable Chemical Vapor Deposition, FCVD). The flowable chemical vapor deposition process has good filling capability, which is beneficial to reducing the probability of forming defects such as voids in the isolation layer 107. In other embodiments, the isolation layer may also be formed using an atomic layer deposition process (Atomic layer deposition, ALD). In other embodiments, a layer of isolation material (not shown) may also be formed in the opening; and etching back part of the isolation material layer to form an isolation layer.
Specifically, the process parameters for forming the isolation layer 107 include: the power is 200W to 1000W; the reaction gas comprises Dichlorosilane (DCS); the chamber pressure is 5Torr to 50Torr.
As shown in fig. 7, a stressed dielectric layer 108 is formed over the isolation layer 107 in the opening 105.
Compared with the case that the opening is not filled with the stress dielectric layer, the hardness of the stress dielectric layer 108 is higher, and the deformation amount of the stress dielectric layer 108 is smaller when the stress dielectric layer 108 is extruded, so that the stress dielectric layer 108 can generate compressive stress on the source-drain doped region 102, and the source-drain doped region 102 can provide stress for a channel below the device gate structure 1031, thereby improving the carrier migration rate in the channel and improving the electrical performance of the semiconductor structure.
Specifically, the material of the stressed dielectric layer 108 includes a silicon nitride or diamond-like carbon (DLC) film. In this embodiment, the material of the stress dielectric layer 108 includes silicon nitride, which has a high hardness, is a dielectric material with a common process and a low cost, has a high process compatibility, and is beneficial to reducing the process difficulty and the process cost of forming the stress dielectric layer 108.
In this embodiment, the stressed dielectric layer 108 is formed using a High Density Plasma Chemical Vapor Deposition (HDPCVD) process. The high-density plasma chemical vapor deposition process enables the deposition process to be applied to low temperature (250-450 ℃), and in the process, the deposition and etching can be synchronously performed in the same reaction chamber, so that the high-aspect-ratio gap filling capability, the good adhesion capability of a deposited film to a silicon wafer, the higher deposition rate, fewer deposition defects such as holes or pinholes and the like are realized, and the formation of the stress dielectric layer 108 is facilitated. In other embodiments, the stressed dielectric layer may also be formed using an atomic layer deposition process. The gap filling performance and the step coverage of the atomic layer deposition process are good, and the formation quality of the stress dielectric layer is improved.
In other embodiments, the step of forming the stressed dielectric layer may further comprise: forming a layer of stressed dielectric material (not shown) over the isolation layer; and removing the stress dielectric material layer exposing the opening, and taking the rest stress dielectric material layer in the opening as the stress dielectric layer.
Note that the distance d from the bottom of the stressed dielectric layer 108 to the top of the source/drain doped region 102 1 It is not desirable to either be too short or too long (as shown in FIG. 8). The material of the stress dielectric layer 108 is silicon nitride, and the filling performance of the silicon nitride is poor. If the distance d 1 Too long, the stress dielectric layer 108 is too thick, and holes are easy to exist in the formed stress dielectric layer 108, which increases the difficulty of forming the stress dielectric layer 108; and the stressed dielectric layer 108 on the sidewall of the source-drain doped region 102 is more likely to stress the source-drain doped region 102 if the distance d 1 Too long, too much of the stressed dielectric layer 108 is located under the source-drain doped region 102, and the compressive stress of the stressed dielectric layer 108 on the source-drain doped region 102 cannot be significantly increased, and the stress of the corresponding source-drain doped region 102 on the channel cannot be significantly increased. If the distance d 1 Too short, the stressed dielectric layer 108 may not be capable of generating a sufficient stress on the source-drain doped region 102, thereby making the source-drain doped region 102 less prone to generate a larger stress on the channel, and thus resulting in a lower carrier mobility. In this embodiment, the bottom of the stressed dielectric layer 108 is the same as the source/drainDistance d at the top of doped region 102 1 1 to 1.5 times the thickness of the source drain doped region 102.
Specifically, the process steps for forming the stressed dielectric layer 108 include: the power is 300W to 1500W; the reaction gas comprises ammonia and monosilane, or ammonia and silicon tetrachloride; the chamber pressure is 15Torr to 100Torr.
After the formation of the stressed dielectric layer 108, the stressed dielectric layer 108 is annealed by spike annealing. The annealing process makes the stressed dielectric layer 108 more dense, and the stressed dielectric layer 108 can generate larger stress on the source-drain doped region 102.
As shown in fig. 8, a portion of the stressed dielectric layer 108 is etched back to form a trench 109 over the stressed dielectric layer 108.
The trench 109 provides for the subsequent formation of a top buffer layer.
In this embodiment, the stressed dielectric layer 108 is etched by a dry etching process to form the trench 109. The dry etching process is an anisotropic etching process, has good etching profile control, ensures that the interlayer dielectric layer 104 is not easy to be etched by mistake in the etching process, and is beneficial to enabling the shape of the groove 109 to meet the process requirements. And the dry etching process is beneficial to precisely controlling the removal thickness of the material of the stress dielectric layer 108 and controlling the depth of the trench 109.
The trench 109 is preferably not too deep or too shallow. If the trench 109 is too deep, the compressive stress of the stressed dielectric layer 108 on the source-drain doped region 102 is easily weakened, so that the stress of the source-drain doped region 102 on the channel is weakened, and the migration rate of carriers is low when the semiconductor structure works. The method for forming the semiconductor structure further comprises the following steps: etching the interlayer dielectric layer 104 to form a groove (not shown in the figure) exposing the source-drain doped region 102; after the grooves are formed, filling conductive materials in the grooves to form contact hole plugs, wherein the cross sections of the grooves are inverted trapezoids due to the loading effect in the etching process, and the distance from the tops of the corresponding contact hole plugs to the stress dielectric layer 108 is smaller than the distance from the bottoms of the contact hole plugs to the stress dielectric layer 108; if the trench 109 is too shallow, the top of the stressed dielectric layer 108 has too high compressive stress on the subsequently formed contact hole plug, and the contact hole plug is prone to crack or dislocation, which leads to the situation that the contact hole plug has leakage current on the one hand; on the other hand, when the semiconductor structure works, the crack or dislocation of the contact hole plug is easy to generate excessive heat, so that the performance of the semiconductor structure is poor. In summary, the shallow depth of the trench 109 tends to result in a semiconductor structure having low electrical performance. In this embodiment, the depth of the trench 109 is 3 nm to 10 nm.
After forming the trench 109, a top buffer layer 110 is formed in the trench 109, as shown in fig. 9.
The top buffer layer 110 in the trench 109 serves to relieve the compressive stress between the stressed dielectric layer 108 and a subsequently formed contact plug.
The depth of the trench 109 is 3 nm to 10 nm, and correspondingly, the thickness of the top buffer layer 110 is 3 nm to 10 nm.
In this embodiment, the material of the top buffer layer 110 includes silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the top buffer layer 110; in addition, the dielectric constant of the silicon oxide is small, which is beneficial to isolating adjacent devices.
In this embodiment, the top buffer layer 110 is formed by a flow-through chemical vapor deposition process. The flowable chemical vapor deposition process has good filling capability, is beneficial to reducing the probability of forming defects such as cavities in the top buffer layer 110, and improves the film forming quality of the top buffer layer 110. In other embodiments, the top buffer layer may also be formed using an atomic layer deposition process.
In the process of forming the top buffer layer 110, a back-end dielectric layer 111 is further formed on the device gate structure 1031 and the interlayer dielectric layer 104.
The material and the forming process of the back-end dielectric layer 111 are the same as those of the top buffer layer 110, and will not be described here again.
Fig. 10 and 11 are schematic structural views corresponding to steps after each step in the second embodiment of the method for forming a semiconductor structure according to the present invention.
The embodiment of the present invention is the same as the previous embodiment, and is not repeated herein, but the difference between the present invention and the previous embodiment is that the stress dielectric layer 208 and the isolation layer 207 in the opening 205 are formed in different sequences.
Referring to fig. 10, a stressed dielectric layer 208 is formed in the opening 205.
In this embodiment, the stress dielectric layer 208 is located at the middle lower portion of the sidewall of the source-drain doped region 202, and the stress dielectric layer 208 applies a compressive stress to the middle lower portion of the source-drain doped region 202, so that the source-drain doped region 202 can provide stress to the middle lower portion of the channel, thereby improving the carrier migration rate of the middle lower portion of the channel and improving the electrical performance of the semiconductor structure.
And the subsequent method for forming the semiconductor structure further comprises the following steps: etching the interlayer dielectric layer 204 to form a groove (not shown) exposing the source-drain doped region 202; after the groove is formed, a conductive material is filled in the groove to form a contact hole plug, the cross section of the groove is inverted trapezoid due to a loading effect in an etching process, the distance from the top of the corresponding contact hole plug to the stress dielectric layer 208 is smaller than the distance from the bottom of the contact hole plug to the stress dielectric layer 208, the distance from the stress dielectric layer 208 to the contact hole plug is far, and the stress dielectric layer 208 does not generate excessive compressive stress on the contact hole plug, so that the contact hole plug is not easy to break or misplacement, and the electrical property of the semiconductor structure is improved.
Specifically, the material of the stressed dielectric layer 208 includes a silicon nitride or diamond-like film. In this embodiment, the material of the stress dielectric layer 208 includes silicon nitride, which has a higher hardness, is a dielectric material with a common process and a lower cost, has a higher process compatibility, and is beneficial to reducing the process difficulty and the process cost of forming the stress dielectric layer 208.
The formation method of the stressed dielectric layer 208 is as described in the first embodiment, and is not described herein. In other embodiments, the step of forming the stressed dielectric layer may further include: forming a layer of stressed dielectric material (not shown) in the opening; and etching back part of the stress dielectric material layer, wherein the rest stress dielectric material layer in the opening is used as the stress dielectric layer.
After forming the stressed dielectric layer 208, the stressed dielectric layer 208 is annealed. The specific description refers to the first embodiment, and will not be repeated here.
Note that the distance d from the top of the stressed dielectric layer 208 to the top of the source/drain doped region 202 2 Neither too short nor too long is desirable. If the distance d 2 Too long results in too small a thickness of the stressed dielectric layer 208 on the sidewall of the source-drain doped region 202, which tends to cause a smaller compressive stress applied by the stressed dielectric layer 208 to the middle-lower portion of the source-drain doped region 202, so that the source-drain doped region 202 provides a smaller stress to the middle-lower portion of the channel, and thus the migration rate of carriers in the channel is not easily significantly improved. If the distance d 2 Too small, that is, the distance between the stress dielectric layer 208 and the bottom of the subsequently formed contact hole plug is small, which results in too large stress generated by the stress dielectric layer 208 on the contact hole plug, and the contact hole plug is easy to crack or misplace, on the one hand, resulting in the situation that the contact hole plug has leakage current; on the other hand, when the semiconductor structure works, the crack or dislocation of the contact hole plug is easy to generate excessive heat, so that the performance of the semiconductor structure is poor. In combination, if the distance d 2 Too small, tends to result in a semiconductor structure having lower electrical properties. In this embodiment, the distance d from the top of the stressed dielectric layer 208 to the top of the source/drain doped region 202 2 0.4 to 1 times the thickness of the source drain doped region 202.
It should be noted that the stressed dielectric layer 208 is not too thin. If the stress dielectric layer 208 is too thick, that is, a region of the stress dielectric layer 208 that is more is located below the source-drain doped region 202, the compressive stress of the stress dielectric layer 208 located below the source-drain doped region 202 on the source-drain doped region 202 is smaller, so that the stress provided by the source-drain doped region 202 to the channel is smaller, and the carrier mobility in the channel cannot be significantly improved. If the stressed dielectric layer 208 is too thin, the compressive stress of the stressed dielectric layer 208 on the middle and lower portions of the source-drain doped region 202 is too small, so that the compressive stress of the source-drain doped region 202 on the middle and lower portions of the channel is too small, and the carrier mobility in the channel cannot be significantly improved. In this embodiment, the thickness of the stressed dielectric layer 208 is 1 to 1.5 times the thickness of the source/drain doped region 202.
It should be noted that the method for forming the semiconductor structure includes: after forming the opening 205, an opening buffer layer 209 is formed on the sidewall and bottom of the opening 205 before forming the stressed dielectric layer 208.
The material of the stress dielectric layer 208 has a large difference in thermal expansion coefficient from the material of the substrate 200, and if the stress dielectric layer 208 is directly formed on the substrate 200, the stress dielectric layer 208 is easily cracked or even falls off, so that the stress cannot be applied to the source-drain doped region 202, and therefore, an opening buffer layer 209 is formed between the stress dielectric layer 208 and the substrate 200, and the opening buffer layer 209 plays a role in buffering stress.
In this embodiment, the opening buffer layer 209 is formed by an atomic layer deposition process. The atomic layer deposition process includes performing multiple atomic layer deposition cycles, so that the thickness of the open buffer layer 209 has better thickness uniformity, and the thickness of the open buffer layer 209 can be precisely controlled; in addition, the gap filling performance and the step coverage performance of the atomic layer deposition process are good, and the conformal coverage capability of the opened buffer layer 209 is correspondingly improved. In other embodiments, the open buffer layer may also be formed using a chemical vapor deposition process.
In this embodiment, the material of the opening buffer layer 209 is silicon oxide.
Referring to fig. 11, an isolation layer 207 is formed in the opening 205 on the stressed dielectric layer 208.
The isolation layer 207 is used to isolate adjacent source-drain doped regions 202.
In this embodiment, the material of the isolation layer 207 is a dielectric material.
Specifically, the material of the isolation layer 207 includes silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the isolation layer 207; in addition, the dielectric constant of the silicon oxide is small, which is beneficial to isolating adjacent devices.
In this embodiment, the isolation layer 207 is formed by a flow-type chemical vapor deposition process. The flowable chemical vapor deposition process has good filling capability, which is beneficial to reducing the probability of forming defects such as cavities in the isolation layer 207 and correspondingly improving the film forming quality of the isolation layer 207. In other embodiments, the isolation layer may also be formed using an atomic layer deposition process.
The isolation layer 207 is further formed on the interlayer dielectric layer 204 and the device gate structure 2031.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 9, a schematic structural diagram of a first embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100, the substrate 100 comprising a device region I and an isolation region II; a device gate structure 1031 located on the substrate 100 of the device region I; source-drain doped regions 102 located in the substrate 100 at two sides of the device gate structure 1031; an interlayer dielectric layer located on the source-drain doped region 102; an isolation layer 107 located on the substrate 100 of the isolation region II and located between the source-drain doped regions 102; a stressed dielectric layer 108 on said isolation layer 107; the compressive stress of the stress dielectric layer 108 on the source-drain doped region 102 is greater than the compressive stress of the isolation layer 107 on the source-drain doped region 102.
Compared with the situation that the stress dielectric layer is not formed on the substrate in the isolation region II, the hardness of the stress dielectric layer 108 on the substrate 100 is higher, and the deformation amount of the stress dielectric layer 108 is smaller when the stress dielectric layer 108 is extruded, so that the stress dielectric layer 108 can generate compressive stress on the source-drain doped region 102, and the source-drain doped region 102 can provide stress for a channel under a device gate structure, thereby improving the carrier migration rate in the channel and improving the electrical performance of the semiconductor structure.
In this embodiment, the device region I is used to form a transistor, and the isolation region II is used to isolate the transistor.
The substrate provides a process basis for the subsequent formation of the semiconductor structure.
In this embodiment, the semiconductor structure is exemplified by a fin field effect transistor (FinFET), and the substrate 100 is a substrate 100 having a fin 101. In other embodiments, the semiconductor structure may also be a planar structure, and accordingly, the base is a planar substrate.
In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate 100 may also have an interface layer formed on the surface thereof, and the interface layer may be made of silicon oxide, silicon nitride, silicon oxynitride, or the like.
In this embodiment, the material of the fin 101 is the same as the material of the substrate 100. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
The device gate structure 1031 is used to control the opening and closing of the channel during operation of the semiconductor structure.
The device gate structure 1031 spans across the fin 101, and the device gate structure 1031 covers portions of the sidewalls and top wall of the fin 101.
The device gate structure 1031 is a polysilicon gate structure or a metal gate structure. In this embodiment, the device gate structure 1031 is a polysilicon gate structure.
In this embodiment, the device gate structure 1031 is a stacked structure, and includes a gate oxide layer (not labeled in the drawing) conformally covering a portion of the top surface and a portion of the sidewall of the fin 101, and a gate layer on the gate oxide layer. In other embodiments, the device gate structure may also be a single layer structure, i.e., the device gate structure includes only a gate layer.
In this embodiment, the gate oxide layer is made of silicon oxide. In other embodiments, the gate oxide layer may also be silicon oxynitride.
In this embodiment, the gate layer is made of polysilicon. In other embodiments, the material of the gate layer may also be amorphous carbon.
The source-drain doped region 102 is used to apply stress to the channel during operation of the semiconductor structure, thereby increasing the mobility of carriers in the channel.
Specifically, the source-drain doped regions 102 are located in the fin 101 at two sides of the device gate structure 1031.
In this embodiment, the source-drain doped region 102 is used as a source and a drain of PMOS (Positive Channel Metal Oxide Semiconductor). In operation of the semiconductor structure, the source drain doped region 102 applies compressive stress (compression stress) to the channel under the device gate structure 1031, which can improve hole mobility.
Specifically, the source-drain doped region 102 is made of silicon germanium doped with P-type ions. In this embodiment, by doping P-type ions in the silicon germanium, the P-type ions replace the positions of silicon atoms in the crystal lattice, and the more P-type ions are doped, the higher the concentration of the polynomials is, and the stronger the conductivity is. Specifically, the P-type ions include one or more of B, ga and In.
The interlayer dielectric layer 104 is located on the source-drain doped region 102, and the interlayer dielectric layer 104 covers the sidewall of the device gate structure 1031, exposing the top of the device gate structure 1031.
The material of the interlayer dielectric layer 104 is an insulating material, and the interlayer dielectric layer 104 is used for realizing electrical isolation between adjacent transistors.
In this embodiment, the material of the interlayer dielectric layer 104 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer is one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
In this embodiment, the isolation layer 107 and the stress dielectric layer 108 are both dielectric layers, which can isolate the device region I.
The stress dielectric layer 108 is made of a high stress material, and the isolation layer 107 makes the stress dielectric layer 108 not directly contact with the source-drain doped region 102 and the substrate 100, so that the stress dielectric layer 108 is not easy to crack or fall off, and the formation quality of the stress dielectric layer 108 is improved. In operation of the semiconductor structure, the compressive stress of the stressed dielectric layer 108 on the source-drain doped region 102 is advantageously enhanced to increase the carrier mobility in the channel under the device gate structure 1031. In addition, the isolation layer 107 is further used to isolate the depletion layer adjacent to the source-drain doped region 102.
In this embodiment, the material of the isolation layer 107 is a dielectric material.
Specifically, the material of the isolation layer 107 includes silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the isolation layer 107; in addition, the dielectric constant of the silicon oxide is small, which is beneficial to isolating adjacent devices.
When the semiconductor structure works, the stress dielectric layer 108 on the substrate 100 has higher hardness, and the stress dielectric layer 108 has smaller deformation when being extruded, so that the stress dielectric layer 108 can generate compressive stress on the source-drain doped region 102, and the source-drain doped region 102 can provide stress for a channel below the device gate structure 1031, thereby improving the carrier migration rate in the channel and improving the electrical performance of the semiconductor structure.
Specifically, the material of the stressed dielectric layer 108 includes a silicon nitride or diamond-like film. In this embodiment, the material of the stress dielectric layer 108 includes silicon nitride, which has a higher hardness, is a dielectric material with a common process and a lower cost, has a higher process compatibility, and is beneficial to reducing the process difficulty and the process cost of forming the stress dielectric layer 108.
Note that the distance d from the bottom of the stressed dielectric layer 108 to the top of the source/drain doped region 102 1 Neither too short nor too long is desirable. The material of the stress dielectric layer 108 is silicon nitride, and the filling performance of the silicon nitride is poor. If the distance d 1 Too long, the stress dielectric layer 108 is too thick, and holes are easily formed in the stress dielectric layer 108, which increases the difficulty of forming the stress dielectric layer 108; and the stressed dielectric layer 108 on the sidewall of the source-drain doped region 102 is more likely to stress the source-drain doped region 102 if the distance d 1 Too long, too much of the stressed dielectric layer 108 is located under the source-drain doped region 102, and the compressive stress of the stressed dielectric layer 108 on the source-drain doped region 102 cannot be significantly increased, and the stress of the corresponding source-drain doped region 102 on the channel cannot be significantly increased. If the distance d 1 Too short, the stressed dielectric layer 108 may not be capable of generating a sufficient stress on the source-drain doped region 102, thereby making the source-drain doped region 102 less prone to generate a larger stress on the channel, and thus resulting in a lower carrier mobility. In this embodiment, the distance d from the bottom of the stressed dielectric layer 108 to the top of the source/drain doped region 102 1 1 to 1.5 times the thickness of the source drain doped region 102.
The semiconductor structure further includes: a top buffer layer 110 is located on top of the stressed dielectric layer 108.
The top buffer layer 110 is used to relieve the compressive stress between the stressed dielectric layer 108 and subsequently formed contact plugs.
In this embodiment, the material of the top buffer layer 110 includes silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the top buffer layer 110; in addition, the dielectric constant of the silicon oxide is small, which is beneficial to isolating adjacent devices.
It should be noted that the top buffer layer 110 is not too thick or too thin. If the top buffer layer 110 is too thick, the compressive stress of the stressed dielectric layer 108 on the source-drain doped region 102 is easily weakened, so that the stress of the source-drain doped region 102 on the channel is weakened, and the migration rate of carriers is lower when the semiconductor structure works. Forming a contact hole plug in the interlayer dielectric layer 104, wherein the distance from the top of the contact hole plug to the stress dielectric layer 108 is smaller than the distance from the bottom of the contact hole plug to the stress dielectric layer 108; if the top buffer layer 110 is too thin, that is, the distance between the top of the stressed dielectric layer 108 and the contact hole plug is too short, the compressive stress of the top of the stressed dielectric layer 108 on the contact hole plug is easily excessive, and a crack or dislocation is easily generated in the contact hole plug, which on the one hand leads to the situation that the contact hole plug has leakage current; on the other hand, when the semiconductor structure works, the crack or dislocation of the contact hole plug is easy to generate excessive heat, so that the performance of the semiconductor structure is poor. In summary, the shallow depth of the trench 109 tends to result in a semiconductor structure having low electrical performance. In this embodiment, the thickness of the top buffer layer 110 is 3 nm to 10 nm.
It should be noted that the semiconductor structure further includes: a back end dielectric layer 111 is located on the device gate structure 1031 and on the interlayer dielectric layer 104.
The material of the back-end dielectric layer 111 is the same as that of the top buffer layer 110, and will not be described here.
In this embodiment, the total thickness of the isolation layer 107 and the stress dielectric layer 108 is not too large or too small. If the total thickness is too large, it takes too much process time to form the isolation layer 107 and the stress dielectric layer 108, and in the process of forming the semiconductor structure, the structure composed of the device gate structure 1031, the interlayer dielectric layer 104 and the source-drain doped region 102 between the openings 105 is easily unstable, and is easily tilted or collapsed, so that the electrical performance of the semiconductor structure is poor. If the total thickness is too small, the isolation layer 107 and the stress dielectric layer 108 cannot isolate the depletion region formed in the adjacent source-drain doped region 102 when the semiconductor structure works, so that the semiconductor structure is easy to generate electric leakage; and the stress dielectric layer 108 is easily located above the source-drain doped region 102, so that the stress dielectric layer 108 generates lower compressive stress on the source-drain doped region 102, and thus the source-drain doped region 102 is not easily stressed on a channel, and further the migration rate of carriers is lower. In this embodiment, the total thickness of the isolation layer 107 and the stress dielectric layer 108 is 2.5 to 3 times that of the source/drain doped region 102.
Referring to fig. 11, a schematic structural diagram of a second embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure of the embodiment of the present invention is the same as the first semiconductor structure, and the difference between the semiconductor structure of the embodiment of the present invention and the first semiconductor structure is that: a stressed dielectric layer 208 on the substrate 200 in the isolation region II and between the source and drain doped regions 202; an isolation layer 207 is located on the stressed dielectric layer 208.
In this embodiment, the stress dielectric layer 208 is located at the middle lower portion of the sidewall of the source-drain doped region 202, and the stress dielectric layer 208 applies a compressive stress to the middle lower portion of the source-drain doped region 202, so that the source-drain doped region 202 can provide stress to the middle lower portion of the channel, thereby improving the carrier migration rate of the middle lower portion of the channel and improving the electrical performance of the semiconductor structure.
And a contact hole plug is formed in the interlayer dielectric layer 204 and is in contact with the source-drain doped region 202, wherein the distance from the top of the contact hole plug to the stress dielectric layer 208 is smaller than the distance from the bottom of the contact hole plug to the stress dielectric layer 208, and because the stress dielectric layer 208 is positioned at the middle lower part of the side wall of the source-drain doped region 202, the distance from the stress dielectric layer 208 to the contact hole plug is far, the stress dielectric layer 208 cannot generate excessive compressive stress on the contact hole plug, so that the contact hole plug is not easy to break or misplace, and the electrical property of the semiconductor structure is improved.
Note that the distance d from the top of the stressed dielectric layer 208 to the top of the source/drain doped region 202 2 Neither too short nor too long is desirable. If the distance d 2 Too long, resulting in the strain on the sidewalls of the source drain doped region 202The thickness of the stress dielectric layer 208 is too small, which tends to cause the compressive stress applied by the stress dielectric layer 208 to the middle and lower portions of the source-drain doped region 202 to be smaller, so that the source-drain doped region 202 provides a smaller stress to the middle and lower portions of the channel, and further, the migration rate of carriers in the channel is not easy to be significantly improved. If the distance d 2 Too small, that is, the distance between the stress dielectric layer 208 and the bottom of the subsequently formed contact hole plug is small, which results in too large stress generated by the stress dielectric layer 208 on the contact hole plug, and the contact hole plug is easy to crack or misplace, on the one hand, resulting in the situation that the contact hole plug has leakage current; on the other hand, when the semiconductor structure works, the crack or dislocation of the contact hole plug is easy to generate excessive heat, so that the performance of the semiconductor structure is poor. In combination, if the distance d 2 Too small, tends to result in a semiconductor structure having lower electrical properties. In this embodiment, the distance d from the top of the stressed dielectric layer 208 to the top of the source/drain doped region 202 2 0.4 to 1 times the thickness of the source drain doped region 202.
It should be noted that the stressed dielectric layer 208 is not too thin. If the stressed dielectric layer 208 is too thick, that is, a region of the stressed dielectric layer 208 that is more than the region of the stressed dielectric layer 208 is located below the source-drain doped region 202, the stressed dielectric layer 208 located below the source-drain doped region 202 has a smaller compressive stress on the source-drain doped region 202, so that the source-drain doped region 202 can provide a smaller stress to the channel, which results in a failure to significantly increase the carrier mobility in the channel. If the stressed dielectric layer 208 is too thin, the compressive stress of the stressed dielectric layer 208 on the lower middle portion of the source-drain doped region 202 is too small, so that the compressive stress of the source-drain doped region 202 on the lower middle portion of the channel is too small, and the carrier mobility in the channel cannot be significantly improved. In this embodiment, the thickness of the stressed dielectric layer 208 is 1 to 1.5 times the thickness of the source/drain doped region 202.
The semiconductor structure includes: an isolation layer 207 is located on the stressed dielectric layer 208.
The isolation layer 207 is used to isolate adjacent source-drain doped regions 202.
In this embodiment, the material of the isolation layer 207 is a dielectric material.
Specifically, the material of the isolation layer 207 includes silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the isolation layer 207; in addition, the dielectric constant of the silicon oxide is small, which is beneficial to isolating adjacent devices.
The isolation layer 207 is further located on the interlayer dielectric layer 204 and the device gate structure 2031.
It should be noted that the semiconductor structure further includes: an opening buffer layer 209 is located between the stressed dielectric layer 208 and the substrate 200, and between the stressed dielectric layer 208 and the source drain doped region 202.
The material of the stressed dielectric layer 208 has a relatively large difference in thermal expansion coefficient from the material of the substrate 200, and if the stressed dielectric layer 208 is directly located on the substrate 200, the stressed dielectric layer 208 is prone to crack or even fall off, so that the stress applied to the source-drain doped region 202 cannot be exerted, and therefore, the opening buffer layer 209 plays a role in buffering stress.
In this embodiment, the material of the opening buffer layer 209 is silicon oxide.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the invention, and the scope of the embodiments of the invention should be pointed out in the appended claims.
Claims (20)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate, a gate structure positioned on the substrate, source and drain doped regions positioned in the substrate at two sides of the gate structure, and an interlayer dielectric layer positioned on the source and drain doped regions; the substrate comprises a device region and an isolation region, wherein the gate structure positioned on the device region is used as a device gate structure, and the gate structure positioned on the isolation region is a pseudo gate structure;
etching the substrate between the dummy gate structure and the source-drain doped region below the dummy gate structure to form an opening;
forming an isolation layer and a stress dielectric layer on the isolation layer in the opening, wherein the bottom of the stress dielectric layer is lower than the top of the source-drain doped region; or forming a stress dielectric layer and an isolation layer on the stress dielectric layer in the opening, wherein the top of the stress dielectric layer is higher than the bottom of the source-drain doped region; the compressive stress of the stress dielectric layer on the source-drain doped region is larger than that of the isolation layer on the source-drain doped region.
2. The method of forming a semiconductor structure of claim 1, wherein after forming the isolation layer, forming a stressed dielectric layer on the isolation layer;
the forming of the stress dielectric layer further comprises: etching back part of the stress dielectric layer with the thickness, and forming a groove on the stress dielectric layer; after forming the trench, a top buffer layer is formed in the trench.
3. The method of forming a semiconductor structure of claim 1, wherein after forming the stressed dielectric layer, forming an isolation layer over the stressed dielectric layer;
the method for forming the semiconductor structure further comprises the following steps: and after the opening is formed, forming an opening buffer layer in the opening before forming the stress dielectric layer.
4. The method of forming a semiconductor structure of claim 1, wherein after forming the isolation layer, forming a stressed dielectric layer on the isolation layer;
the distance from the bottom of the stress dielectric layer to the top of the source-drain doped region is 1 to 1.5 times the thickness of the source-drain doped region.
5. The method of forming a semiconductor structure of claim 1, wherein after forming the stressed dielectric layer, forming an isolation layer over the stressed dielectric layer;
The distance from the top of the stress dielectric layer to the top of the source-drain doped region is 0.4 to 1 time of the thickness of the source-drain doped region;
the thickness of the stress dielectric layer is 1 to 1.5 times of that of the source-drain doped region.
6. The method of forming a semiconductor structure as claimed in any one of claims 1 to 5, wherein the stressed dielectric layer is formed using a high density plasma chemical vapor deposition process or an atomic layer deposition process.
7. The method of forming a semiconductor structure of any one of claims 1 to 5, wherein the material of the stressed dielectric layer comprises one or both of silicon nitride and a diamond-like film.
8. The method of forming a semiconductor structure according to any one of claims 1 to 5, wherein the isolation layer is formed using an atomic layer vapor deposition or a flow chemical vapor deposition process.
9. The method of forming a semiconductor structure of any one of claims 1 to 5, wherein the material of the isolation layer comprises silicon oxide.
10. The method of forming a semiconductor structure of any of claims 1-5, wherein the substrate is a substrate having a fin, the gate structure spans the fin, and the gate structure covers portions of a top wall and sidewalls of the fin;
The source-drain doped regions are positioned in the fin parts at two sides of the grid structure;
etching the substrate between the dummy gate structure and a source-drain doped region below the dummy gate structure, and forming an opening comprises the steps of: and etching the dummy gate structure, the fin portion positioned below the dummy gate structure and the substrate with partial thickness to form the opening.
11. The method of forming a semiconductor structure of claim 2, wherein the trench has a depth of 3 nm to 10 nm.
12. A semiconductor structure, comprising:
a substrate comprising a device region and an isolation region;
a device gate structure located on the substrate of the device region;
the source-drain doped regions are positioned in the substrate at two sides of the grid structure of the device;
the interlayer dielectric layer is positioned on the source-drain doped region;
the stress dielectric layer is positioned on the substrate of the isolation region and between the source-drain doped regions; the isolation layer is positioned on the stress dielectric layer, and the top of the stress dielectric layer is higher than the bottom of the source-drain doped region; or, an isolation layer is positioned on the substrate of the isolation region and between the source-drain doped regions; the stress dielectric layer is positioned on the isolation layer, and the bottom of the stress dielectric layer is lower than the top of the source-drain doped region; the compressive stress of the stress dielectric layer on the source-drain doped region is larger than that of the isolation layer on the source-drain doped region.
13. The semiconductor structure of claim 12, wherein the stressed dielectric layer is located on the isolation layer;
the distance from the bottom of the stress dielectric layer to the top of the source-drain doped region is 1 to 1.5 times the thickness of the source-drain doped region.
14. The semiconductor structure of claim 12, wherein the stressed dielectric layer is located on the isolation layer;
the semiconductor structure further includes: and the top buffer layer is positioned on top of the stress dielectric layer.
15. The semiconductor structure of claim 12, wherein the stressed dielectric layer is located below the isolation layer;
the distance from the top of the stress dielectric layer to the top of the source-drain doped region is 0.4 to 1 time the thickness of the source-drain doped region;
the thickness of the stress dielectric layer is 1 to 1.5 times of that of the source-drain doped region.
16. The semiconductor structure of any one of claims 12 to 15, wherein the material of the stressed dielectric layer comprises one or both of silicon nitride and a diamond-like film.
17. The semiconductor structure of any one of claims 12-15, wherein the material of the isolation layer comprises silicon oxide.
18. The semiconductor structure of any of claims 12-15, wherein the substrate is a substrate having a fin, the gate structure spans the fin, and the gate structure covers portions of a top wall and sidewalls of the fin;
the source-drain doped region is located in the fin portions at two sides of the gate structure.
19. The semiconductor structure of claim 14, wherein the top buffer layer has a thickness of 3 nm to 10 nm.
20. The semiconductor structure of claim 15, wherein the semiconductor structure further comprises: and the opening buffer layer is positioned between the substrate and the stress dielectric layer and between the source-drain doped region and the stress dielectric layer.
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