CN111613582B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN111613582B
CN111613582B CN201910134224.4A CN201910134224A CN111613582B CN 111613582 B CN111613582 B CN 111613582B CN 201910134224 A CN201910134224 A CN 201910134224A CN 111613582 B CN111613582 B CN 111613582B
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fin
forming
isolation
pseudo
fin portion
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CN111613582A (en
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein the substrate comprises a substrate and a pseudo fin part positioned on the substrate; forming an isolation layer on the substrate exposed by the pseudo fin part, wherein the isolation layer covers part of the side wall of the pseudo fin part; forming a fin portion on the isolation layer exposed by the pseudo fin portion; removing the pseudo fin portion after forming the fin portion; and after the pseudo fin part is removed, forming an isolation structure on the substrate exposed out of the fin part, wherein the isolation structure covers part of the side wall of the fin part. After a gate structure which spans the fin portion and covers part of the top surface and part of the side wall of the fin portion is formed subsequently, the gate structure can directly control part of the fin portion covered by the gate structure, part of the fin portion in the isolation structure is not covered by the gate structure and is not easy to be directly controlled by the gate structure.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate structure on the channel is further and further reduced, and the difficulty of pinching off (pin off) the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely so-called short-channel effects (SCE), is more likely to occur.
Accordingly, to better accommodate the reduction in feature sizes, semiconductor processes are increasingly beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) from at least two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit short channel effect; and finfets have better compatibility with existing integrated circuit fabrication than other devices.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and optimizes the electrical performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and a pseudo fin part positioned on the substrate; forming an isolation layer on the substrate exposed by the pseudo fin portion, wherein the isolation layer covers part of the side wall of the pseudo fin portion; forming a fin portion on the isolation layer exposed by the pseudo fin portion; removing the pseudo fin portion after forming the fin portion; and after the pseudo fin portion is removed, forming an isolation structure on the substrate exposed out of the fin portion, wherein the isolation structure covers part of the side wall of the fin portion.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate; an isolation layer discrete on the substrate; the fin part is positioned on the isolation layer; and the isolation structure is positioned on the substrate exposed by the fin part and covers part of the side wall of the fin part.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a substrate, which comprises a substrate and a pseudo fin part positioned on the substrate; forming an isolation layer on the substrate exposed by the pseudo fin portion, wherein the isolation layer covers part of the side wall of the pseudo fin portion; forming a fin portion on the isolation layer exposed by the pseudo fin portion; removing the pseudo fin portion after forming the fin portion; and forming an isolation structure on the substrate exposed by the fin part, wherein the isolation structure covers part of the side wall of the fin part. After a gate structure which spans the fin portion and covers part of the top surface and part of the side wall of the fin portion is formed subsequently, the gate structure can directly control part of the fin portion covered by the gate structure, part of the fin portion in the isolation structure is not covered by the gate structure, the fin portion in the isolation structure is not easy to directly control by the gate structure, electric leakage easily occurs between the fin portion in the isolation structure and the substrate, and because the fin portion is formed on the isolation layer, the isolation layer electrically isolates the fin portion from the substrate, electric leakage is not easy to occur to the fin portion in the isolation structure, and the electrical performance of the semiconductor structure is optimized.
Drawings
Fig. 1 to 5 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
fig. 6 to 15 are schematic structural views corresponding to steps in the first embodiment of the method for forming a semiconductor structure according to the embodiment of the present invention;
fig. 16 to 19 are schematic structural views corresponding to steps in a second embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As can be seen from the background art, the devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed by combining a forming method of a semiconductor structure.
Referring to fig. 1 to 5, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, a base is provided, the base comprising a substrate 10 and a fin 11 located on the substrate 10.
Referring to fig. 2, an isolation material layer 12 is formed on the substrate 10 where the fin 11 (shown in fig. 1) is exposed; after the isolation material layer 12 is formed, part of the fin 11 is removed to form a groove 13.
Referring to fig. 3, a fill fin 14 is formed in the recess 13 (shown in fig. 2).
Referring to fig. 4, a portion of the thickness of the isolation material layer 12 is removed, forming an isolation layer 15 exposing a portion of the thickness of the fill fin 14.
Referring to fig. 5, a gate structure 16 is formed across the fill fin 14, the gate structure 16 covering a portion of the top wall and a portion of the sidewalls of the fill fin 14.
It should be noted that, the material of the filling fin 14 is silicon, and the material of the filling fin 14 is SiGe, which is capable of improving carrier mobility compared to Si, so that more and more materials of the channel region are changed from Si to SiGe, but because in the semiconductor structure, only the part of the filling fin 14 located above the isolation layer 15 is directly controlled by the gate structure 16, the filling fin 14 in the isolation layer 15 is not easily directly controlled by the gate structure 16, and when the carrier mobility in the channel region increases, carriers flowing in the filling fin 14 in the isolation layer 15 are likely to cause punch-through, resulting in poor electrical performance of the semiconductor structure.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and a pseudo fin part positioned on the substrate; forming an isolation layer on the substrate exposed by the pseudo fin portion, wherein the isolation layer covers part of the side wall of the pseudo fin portion; forming a fin portion on the isolation layer exposed by the pseudo fin portion; removing the pseudo fin portion after forming the fin portion; and after the pseudo fin portion is removed, forming an isolation structure on the substrate exposed out of the fin portion, wherein the isolation structure covers part of the side wall of the fin portion.
The embodiment of the invention provides a substrate, which comprises a substrate and a pseudo fin part positioned on the substrate; forming an isolation layer on the substrate exposed by the pseudo fin portion, wherein the isolation layer covers part of the side wall of the pseudo fin portion; forming a fin portion on the isolation layer exposed by the pseudo fin portion; removing the pseudo fin portion after forming the fin portion; and forming an isolation structure on the substrate exposed by the fin part, wherein the isolation structure covers part of the side wall of the fin part. After a gate structure which spans the fin portion and covers part of the top surface and part of the side wall of the fin portion is formed subsequently, the gate structure can directly control part of the fin portion covered by the gate structure, part of the fin portion in the isolation structure is not covered by the gate structure, the fin portion in the isolation structure is not easy to directly control by the gate structure, electric leakage easily occurs between the fin portion in the isolation structure and the substrate, and because the fin portion is formed on the isolation layer, the isolation layer electrically isolates the fin portion from the substrate, electric leakage is not easy to occur to the fin portion in the isolation structure, and the electrical performance of the semiconductor structure is optimized.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of specific embodiments of the present invention is provided below with reference to the accompanying drawings.
Fig. 6 to 15 are schematic structural views corresponding to steps in the first embodiment of the method for forming a semiconductor structure according to the present invention.
Referring to fig. 6, a base is provided, the base comprising a substrate 100 and a dummy fin 101 located on the substrate 100.
The substrate 100 is used to provide a process platform for the subsequent formation of fins.
In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The surface of the substrate 100 may further be formed with an interface layer, and the material of the interface layer may be silicon oxide, silicon nitride, silicon oxynitride, or the like.
In this embodiment, the material of the dummy fin 101 is the same as the material of the substrate 100. In other embodiments, the material of the dummy fin may also be different from the material of the substrate.
The step of forming the substrate 100 and the dummy fin 101 includes: providing a base film (not shown in the figure) and a dummy fin buffer material layer (not shown in the figure) on the base film, and forming a dummy fin mask layer 104 on the dummy fin buffer material layer; and etching the base film by taking the pseudo fin mask layer 104 as a mask to form a base and a pseudo fin buffer layer 103 positioned on the base, wherein the base comprises a substrate 100 and a pseudo fin 101 positioned on the substrate 100.
The mask layer 104 of the pseudo fin portion and the mask layer 101 of the pseudo fin portion have a larger etching selection ratio, and in the process of etching the substrate film to form the substrate, the mask layer 104 of the pseudo fin portion has extremely low etching rate and good selectivity.
The material of the dummy fin mask layer 104 may include one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the dummy fin mask layer 104 is silicon nitride.
The dummy fin buffer layer 103 is configured to reduce stress between the dummy fin mask layer 104 and the dummy fin 101, thereby improving adhesion between the fin mask layer 104 and the dummy fin 101.
The material of the dummy fin mask layer 104 is silicon nitride, the material of the dummy fin 101 is silicon, the thermal expansion coefficient of the silicon nitride is greatly different from that of the silicon, and the silicon nitride can crack or even fall off on the silicon, so that the silicon nitride cannot play a role of the mask layer.
In this embodiment, the material of the dummy fin buffer layer 103 is silicon oxide. The silicon oxide is not easy to crack or fall off by forming the silicon oxide between the silicon nitride and the silicon.
Referring to fig. 7 to 10, an isolation layer 102 is formed on the substrate 100 exposed by the dummy fin 101 (as shown in fig. 10), and the isolation layer 102 covers a portion of the sidewall of the dummy fin 101.
A fin portion is subsequently formed on the isolation layer 102, where the isolation layer 102 is configured to electrically isolate the fin portion from the substrate 100, so that leakage of electricity of the fin portion is not easy to occur, and electrical performance of the semiconductor structure is optimized.
In this embodiment, the material of the isolation layer 102 is an insulating material.
Specifically, the material of the isolation layer 102 includes one or more of silicon oxide, silicon nitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the isolation layer 102 is silicon oxide.
The step of forming the isolation layer 102 includes: forming an isolation material layer 105 on the substrate 100 exposed by the dummy fin portion 101, wherein the isolation material layer 105 covers part of the side wall of the dummy fin portion 101; the isolation layer 102 is formed by etching back a portion of the isolation material layer 105.
In this embodiment, a wet etching process is used to etch the isolation material layer 105, so as to form the isolation layer 102. The wet etching process is isotropic etching, so that the surface of the isolation layer 102 formed by etching is better in horizontality, the wet etching process has higher etching rate, the thickness of the removed isolation material layer 105 is easy to control by adopting low-concentration wet etching solution, and the operation is simple and the process cost is low.
Specifically, an HF solution is used to etch away a portion of the thickness of the isolation material layer 105.
In other embodiments, a dry etching process may be used to etch the isolation material layer to form an isolation layer.
The thickness of the isolation layer 102 is not too thick or too thin. If the isolation layer 102 is too thick, fin portions formed on the isolation layer 102 later collapse, so that the process difficulty is increased; if the isolation layer 102 is too thin, the isolation layer 102 is easy to break down, and the isolation layer 102 is not easy to electrically isolate the fin portion from the substrate 100, so that the fin portion is easy to leak electricity, which is not beneficial to optimizing the electrical performance of the semiconductor structure. In this embodiment, the thickness of the isolation layer is 3 nm to 8 nm.
Referring to fig. 8 and 9, the method for forming the semiconductor structure includes: after the isolation material layer 105 is formed, before the isolation layer 102 is formed, forming a sidewall 106 on the upper sidewall of the dummy fin portion 101 exposed by the isolation material layer 105 (as shown in fig. 9);
when the fin material is epitaxially grown in the area surrounded by the isolation layer and the dummy fin 101, the fin material rapidly grows on the isolation layer and the side wall of the portion of the dummy fin 101 exposed out of the side wall 106, but the fin material on the side wall 106 slowly grows, so that the fin material can grow from bottom to top, a cavity is not easy to exist in the formed fin, the formation quality of the fin is improved, and defects such as electric leakage and the like are not easy to occur in the fin.
The material of the sidewall 106 has poor adhesion with the fin material formed by epitaxial growth.
Specifically, the material of the sidewall 106 includes one or more of silicon oxide, silicon nitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the sidewall 106 is silicon oxide.
The step of forming the sidewall 106 includes: forming a side wall material layer 107, wherein the side wall material layer 107 conformally covers the isolation material layer 105 and the dummy fin portion 101 exposing the isolation material layer 105; and removing the side wall material layer 107 on the isolation material layer 105 and the top of the pseudo fin portion 101 to form the side wall 106.
In this embodiment, the sidewall material layer 107 is formed by an atomic layer deposition process (Atomic Layer Deposition, ALD). The atomic layer deposition process has good deposition uniformity, is favorable for improving the thickness uniformity and the film quality of the isolation film, is correspondingly favorable for improving the film forming quality of the side wall material layer 107, and is also favorable for accurately controlling the deposition thickness of the side wall material layer 107 by adopting the atomic layer deposition process. In other embodiments, the sidewall material layer may also be formed using a chemical vapor deposition process (Chemical Vapor Deposition, CVD).
In this embodiment, a maskless etching process is used to remove the sidewall material layer 107 on the isolation material layer 105 and the dummy fin 101, so as to form the sidewall 106. The maskless etching process does not need a Mask (Mask), and the process cost is reduced. Specifically, the maskless dry etching process is adopted to perform the maskless etching, and the dry etching process has the characteristic of anisotropic etching, so that the problem that the thickness of the side wall 106 is too thin due to lateral etching of the side wall material layer 107 is avoided while the side wall material layer 107 on the isolation material layer 105 and the pseudo fin 101 is completely removed, and therefore the side wall 106 can be ensured to be lower than the growth speed of the fin material on the isolation layer in the subsequent step of selectively epitaxially growing the fin, and the formed fin is not prone to having holes.
It should be noted that the proportion of the height of the dummy fin portion 101 covered by the sidewall 106 to the total height of the dummy fin portion 101 should not be too large or too small. If the ratio is too large, the subsequent epitaxial growth of the fin material on the isolation layer exposed by the dummy fin 101 is too slow, resulting in too long process time. If the duty ratio is too small, too many dummy fins 101 are exposed from the side walls 106, fin materials are selectively grown on too many side walls of the dummy fins 101, and the fin materials on the side walls of the dummy fins 101 are easily closed, so that voids exist in the subsequently formed fins, the formation quality of the fins is reduced, and the electrical performance of the semiconductor structure is not improved. In this embodiment, the height of the dummy fin portion 101 covered by the sidewall 106 is one third to two thirds of the total height of the dummy fin portion 101.
The sidewall 106 is preferably not too thick or too thin. If the sidewall 106 is too thick, the bottom of the sidewall 106 is not supported after the isolation layer 102 is formed, and the sidewall 106 is easy to fall off. If the side wall 106 is too thin, the side wall of the top part area of the pseudo fin 101 is not covered by the side wall 106, so that in the process of forming the fin material by subsequent epitaxial growth, the fin material is grown in the top part area which is not covered by the side wall 106, the top part is closed first, and then a cavity exists in the subsequently formed fin, so that electric leakage is easy to occur. In this embodiment, the thickness of the sidewall 106 is 3 nm to 10 nm.
Referring to fig. 11 and 12, a fin 109 is formed on the isolation layer 102 where the dummy fin 101 is exposed (as shown in fig. 12).
The fin 109 provides a channel region for carrier flow during subsequent operation.
In the step of forming the fin 109, the fin 109 formed between the dummy fin 101 exposed by the sidewall 106 is a bottom fin 1091, and the fin 109 formed between the sidewall 106 and the sidewall 106 is a top fin 1092.
In this embodiment, the materials of the dummy fin 101 and the fin 109 are different. The dummy fin portion 101 and the fin portion 109 have a larger etching selection ratio, so that the damage to the fin portion 109 caused by the subsequent process of removing the dummy fin portion 101 is smaller.
In this embodiment, the fin 109 is made of SiGe, and Si and SiGe have a large etching selectivity. SiGe is more capable of improving carrier mobility in the channel region than Si, and is advantageous for improving electrical properties of semiconductor structures.
In other embodiments, when the material of the dummy fin portion and the fin portion may also be Si. In other embodiments, when the material of the dummy fin is SiGe, the material of the fin may also be SiGe or Si; or the material of the pseudo fin portion is Ge, and the material of the fin portion is SiGe.
The step of forming the fin 109 includes: forming a fin material layer 108 (as shown in fig. 11) on the substrate 100 exposed by the dummy fin 101 by epitaxial growth, wherein the fin material layer 108 covers the dummy fin 101; and etching back the fin material layer 108 with partial thickness to form the fin 109.
In this embodiment, a dry etching process is used to etch a portion of the fin material layer 108 to form the fin 109. The dry etching process has the characteristic of anisotropic etching, and can well control the thickness of the fin portion material layer 108 removed by etching, so that the height of the fin portion 109 can meet the process requirement.
In other embodiments, the epitaxial growth method is adopted to form the direct fin portion on the substrate exposed by the pseudo fin portion, so that the etching back process is avoided, and the forming process of the semiconductor structure is simplified.
In this embodiment, the fin 109 has the same height as the dummy fin 101. In other embodiments, the fin may have a height different from the dummy fin.
The method for forming the semiconductor structure further comprises the following steps: after forming the fin 109, before removing the dummy fin 101, a fin mask material layer (not shown) covering the fin 109 and the dummy fin mask layer 104 is formed, a planarization process is used to remove the fin mask material layer higher than the fin mask layer 104, and a fin mask layer 110 is formed on the fin 109.
The fin mask layer 110 protects the top of the fin 109 from damage during the process of removing the dummy fin 101, so that the fin 109 has a consistent height.
Before removing the dummy fin 101, the dummy fin mask layer 104 needs to be removed, the fin mask layer 110 and the dummy fin mask layer 104 have an etching selectivity ratio, and the fin mask layer 110 is less damaged in the step of removing the dummy fin mask layer 104.
In this embodiment, the fin mask layer 110 is made of silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, is beneficial to reducing the process difficulty and the process cost for forming the fin mask layer 110, and has simple removal process. In other embodiments, the fin mask layer may further be made of SiC.
Referring to fig. 13, after the fin 109 is formed, the dummy fin 101 is removed.
Removing the dummy fins 101 provides for subsequently providing isolation structures on the substrate 100 where the fins 109 are exposed.
In this embodiment, the materials of the fin portion 109 and the dummy fin portion 101 are different, the fin portion 109 and the dummy fin portion 101 have an etching selectivity ratio, and a wet process is used to remove the dummy fin portion 101. The wet etching process is isotropic etching, has higher etching rate, and is simple to operate and low in process cost.
Specifically, the dummy fin 101 is removed using a tetramethylammonium hydroxide solution.
In other embodiments, when the materials of the dummy fin portion and the fin portion are the same, the fin portion mask layer is used as a mask, and a dry etching process is used to etch and remove the dummy fin portion. The thickness of the etched and removed pseudo fin portions is easy to control by the dry etching process, so that the heights of the remaining pseudo fin portions are well consistent.
After removing the dummy fin portion 101, the side wall 106 is also removed (as shown in fig. 12).
In this embodiment, a wet process is used to remove the sidewall 106. The wet etching process is isotropic etching, has higher etching rate, and is simple to operate and low in process cost.
Specifically, the sidewall 106 is removed using a phosphoric acid solution.
Referring to fig. 14, after the dummy fin 101 is removed, an isolation structure 111 is formed on the substrate 100 exposed by the fin 109, and the isolation structure 111 covers a portion of the sidewall of the fin 109.
The isolation structures 111 may function to electrically isolate adjacent fins 109. The gate structure is formed to span the fin 109, and covers a portion of the top surface and a portion of the sidewall of the fin 109, so that the gate structure can directly control the portion of the fin 109 covered by the gate structure, and a portion of the fin 109 in the isolation structure 111 is not covered by the gate structure, which is not easily controlled directly by the gate structure, but because the fin 109 is formed on the isolation layer 102, the isolation layer 102 electrically isolates the fin 109 from the substrate 100, so that leakage of the fin 109 is not easy to occur, and the electrical performance of the semiconductor structure is optimized.
In this embodiment, the material of the isolation structure 111 is an insulating material.
Specifically, the material of the isolation structure 111 includes one or more of silicon oxide, silicon nitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the isolation structure 111 is silicon oxide.
The step of forming the isolation structure 111 includes: forming an isolation material structure (not shown) covering the fin mask layer 110, and performing planarization treatment on the isolation material structure until the fin mask layer 110 is exposed; after exposing the fin mask layer 110, the isolation structure 111 is formed by etching back the isolation material structure with a partial thickness by using the fin mask layer 110 as a mask.
It should be noted that, in this embodiment, the fin mask layer 110 is consumed in the process of etching the isolation material structure to form the isolation structure 111, and after the fin mask layer 110 is removed, the fin 109 is used as a mask to etch the isolation material structure to form the isolation structure 111.
Referring to fig. 15, a gate structure 112 is formed across the fin 109, the gate structure 112 covering a portion of the top surface and a portion of the sidewalls of the fin 109.
The gate structure 112 is a polysilicon gate structure or a metal gate structure. The gate structure 112 is used to control the turning on and off of the channel in the fin 109 during semiconductor operation.
Fig. 16 to 19 are schematic structural views corresponding to steps in a second embodiment of a method for forming a semiconductor structure according to the present invention.
The present embodiment is the same as the first embodiment, and will not be described again. The present embodiment is different from the first embodiment in that: the fin 209 (shown in fig. 17) includes a buffer strained fin 2091 (shown in fig. 17) and a channel fin 2092 (shown in fig. 17) on the buffer strained fin 2091.
The Ge concentration in the buffer strained fin 2091 is low (when the semiconductor structure is PMOS, the Ge concentration in the channel fin 2092 is higher than the Ge concentration in the buffer strained fin 2091; when the semiconductor structure is NMOS, the material of the channel fin 2092 is Si, and the material of the buffer strained fin 2091 is SiGe), the buffer strained fin 2091 can provide sufficient stress to the channel fin 2092, so that the carrier mobility in the channel fin 2092 is fast. The gate structure is formed subsequently across the fin 209, and covers a portion of the top surface and a portion of the sidewall of the fin 209, so that the gate structure can directly control the portion of the fin 209 covered by the gate structure, while the portion of the fin in the isolation structure is not covered by the gate structure, and accordingly is not easily directly controlled by the gate structure, but because the fin 209 is formed on the isolation layer 102, the isolation layer 102 electrically isolates the fin 209 from the substrate 200, even if carriers with higher migration rate exist in the channel fin, the fin 209 in the gate structure is still not easily electrically connected with the substrate 200, so that electric leakage of the fin 209 is not easily generated, and the electrical performance of the semiconductor structure is optimized.
Referring to fig. 16 and 17, the fin 209 is formed.
In this embodiment, the semiconductor structure is PMOS, the materials of the buffer strained fin portion 2091 and the channel fin portion 2092 of PMOS are SiGe, and the mole volume percentage of Ge in the channel fin portion 2092 is higher than that of Ge in the buffer strained fin portion 2091, because Ge atoms are larger than Si atoms, the buffer strained fin portion 2091 with low Ge concentration contacts the channel fin portion 2092 with higher Ge concentration, compressive stress is generated in the channel fin portion 2092, tensile stress is generated in the buffer strained fin portion 2091, and compressive stress is generated in the channel fin portion 2092, which is favorable for improving carrier mobility in PMOS.
In other embodiments, the semiconductor structure is an NMOS, the material of the buffer strained fin is SiGe, and the material of the channel fin is Si. The Ge concentration in the channel fin portion is lower than that in the buffer strain fin portion, the channel fin portion grows on the buffer strain fin portion, and the channel fin portion is provided with tensile stress, so that carrier mobility in the NMOS is improved.
The step of forming the buffer strained fin 2091 includes: a buffer strained fin 2091 is formed on the substrate 200 exposed by the dummy fin 201 by epitaxial growth.
The step of forming the channel fin 2092 includes: after the buffer strained fin 2091 is formed, the channel fin 2092 is formed on the buffer strained fin 2091 by epitaxial growth. In other embodiments, the epitaxial growth method is adopted to form a channel fin portion material layer on the buffer strained fin portion, the channel fin portion material layer covers the dummy fin portion, and the channel fin portion material layer with partial thickness is etched back to form the channel fin portion.
It should be noted that the ratio of the height of the buffer strained fin 2091 to the height of the fin 209 should not be too large or too small. If the ratio is too large, the process time to form the buffer strained fin 2091 is too long. If the ratio is too small, the buffer strained fin 2091 is too short, which easily results in too steep concentration gradient between the buffer strained fin 2091 and the channel fin 2092, resulting in too large stress generated between the channel fin 2092 and the buffer strained fin 2091, and further results in easy falling of the channel fin 2092. In this embodiment, the height of the buffer strained fin 2091 is one third to two thirds of the height of the fin 209.
Referring to fig. 18, an isolation structure 211 is formed on the substrate 200 where the fin 209 is exposed.
In this embodiment, the isolation structure 211 covers a portion of the sidewall of the channel fin 2092. In other embodiments, the isolation structure covers a portion of the sidewall of the buffer strained fin; alternatively, the top surface of the isolation structure is flush with the top surface of the buffer strained fin.
Referring to fig. 19, a gate structure 212 is formed across the fin 209, the gate structure 212 covering a portion of the top surface and a portion of the sidewalls of the fin 209.
The gate structure 212 is a polysilicon gate structure or a metal gate structure. The gate structure 212 is used to control the turn-on and turn-off of the channel in the fin 209 during semiconductor operation.
For a specific description of the forming method in this embodiment, reference may be made to the description related to the first embodiment, which is not repeated here.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 15, a schematic structural diagram of a first embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100; an isolation layer 102, discrete on the substrate 100; a fin 109 located on the isolation layer 102; the isolation structure 111 is located on the substrate 100 exposed by the fin 109, and the isolation structure 111 covers part of the side wall of the fin 109; a gate structure 112 spans the fin 109 and covers a portion of the top surface and a portion of the sidewalls of the fin 109.
The gate structure 112 can directly control the part of the fin 109 covered by the gate structure, but the part of the fin 109 in the isolation structure 111 is not covered by the gate structure, so that the part of the fin 109 in the isolation structure is not easily controlled by the gate structure, and electric leakage easily occurs between the fin 109 in the isolation structure and the substrate 100.
The substrate 100 is used to provide a process platform for forming semiconductor structures.
In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The surface of the substrate 100 may further be formed with an interface layer, and the material of the interface layer may be silicon oxide, silicon nitride, silicon oxynitride, or the like.
The isolation layer 102 is used to electrically isolate the fin 109 from the substrate 100, so that the fin 109 is not prone to leakage, and the electrical performance of the semiconductor structure is optimized.
In this embodiment, the material of the isolation layer 102 is an insulating material.
Specifically, the material of the isolation layer 102 includes one or more of silicon oxide, silicon nitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the isolation layer 102 is silicon oxide.
The thickness of the isolation layer 102 is not too thick or too thin. If the isolation layer 102 is too thick, the fin portion may collapse. If the isolation layer 102 is too thin, the isolation layer 102 is easy to break down, and the isolation layer 102 is not easy to electrically isolate the fin 109 from the substrate 100, so that the fin 109 is easy to leak electricity, which is not beneficial to optimizing the electrical performance of the semiconductor structure. In this embodiment, the thickness of the isolation layer 102 is 3 nm to 8 nm.
In this embodiment, the semiconductor structure is used to form PMOS, and the fin 109 is made of SiGe, which is better than Si in improving carrier mobility in the channel region, and is beneficial to improving electrical performance of the semiconductor structure. In other embodiments, the fin may also be made of Si or Ge.
In this embodiment, the fin 109 includes a bottom fin 1091 and a top fin 1092 located on the bottom fin 1091, where the bottom fin 1091 is wider than the top fin 1092 in a direction perpendicular to the extension direction of the fin 109.
The sidewalls of the bottom fin 1091 are flush with the sidewalls of the isolation layer 102.
The difference in width between the bottom fin 1091 and the top fin 1092 in the direction perpendicular to the extending direction of the fin 109 is not too large or too small. If the width difference is too large, the difficulty in forming the fin 109 is too large, which is not beneficial to improving the process rate; if the width difference is too small, voids are likely to exist in the fin 109 and leakage is likely to occur during the process of selectively epitaxially forming the material of the fin 109. In this embodiment, the difference in width between the bottom fin 1091 and the top fin 1092 is between 6 nm and 16 nm.
It should be noted that the proportion of the height of the top fin 1092 to the total height of the fin 109 is not too large or too small. If the ratio is too large, the speed of selectively epitaxially growing the fin 109 material is too slow, resulting in too long process time; if the ratio is too small, voids are likely to exist in the fin 109 during the process of selectively epitaxially forming the material of the fin 109, which reduces the formation quality of the fin 109 and is not beneficial to improving the electrical performance of the semiconductor structure. In this embodiment, the top fin 1092 has a height that is one third to two thirds of the total height of the fin 109.
The isolation structures 111 serve to electrically isolate adjacent fins 109.
In this embodiment, the material of the isolation structure 111 is an insulating material.
Specifically, the material of the isolation structure 111 includes one or more of silicon oxide, silicon nitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the isolation structure 111 is silicon oxide.
In this embodiment, the gate structure 112 is a polysilicon gate structure or a metal gate structure.
The gate structure 112 is used to control the turning on and off of the channel in the fin 109 during semiconductor operation.
Referring to fig. 19, a schematic structural diagram of a second embodiment of the semiconductor structure of the present invention is shown. The present embodiment is different from the first embodiment in that: the fin 209 includes a buffer strained fin 2091 and a channel fin 2092 on the buffer strained fin 2091.
In this embodiment, when the semiconductor structure is PMOS, the materials of the buffer strained fin 2091 and the channel fin 2092 are SiGe, and the mol volume percentage of Ge in the channel fin 2092 is higher than the mol volume percentage of Ge in the buffer strained fin 2091. Because the Ge atoms are larger than the Si atoms, the contact of the buffer strained fin 2091 with a low Ge concentration with the channel fin 2092 with a higher Ge concentration may generate compressive stress in the channel fin 2092 and may generate tensile stress in the buffer strained fin 2091, and the channel fin 2092 has compressive stress therein, which is beneficial to carrier mobility in PMOS.
In other embodiments, the semiconductor structure is an NMOS, the material of the buffer strained fin is SiGe, and the material of the channel fin is Si. The Ge concentration in the channel fin is lower than that in the buffer strain fin, the channel fin grows on the buffer strain fin, and the channel fin is provided with tensile stress, so that carrier mobility in the NMOS is facilitated.
The Ge concentration in the buffer strained fin 2091 is low (when the semiconductor structure is PMOS, the Ge concentration in the channel fin 2092 is higher than the Ge concentration in the buffer strained fin 2091; when the semiconductor structure is NMOS, the material of the channel fin 2092 is Si, and the material of the buffer strained fin 2091 is SiGe), the buffer strained fin 2091 can provide sufficient stress to the channel fin 2092, so that the carrier mobility in the channel fin 2092 is fast. The gate structure 212 covers a portion of the top surface and a portion of the sidewall of the fin 209, so that the gate structure 212 can directly control a portion of the fin 209 covered by the gate structure, but a portion of the fin 209 in the isolation structure 211 is not covered by the gate structure 212, and is correspondingly not easily controlled directly by the gate structure 212, but because the fin 209 is formed on the isolation layer 102, the isolation layer 102 electrically isolates the fin 209 from the substrate 200, even if carriers with higher migration rate in the channel fin 2092 are not easily electrically connected with the substrate 200, so that the fin 209 is not easily electrically leaked, and the electrical performance of the semiconductor structure is optimized.
It should be noted that the ratio of the height of the buffer strained fin 2091 to the height of the fin 209 should not be too large or too small. If the ratio is too large, the process time to form the buffer strained fin 2091 is too long; if the ratio is too small, the buffer strained fin 2091 is too short, which easily results in too steep concentration gradient between the buffer strained fin 2091 and the channel fin 2092, resulting in too large stress generated between the channel fin 2092 and the buffer strained fin 2091, and further results in easy falling of the channel fin 2092. In this embodiment, the height of the buffer strained fin 2091 is one third to two thirds of the height of the fin 209.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the invention, and the scope of the embodiments of the invention should be pointed out in the appended claims.

Claims (15)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate and a pseudo fin part positioned on the substrate;
forming an isolation layer on the substrate exposed by the pseudo fin portion, wherein the isolation layer covers part of the side wall of the pseudo fin portion;
forming a side wall on the upper side wall of the pseudo fin part;
forming fin parts on the isolation layer exposed by the pseudo fin parts, wherein the fin parts are filled between the pseudo fin parts exposed by the side walls and between adjacent side walls;
removing the pseudo fin portion after forming the fin portion;
and after the pseudo fin portion is removed, forming an isolation structure on the substrate exposed out of the fin portion, wherein the isolation structure covers part of the side wall of the fin portion.
2. The method of forming a semiconductor structure of claim 1, wherein forming the fin comprises: forming a fin portion on the substrate exposed by the pseudo fin portion by adopting an epitaxial growth method;
or, forming a fin portion material layer on the substrate exposed by the pseudo fin portion by adopting an epitaxial growth method, wherein the fin portion material layer covers the pseudo fin portion; and etching back the fin material layer with partial thickness to form the fin.
3. The method of forming a semiconductor structure of claim 1, wherein,
the material of the pseudo fin part is Si or Ge, and the material of the fin part is SiGe;
or the material of the pseudo fin part is SiGe, and the material of the fin part is Si;
or the materials of the pseudo fin part and the fin part are Si;
or the materials of the pseudo fin portion and the fin portion are SiGe.
4. The method of claim 1, wherein the dummy fin is removed using one or both of a wet etch process and a dry etch process.
5. The method of forming a semiconductor structure of claim 1, wherein after forming the fin, removing the dummy fin further comprises: forming a fin mask layer on the fin; and removing the pseudo fin parts by taking the fin part mask layer as a mask and adopting a dry etching process.
6. The method of forming a semiconductor structure of claim 1, wherein the step of forming the isolation layer comprises: forming an isolation material layer on the substrate exposed by the pseudo fin portion, wherein the isolation material layer covers part of the side wall of the pseudo fin portion; etching back part of the isolation material layer to form the isolation layer;
in the step of forming the fin portions, the fin portions formed between the dummy fin portions exposed from the side walls are bottom fin portions, and the fin portions formed between the side walls are top fin portions.
7. The method of claim 6, wherein the sidewall has a thickness of 3 nm to 10 nm.
8. The method of claim 6, wherein the sidewall material comprises one or more of SiO, siN, siC, siON, siBCN and SiCN.
9. The method of forming a semiconductor structure of claim 6, wherein the step of forming a sidewall comprises: forming a side wall material layer, wherein the side wall material layer conformally covers the isolation material layer and exposes the pseudo fin parts of the isolation material layer; and removing the side wall material layers on the isolation material layer and the pseudo fin parts to form the side wall.
10. The method of claim 6, wherein the dummy fin covered by the sidewall has a height of one third to two thirds of a total height of the dummy fin.
11. The method of forming a semiconductor structure of claim 1, wherein the fin comprises a buffer strained fin and a channel fin on the buffer strained fin;
the semiconductor structure is PMOS, the buffer strain fin portion and the channel fin portion are made of SiGe, and the mole volume percentage of Ge in the channel fin portion is higher than that in the buffer strain fin portion;
or the semiconductor structure is NMOS, the material of the buffer strain fin part is SiGe, and the material of the channel fin part is Si;
in the step of forming the isolation structure, the isolation structure covers part of the side wall of the channel fin part; or, the top surface of the isolation structure covers part of the side wall of the buffer strain fin part; or the top surface of the isolation structure is flush with the top surface of the buffer strain fin.
12. The method of forming a semiconductor structure of claim 11, wherein forming the buffer strained fin comprises: forming a buffer strain fin portion on the substrate exposed by the pseudo fin portion by adopting an epitaxial growth method;
the step of forming the channel fin includes: after the buffer strain fin portion is formed, forming the channel fin portion on the buffer strain fin portion by adopting an epitaxial growth method;
or forming a channel fin part material layer on the buffer strain fin part by adopting the epitaxial growth method, wherein the channel fin part material layer covers the pseudo fin part, and etching back the channel fin part material layer with partial thickness to form the channel fin part.
13. The method of claim 11, wherein a height of the buffer strained fin is one third to two thirds of a height of the fin.
14. The method of forming a semiconductor structure of claim 1, wherein the spacer layer has a thickness of 3 nm to 8 nm.
15. The method of forming a semiconductor structure of claim 1, wherein the material of the isolation layer comprises one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
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CN107615490A (en) * 2015-06-26 2018-01-19 英特尔公司 In sacrificial core via cladding transistor fin-shaped into
CN106409680A (en) * 2015-07-31 2017-02-15 台湾积体电路制造股份有限公司 Semiconductor device including fin structures and manufacturing method thereof
CN106558614A (en) * 2015-09-30 2017-04-05 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

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