CN111613582A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN111613582A
CN111613582A CN201910134224.4A CN201910134224A CN111613582A CN 111613582 A CN111613582 A CN 111613582A CN 201910134224 A CN201910134224 A CN 201910134224A CN 111613582 A CN111613582 A CN 111613582A
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fin
forming
isolation
fin part
semiconductor structure
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CN111613582B (en
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate comprises a substrate and a pseudo fin part positioned on the substrate; forming an isolation layer on the substrate exposed out of the pseudo fin part, wherein the isolation layer covers part of the side wall of the pseudo fin part; forming a fin part on the isolation layer exposed out of the pseudo fin part; after the fin part is formed, removing the pseudo fin part; and after removing the pseudo fin part, forming an isolation structure on the substrate exposed out of the fin part, wherein the isolation structure covers part of the side wall of the fin part. After the gate structure which stretches across the fin part and covers part of the top surface and part of the side wall of the fin part is formed subsequently, the gate structure can directly control the part of the fin part covered by the gate structure, and the part of the fin part in the isolation structure is not covered by the gate structure and is not easily controlled directly by the gate structure.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
In Semiconductor manufacturing, with the trend of ultra-large scale integrated circuits, the feature size of the integrated circuit is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is also continuously shortened correspondingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the controllability of the gate structure to the channel is deteriorated, and the difficulty of the gate voltage to pinch off the channel is increased, so that a sub-threshold leakage (SCE) phenomenon, which is a so-called short-channel effect (SCE), is more likely to occur.
Therefore, in order to better accommodate the reduction of feature sizes, semiconductor processing is gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit a short-channel effect; and finfets have better compatibility with existing integrated circuit fabrication relative to other devices.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which optimize electrical properties of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a substrate and a pseudo fin part positioned on the substrate; forming an isolation layer on the substrate exposed out of the pseudo fin portion, wherein the isolation layer covers part of the side wall of the pseudo fin portion; forming a fin part on the isolation layer exposed out of the pseudo fin part; after the fin part is formed, removing the pseudo fin part; and after removing the pseudo fin part, forming an isolation structure on the substrate exposed out of the fin part, wherein the isolation structure covers part of the side wall of the fin part.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; an isolation layer separated from the substrate; a fin portion located on the isolation layer; and the isolation structure is positioned on the substrate with the exposed fin part and covers part of the side wall of the fin part.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a base, which comprises a substrate and a pseudo fin part positioned on the substrate; forming an isolation layer on the substrate exposed out of the pseudo fin portion, wherein the isolation layer covers part of the side wall of the pseudo fin portion; forming a fin part on the isolation layer exposed out of the pseudo fin part; after the fin part is formed, removing the pseudo fin part; and forming an isolation structure on the substrate exposed out of the fin part, wherein the isolation structure covers part of the side wall of the fin part. After a gate structure which stretches across the fin part and covers part of the top surface and part of the side wall of the fin part is formed subsequently, the gate structure can directly control part of the fin part covered by the gate structure, and part of the fin part in the isolation structure is not covered by the gate structure, so that the fin part is not easily controlled by the gate structure, and electric leakage is easily generated between the fin part in the isolation structure and the substrate.
Drawings
Fig. 1 to 5 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
fig. 6 to 15 are schematic structural views corresponding to steps in the first embodiment of the method for forming a semiconductor structure according to the embodiment of the present invention;
fig. 16 to 19 are schematic structural diagrams corresponding to steps in a second embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As can be seen from the background art, the performance of the devices formed at present is still not good. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.
Referring to fig. 1 to 5, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, a base is provided, the base comprising a substrate 10 and a fin 11 on the substrate 10.
Referring to fig. 2, a spacer material layer 12 is formed on the substrate 10 exposed by the fin 11 (shown in fig. 1); after the isolation material layer 12 is formed, the fin portion 11 is removed by a certain thickness, and a groove 13 is formed.
Referring to fig. 3, a filler fin 14 is formed in the recess 13 (shown in fig. 2).
Referring to fig. 4, a portion of the thickness of the isolation material layer 12 is removed to form an isolation layer 15 exposing a portion of the thickness of the filled fin 14.
Referring to fig. 5, a gate structure 16 is formed across the fill fin 14, wherein the gate structure 16 covers a portion of the top wall and a portion of the sidewalls of the fill fin 14.
It should be noted that the material of the filling fin 14 is silicon, and the material of the filling fin 14 is SiGe, which is capable of improving carrier mobility compared with Si, so that more and more channel regions are changed from Si to SiGe, but because only a portion of the filling fin 14 located above the isolation layer 15 in the semiconductor structure is directly controlled by the gate structure 16, the filling fin 14 in the isolation layer 15 is not easily directly controlled by the gate structure 16, and when the carrier mobility rate in the channel region is increased, carriers flowing in the filling fin 14 in the isolation layer 15 are likely to cause punch-through, resulting in poor electrical performance of the semiconductor structure.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a substrate and a pseudo fin part positioned on the substrate; forming an isolation layer on the substrate exposed out of the pseudo fin portion, wherein the isolation layer covers part of the side wall of the pseudo fin portion; forming a fin part on the isolation layer exposed out of the pseudo fin part; after the fin part is formed, removing the pseudo fin part; and after removing the pseudo fin part, forming an isolation structure on the substrate exposed out of the fin part, wherein the isolation structure covers part of the side wall of the fin part.
The embodiment of the invention provides a base, which comprises a substrate and a pseudo fin part positioned on the substrate; forming an isolation layer on the substrate exposed out of the pseudo fin portion, wherein the isolation layer covers part of the side wall of the pseudo fin portion; forming a fin part on the isolation layer exposed out of the pseudo fin part; after the fin part is formed, removing the pseudo fin part; and forming an isolation structure on the substrate exposed out of the fin part, wherein the isolation structure covers part of the side wall of the fin part. After a gate structure which stretches across the fin part and covers part of the top surface and part of the side wall of the fin part is formed subsequently, the gate structure can directly control part of the fin part covered by the gate structure, and part of the fin part in the isolation structure is not covered by the gate structure, so that the fin part is not easily controlled by the gate structure, and electric leakage is easily generated between the fin part in the isolation structure and the substrate.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 6 to 15 are schematic structural diagrams corresponding to steps in the first embodiment of the method for forming a semiconductor structure according to the present invention.
Referring to fig. 6, a base is provided, the base including a substrate 100 and a dummy fin 101 on the substrate 100.
The substrate 100 is used to provide a process platform for subsequent fin formation.
In this embodiment, the substrate 100 is made of silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The surface of the substrate 100 may also form an interface layer, and the material of the interface layer is silicon oxide, silicon nitride, silicon oxynitride, or the like.
In this embodiment, the material of the dummy fin 101 is the same as that of the substrate 100. In other embodiments, the dummy fin may be made of a different material than the substrate.
The steps of forming the substrate 100 and the dummy fin 101 include: providing a base film (not shown in the figure) and a dummy fin buffer material layer (not shown in the figure) on the base film, and forming a dummy fin mask layer 104 on the dummy fin buffer material layer; and etching the base film by taking the pseudo fin mask layer 104 as a mask to form a base and a pseudo fin buffer layer 103 positioned on the base, wherein the base comprises a substrate 100 and a pseudo fin 101 positioned on the substrate 100.
The dummy fin portion mask layer 104 and the dummy fin portion 101 have a large etching selection ratio, and in the process of etching the substrate film forming substrate by the dummy fin portion mask layer 104, the etching rate of the dummy fin portion mask layer 104 is extremely low, and good selectivity is achieved.
The dummy fin mask layer 104 is made of one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the dummy fin mask layer 104 is made of silicon nitride.
The dummy fin buffer layer 103 is used for reducing stress between the dummy fin mask layer 104 and the dummy fin 101, so as to improve adhesion between the fin mask layer 104 and the dummy fin 101.
The dummy fin portion mask layer 104 is made of silicon nitride, the dummy fin portion 101 is made of silicon, the difference between the thermal expansion coefficients of the silicon nitride and the silicon is large, and the silicon nitride cracks or even falls off on the silicon, so that the silicon nitride cannot play a role of the mask layer.
In this embodiment, the dummy fin buffer layer 103 is made of silicon oxide. The silicon oxide is not easy to crack or fall off by forming the silicon oxide between the silicon nitride and the silicon.
Referring to fig. 7 to 10, an isolation layer 102 is formed on the substrate 100 where the dummy fins 101 are exposed (as shown in fig. 10), and the isolation layer 102 covers part of the sidewalls of the dummy fins 101.
And subsequently, a fin part is formed on the isolation layer 102, and the isolation layer 102 is used for electrically isolating the fin part from the substrate 100, so that the fin part is not easy to leak electricity, and the electrical property of the semiconductor structure is optimized.
In this embodiment, the isolation layer 102 is made of an insulating material.
Specifically, the material of the isolation layer 102 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the isolation layer 102 is made of silicon oxide.
The step of forming isolation layer 102 includes: forming an isolation material layer 105 on the substrate 100 exposed by the dummy fin 101, wherein the isolation material layer 105 covers part of the sidewall of the dummy fin 101; a portion of the thickness of the isolation material layer 105 is etched back to form the isolation layer 102.
In this embodiment, the isolation material layer 105 is etched by a wet etching process to form the isolation layer 102. The wet etching process is isotropic etching, so that the levelness of the surface of the isolation layer 102 formed by etching is better, the wet etching process has higher etching rate, the adoption of a low-concentration wet etching solution is easy to control the thickness of the removed isolation material layer 105, the operation is simple, and the process cost is low.
Specifically, the isolation material layer 105 is etched and removed by a HF solution.
In other embodiments, the isolation material layer may be etched by a dry etching process to form the isolation layer.
It should be noted that the thickness of the isolation layer 102 is not too thick or too thin. If the isolation layer 102 is too thick, a fin portion formed on the isolation layer 102 later collapses, which increases the process difficulty; if the isolation layer 102 is too thin, the isolation layer 102 is easily broken down, and the isolation layer 102 does not easily electrically isolate the fin portion from the substrate 100, so that the fin portion is easily subjected to electric leakage, and the electrical performance of the semiconductor structure is not optimized. In this embodiment, the thickness of the isolation layer is 3 nm to 8 nm.
Referring to fig. 8 and 9, the method of forming the semiconductor structure includes: after the isolation material layer 105 is formed and before the isolation layer 102 is formed, forming a sidewall 106 on the upper sidewall of the dummy fin 101 exposed by the isolation material layer 105 (as shown in fig. 9);
when the fin material is epitaxially grown in the region surrounded by the isolation layer and the dummy fin portion 101, the fin material grows rapidly on the isolation layer and on the partial dummy fin portion 101 exposed from the side wall 106, but the fin material on the side wall 106 grows slowly, so that the fin material can grow from bottom to top, a hole is not easy to exist in the formed fin portion, the formation quality of the fin portion is improved, and the fin portion is not easy to have the defects of electric leakage and the like.
The sidewall 106 material has poor adhesion to the epitaxially formed fin material.
Specifically, the material of the sidewall 106 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the sidewall 106 is silicon oxide.
The step of forming the sidewall spacers 106 includes: forming a side wall material layer 107, wherein the side wall material layer 107 conformally covers the isolation material layer 105 and the pseudo fin part 101 exposed out of the isolation material layer 105; and removing the side wall material layer 107 on the isolation material layer 105 and on the top of the pseudo fin portion 101 to form the side wall 106.
In this embodiment, the sidewall material Layer 107 is formed by an Atomic Layer Deposition (ALD) process. The atomic layer deposition process has good deposition uniformity, is beneficial to improving the thickness uniformity and the film quality of the isolation film, is correspondingly beneficial to improving the film forming quality of the side wall material layer 107, and is also beneficial to accurately controlling the deposition thickness of the side wall material layer 107 by adopting the atomic layer deposition process. In other embodiments, a Chemical Vapor Deposition (CVD) process may also be used to form the sidewall material layer.
In this embodiment, the sidewall material layer 107 on the isolation material layer 105 and on the dummy fin 101 is removed by a maskless etching process to form the sidewall 106. The maskless etching process does not need a Mask (Mask), thereby reducing the process cost. Specifically, the maskless etching is performed by adopting a maskless dry etching process, and the dry etching process has the characteristic of anisotropic etching, so that the problem that the thickness of the side wall 106 is too thin due to the transverse etching of the side wall material layer 107 is avoided while the side wall material layers 107 on the isolation material layer 105 and the pseudo fin portion 101 are completely removed, and the side wall 106 can be ensured to ensure that the growth speed of the fin portion material on the side wall of the side wall 106 is lower than that of the fin portion material on the isolation layer in the subsequent step of selectively epitaxially growing the fin portion, so that a cavity is not easy to exist in the formed fin portion.
It should be noted that the ratio of the height of the dummy fin 101 covered by the side walls 106 to the total height of the dummy fin 101 is not too large or too small. If the ratio is too high, the speed of subsequent epitaxial growth of fin material on the exposed isolation layer of the dummy fin 101 is too slow, which results in too long process time. If the occupation ratio is too small, too many pseudo fin portions 101 exposed out of the side walls 106 are likely to be caused, fin portion materials are selectively grown on too many side walls on the pseudo fin portions 101, and fin portion materials on the side walls of the pseudo fin portions 101 are likely to be closed first, so that holes exist in subsequently formed fin portions, the formation quality of the fin portions is reduced, and the improvement of the electrical performance of the semiconductor structure is not facilitated. In this embodiment, the height of the dummy fin 101 covered by the sidewall 106 is one third to two thirds of the total height of the dummy fin 101.
It should be noted that the sidewall 106 is not too thick or too thin. If the sidewall 106 is too thick, after the isolation layer 102 is formed, the bottom of the sidewall 106 is not supported, and the sidewall 106 is easy to fall off. If the side wall 106 is too thin, the side wall of the partial region at the top of the pseudo fin portion 101 is not covered by the side wall 106, and in the process of forming fin material by subsequent epitaxial growth, the fin material is grown in the region at the top which is not covered by the side wall 106, so that the top is firstly closed, and further, a cavity is formed in the fin portion formed subsequently, and electric leakage is easy to occur. In this embodiment, the thickness of the sidewall 106 is 3 nm to 10 nm.
Referring to fig. 11 and 12, a fin 109 is formed on the isolation layer 102 exposed by the dummy fin 101 (as shown in fig. 12).
The fin 109 provides a channel region for carrier flow during subsequent operation.
In the step of forming the fin portion 109, the fin portion 109 formed between the dummy fin portions 101 exposed by the side walls 106 is a bottom fin portion 1091, and the fin portion 109 formed between the side walls 106 and the side walls 106 is a top fin portion 1092.
In this embodiment, the dummy fin 101 and the fin 109 are made of different materials. The dummy fin portion 101 and the fin portion 109 have a larger etching selection ratio, so that the subsequent process of removing the dummy fin portion 101 has less damage to the fin portion 109.
In this embodiment, the fin 109 is made of SiGe, and Si and SiGe have a larger etching selectivity. Compared with Si, SiGe can improve the carrier mobility in a channel region, and is favorable for improving the electrical property of a semiconductor structure.
In other embodiments, the dummy fin and the fin may be made of Si. In other embodiments, when the dummy fin is SiGe, the fin may be SiGe or Si; or the dummy fin portion is made of Ge and the fin portion is made of SiGe.
The step of forming the fin 109 includes: forming a fin material layer 108 (as shown in fig. 11) on the substrate 100 exposed by the dummy fin 101 by using an epitaxial growth method, wherein the fin material layer 108 covers the dummy fin 101; the fin material layer 108 is etched back to a certain thickness to form a fin 109.
In this embodiment, the fin material layer 108 with a certain thickness is etched by a dry etching process to form a fin 109. The dry etching process has the characteristic of anisotropic etching, and the thickness of the fin material layer 108 removed by etching can be better controlled by the dry etching process, so that the height of the fin 109 can meet the process requirement.
In other embodiments, an epitaxial growth method is adopted to form a direct fin portion on the substrate exposed out of the pseudo fin portion, so that a back etching process is avoided, and a semiconductor structure forming process is simplified.
It should be noted that, in this embodiment, the height of the fin portion 109 is the same as the height of the dummy fin portion 101. In other embodiments, the height of the fin and the height of the dummy fin may be different.
The method for forming the semiconductor structure further comprises the following steps: after the fin 109 is formed, a fin mask material layer (not shown) covering the fin 109 and the dummy fin mask layer 104 is formed before the dummy fin 101 is removed, the fin mask material layer higher than the dummy fin mask layer 104 is removed by a planarization process, and a fin mask layer 110 is formed on the fin 109.
The fin mask layer 110 protects the top of the fin 109 from damage during removal of the dummy fin 101, resulting in uniformity of the height of the fin 109.
It should be noted that, before removing the dummy fin 101, the dummy fin mask layer 104 needs to be removed, the fin mask layer 110 has an etching selectivity with the dummy fin mask layer 104, and the fin mask layer 110 is less damaged in the step of removing the dummy fin mask layer 104.
In this embodiment, the fin mask layer 110 is made of silicon oxide. The silicon oxide is a dielectric material with a common process and low cost, has high process compatibility, is beneficial to reducing the process difficulty and the process cost for forming the fin mask layer 110, and has a simple removal process. In other embodiments, the fin mask layer may be made of SiC.
Referring to fig. 13, after the fin portion 109 is formed, the dummy fin portion 101 is removed.
Removing the dummy fins 101 provides for a subsequent provision of isolation structures on the substrate 100 exposed by the fins 109.
In this embodiment, the fin portion 109 and the dummy fin portion 101 are made of different materials, the fin portion 109 and the dummy fin portion 101 have an etching selectivity, and the dummy fin portion 101 is removed by a wet process. The wet etching process is isotropic etching, has high etching rate, and is simple to operate and low in process cost.
Specifically, the dummy fin 101 is removed by using a tetramethylammonium hydroxide solution.
In other embodiments, when the dummy fin portion and the fin portion are made of the same material, the fin portion mask layer is used as a mask, and the dummy fin portion is removed by etching through a dry etching process. The dry etching process is easy to control the thickness of the pseudo fin portion removed by etching, so that the heights of the remaining pseudo fin portions are good and consistent.
Note that, after the dummy fin 101 is removed, the side walls 106 are also removed (as shown in fig. 12).
In this embodiment, the sidewall 106 is removed by a wet process. The wet etching process is isotropic etching, has high etching rate, and is simple to operate and low in process cost.
Specifically, the side wall 106 is removed by using a phosphoric acid solution.
Referring to fig. 14, after removing the dummy fin 101, an isolation structure 111 is formed on the substrate 100 exposed by the fin 109, and the isolation structure 111 covers a portion of the sidewall of the fin 109.
The isolation structure 111 may serve to electrically isolate adjacent fins 109. A gate structure crossing the fin 109 is formed subsequently, and the gate structure covers part of the top surface and part of the sidewall of the fin 109, so that the gate structure can directly control part of the fin 109 covered by the gate structure, and part of the fin 109 in the isolation structure 111 is not covered by the gate structure, so that the fin 109 is not easily directly controlled by the gate structure, but because the fin 109 is formed on the isolation layer 102, the isolation layer 102 electrically isolates the fin 109 from the substrate 100, so that the fin 109 is not easily subjected to electric leakage, and the electrical performance of the semiconductor structure is optimized.
In this embodiment, the isolation structure 111 is made of an insulating material.
Specifically, the material of the isolation structure 111 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the isolation structure 111 is made of silicon oxide.
The step of forming the isolation structure 111 includes: forming an isolation material structure (not shown) covering the fin mask layer 110, and performing planarization treatment on the isolation material structure until the fin mask layer 110 is exposed; after the fin mask layer 110 is exposed, the isolation material structure with a part of thickness is etched back by using the fin mask layer 110 as a mask, and an isolation structure 111 is formed.
It should be noted that, in this embodiment, the fin mask layer 110 is consumed in the process of etching the isolation material structure to form the isolation structure 111, and after the fin mask layer 110 is removed, the isolation material structure is etched by using the fin 109 as a mask to form the isolation structure 111.
Referring to fig. 15, a gate structure 112 is formed to cross the fin 109, and the gate structure 112 covers a portion of the top surface and a portion of the sidewall of the fin 109.
The gate structure 112 is a polysilicon gate structure or a metal gate structure. The gate structure 112 is used to control the channel in the fin 109 to be turned on and off during semiconductor operation.
Fig. 16 to 19 are schematic structural diagrams corresponding to steps in a second embodiment of a method for forming a semiconductor structure according to the present invention.
The same parts of this embodiment as those of the first embodiment will not be described herein again. The present embodiment is different from the first embodiment in that: the fin 209 (shown in fig. 17) includes a strain relief fin 2091 (shown in fig. 17) and a channel fin 2092 (shown in fig. 17) on the strain relief fin 2091.
The Ge concentration in the strain buffer fin portion 2091 is low (when the semiconductor structure is a PMOS, the Ge concentration in the channel fin portion 2092 is higher than the Ge concentration in the strain buffer fin portion 2091; when the semiconductor structure is an NMOS, the channel fin portion 2092 is made of Si and the strain buffer fin portion 2091 is made of SiGe), and the strain buffer fin portion 2091 can provide sufficient stress for the channel fin portion 2092, so that the carrier transfer rate in the channel fin portion 2092 is fast. A gate structure crossing the fin portion 209 is formed subsequently, and the gate structure covers part of the top surface and part of the side wall of the fin portion 209, so that the gate structure can directly control part of the fin portion 209 covered by the gate structure, and part of the fin portion in the isolation structure is not covered by the gate structure, and is not easily controlled by the gate structure correspondingly, but because the fin portion 209 is formed on the isolation layer 102, the isolation layer 102 electrically isolates the fin portion 209 from the substrate 200, even though the channel fin portion has carriers with high migration rate, the fin portion 209 in the gate structure is still not easily electrically connected with the substrate 200, so that the fin portion 209 is not easy to generate electric leakage, and the electrical performance of the semiconductor structure is optimized.
Referring to fig. 16 and 17, the fin 209 is formed.
In this embodiment, the semiconductor structure is a PMOS, the buffer strain fin portion 2091 and the channel fin portion 2092 of the PMOS are made of SiGe, and the molar volume percentage of Ge in the channel fin portion 2092 is higher than the molar volume percentage of Ge in the buffer strain fin portion 2091, because Ge atoms are larger than Si atoms, the buffer strain fin portion 2091 with low Ge concentration contacts the channel fin portion 2092 with higher Ge concentration, which may generate compressive stress in the channel fin portion 2092, and may generate tensile stress in the buffer strain fin portion 2091, and the channel fin portion 2092 has compressive stress therein, which is beneficial to improving carrier mobility in the PMOS.
In other embodiments, the semiconductor structure is an NMOS, the buffer strained fin is SiGe, and the channel fin is Si. The Ge concentration in the channel fin part is lower than that in the buffering strain fin part, the channel fin part grows on the buffering strain fin part, and the channel fin part has tensile stress, so that the carrier mobility in the NMOS can be improved.
The step of forming the buffered strain fin 2091 includes: and forming a buffer strained fin portion 2091 on the substrate 200 exposed out of the dummy fin 201 by using an epitaxial growth method.
The step of forming channel fin 2092 includes: after the buffer strain fin 2091 is formed, a channel fin 2092 is formed on the buffer strain fin 2091 by an epitaxial growth process. In other embodiments, a channel fin portion material layer is formed on the buffer strain fin portion by the epitaxial growth method, covers the dummy fin portion, and is etched back to a partial thickness to form a channel fin portion.
It should be noted that the ratio of the height of the strain relief fin 2091 to the height of the fin 209 is not too large or too small. If the ratio is too large, the process time to form the buffered strain fin 2091 is too long. If the ratio is too small, the strain buffer fin 2091 is too short, which may cause too steep a concentration gradient between the strain buffer fin 2091 and the channel fin 2092, and cause too large a stress between the channel fin 2092 and the strain buffer fin 2091, thereby causing the channel fin 2092 to fall off easily. In this embodiment, the height of the strain relief fin 2091 is one third to two thirds of the height of the fin 209.
Referring to fig. 18, an isolation structure 211 is formed on the substrate 200 where the fin 209 is exposed.
In this embodiment, the isolation structure 211 covers a portion of the sidewalls of the channel fin 2092. In other embodiments, a portion of the sidewall of the isolation structure covering the buffered strained fin portion; or the top surface of the isolation structure is flush with the top surface of the buffer strain fin portion.
Referring to fig. 19, a gate structure 212 is formed to cross the fin 209, and the gate structure 212 covers a portion of the top surface and a portion of the sidewall of the fin 209.
The gate structure 212 is a polysilicon gate structure or a metal gate structure. The gate structure 212 is used to control the opening and closing of the channel in the fin 209 during semiconductor operation.
For the specific description of the forming method in this embodiment, reference may be made to the related description of the first embodiment, and details are not repeated in this embodiment.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 15, a schematic diagram of a first embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100; an isolation layer 102 separated from the substrate 100; a fin 109 on the isolation layer 102; an isolation structure 111 located on the substrate 100 where the fin 109 is exposed, wherein the isolation structure 111 covers a portion of a sidewall of the fin 109; and a gate structure 112 crossing the fin 109 and covering a part of the top surface and a part of the sidewall of the fin 109.
The gate structure 112 can directly control a part of the fin portion 109 covered by the gate structure, and a part of the fin portion 109 located in the isolation structure 111 is not covered by the gate structure, so that the fin portion is not easily directly controlled by the gate structure, and leakage is easily generated between the fin portion 109 located in the isolation structure and the substrate 111.
The substrate 100 is used to provide a process platform for forming semiconductor structures.
In this embodiment, the substrate 100 is made of silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The surface of the substrate 100 may also form an interface layer, and the material of the interface layer is silicon oxide, silicon nitride, silicon oxynitride, or the like.
The isolation layer 102 is used for electrically isolating the fin 109 from the substrate 100, so that the fin 109 is not prone to electric leakage, and the electrical performance of the semiconductor structure is optimized.
In this embodiment, the isolation layer 102 is made of an insulating material.
Specifically, the material of the isolation layer 102 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the isolation layer 102 is made of silicon oxide.
It should be noted that the thickness of the isolation layer 102 is not too thick or too thin. If the isolation layer 102 is too thick, the fin collapse is easily caused. If the isolation layer 102 is too thin, the isolation layer 102 is easily broken, and the isolation layer 102 does not easily electrically isolate the fin 109 from the substrate 100, so that the fin 109 is easily subjected to electric leakage, which is not favorable for optimizing the electrical performance of the semiconductor structure. In this embodiment, the thickness of the isolation layer 102 is 3 nm to 8 nm.
In this embodiment, the semiconductor structure is used to form a PMOS, the fin 109 is made of SiGe, and compared with Si, SiGe can improve carrier mobility in a channel region, which is beneficial to improving electrical performance of the semiconductor structure. In other embodiments, the material of the fin portion may also be Si or Ge.
In this embodiment, the fin 109 includes a bottom fin 1091 and a top fin 1092 on the bottom fin 1091, and the bottom fin 1091 is wider than the top fin 1092 in an extending direction perpendicular to the fin 109.
The sidewalls of the bottom fin portion 1091 are flush with the sidewalls of the isolation layer 102.
It should be noted that, perpendicular to the extending direction of the fins 109, the difference between the widths of the bottom fin 1091 and the top fin 1092 is not too large or too small. If the width difference is too large, the difficulty in forming the fin portion 109 is too large, which is not favorable for increasing the process rate; if the width difference is too small, voids are likely to exist in the fin 109 during the selective epitaxial formation of the material of the fin 109, and leakage is likely to occur. In this embodiment, the difference between the widths of the bottom fin portion 1091 and the top fin portion 1092 is 6 nm to 16 nm.
It should be noted that the height of the top fin 1092 is preferably not too large or too small in proportion to the total height of the fin 109. If the ratio is too high, the speed of selectively epitaxially growing the fin 109 material is too slow, which may result in too long process time; if the ratio is too low, voids are likely to exist in the fin portion 109 during the selective epitaxial formation of the material of the fin portion 109, which reduces the formation quality of the fin portion 109 and is not favorable for improving the electrical performance of the semiconductor structure. In this embodiment, the height of the top fin 1092 is one third to two thirds of the total height of the fin 109.
The isolation structure 111 serves to electrically isolate adjacent fins 109.
In this embodiment, the isolation structure 111 is made of an insulating material.
Specifically, the material of the isolation structure 111 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the isolation structure 111 is made of silicon oxide.
In this embodiment, the gate structure 112 is a polysilicon gate structure or a metal gate structure.
The gate structure 112 is used to control the channel in the fin 109 to be turned on and off during semiconductor operation.
Referring to fig. 19, a schematic diagram of a second embodiment of the semiconductor structure of the present invention is shown. The present embodiment is different from the first embodiment in that: the fin 209 includes a strain relief fin 2091 and a channel fin 2092 on the strain relief fin 2091.
In this embodiment, when the semiconductor structure is a PMOS, the buffer strained fin 2091 and the channel fin 2092 are both made of SiGe, and the molar volume percentage of Ge in the channel fin 2092 is higher than the molar volume percentage of Ge in the buffer strained fin 2091. Because Ge atoms are larger than Si atoms, the buffered strained fin 2091 with low Ge concentration is in contact with the channel fin 2092 with higher Ge concentration, which may generate compressive stress in the channel fin 2092 and tensile stress in the buffered strained fin 2091, and the channel fin 2092 has compressive stress therein, which is beneficial to carrier mobility in PMOS.
In other embodiments, the semiconductor structure is an NMOS, the buffer strained fin is SiGe, and the channel fin is Si. The Ge concentration in the channel fin part is lower than that in the buffering strain fin part, the channel fin part grows on the buffering strain fin part, and the channel fin part has tensile stress, so that the carrier mobility in an NMOS (N-channel metal oxide semiconductor) is facilitated.
The Ge concentration in the strain buffer fin portion 2091 is low (when the semiconductor structure is a PMOS, the Ge concentration in the channel fin portion 2092 is higher than the Ge concentration in the strain buffer fin portion 2091; when the semiconductor structure is an NMOS, the channel fin portion 2092 is made of Si and the strain buffer fin portion 2091 is made of SiGe), and the strain buffer fin portion 2091 can provide sufficient stress for the channel fin portion 2092, so that the carrier transfer rate in the channel fin portion 2092 is fast. The gate structure 212 covers part of the top surface and part of the side walls of the fin portion 209, so that the gate structure 212 can directly control part of the fin portion 209 covered by the gate structure 212, and part of the fin portion 209 located in the isolation structure 211 is not covered by the gate structure 212, and is not easily controlled by the gate structure 212 correspondingly, but because the fin portion 209 is formed on the isolation layer 102, the isolation layer 102 electrically isolates the fin portion 209 from the substrate 200, and even though carriers with high migration rate in the channel fin portion 2092 are carriers, the fin portion 209 located in the gate structure 212 is still not easily electrically connected with the substrate 200, so that the fin portion 209 is not easily subjected to electric leakage, and the electrical performance of the semiconductor structure is optimized.
It should be noted that the ratio of the height of the strain relief fin 2091 to the height of the fin 209 is not too large or too small. If the ratio is too large, the process time for forming the buffered strain fin portion 2091 is too long; if the ratio is too small, the strain buffer fin 2091 is too short, which may cause too steep a concentration gradient between the strain buffer fin 2091 and the channel fin 2092, and cause too large a stress between the channel fin 2092 and the strain buffer fin 2091, thereby causing the channel fin 2092 to fall off easily. In this embodiment, the height of the strain relief fin 2091 is one third to two thirds of the height of the fin 209.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.

Claims (23)

1. A method of forming a semiconductor structure, comprising:
providing a base, wherein the base comprises a substrate and a pseudo fin part positioned on the substrate;
forming an isolation layer on the substrate exposed out of the pseudo fin portion, wherein the isolation layer covers part of the side wall of the pseudo fin portion;
forming a fin part on the isolation layer exposed out of the pseudo fin part;
after the fin part is formed, removing the pseudo fin part;
and after removing the pseudo fin part, forming an isolation structure on the substrate exposed out of the fin part, wherein the isolation structure covers part of the side wall of the fin part.
2. The method of forming a semiconductor structure of claim 1, wherein forming the fin comprises: forming a fin part on the substrate exposed out of the pseudo fin part by adopting an epitaxial growth method; or forming a fin part material layer on the substrate exposed out of the pseudo fin part by adopting an epitaxial growth method, wherein the fin part material layer covers the pseudo fin part; and etching back the fin material layer with a part of thickness to form the fin.
3. The method of forming a semiconductor structure of claim 1,
the dummy fin part is made of Si or Ge, and the fin part is made of SiGe;
or the dummy fin part is made of SiGe and the fin part is made of Si;
or the dummy fin part and the fin part are made of Si;
or, the dummy fin part and the fin part are made of SiGe.
4. The method of claim 1, wherein the dummy fin is removed using one or both of a wet etching process and a dry etching process.
5. The method of forming a semiconductor structure of claim 1, wherein after forming the fin, removing the dummy fin further comprises: forming a fin part mask layer on the fin part; and removing the pseudo fin part by using the fin part mask layer as a mask and adopting a dry etching process.
6. The method of forming a semiconductor structure of claim 1, wherein the step of forming the isolation layer comprises: forming an isolation material layer on the substrate exposed out of the pseudo fin portion, wherein the isolation material layer covers part of the side wall of the pseudo fin portion; etching back the isolation material layer with partial thickness to form the isolation layer;
the method for forming the semiconductor structure further comprises the following steps: after the isolation material layer is formed and before the isolation layer is formed, forming a side wall on the upper side wall of the pseudo fin part exposed out of the isolation material layer;
in the step of forming the fin portions, the fin portions formed between the pseudo fin portions exposed out of the side walls are bottom fin portions, and the fin portions formed between the side walls and the side walls are top fin portions.
7. The method for forming a semiconductor structure according to claim 6, wherein the thickness of the sidewall spacers is 3 nm to 10 nm.
8. The method according to claim 6, wherein the material of the sidewall spacers is one or more selected from the group consisting of SiO, SiN, SiC, SiON, SiBCN, and SiCN.
9. The method for forming a semiconductor structure according to claim 6, wherein the step of forming the side wall comprises: forming a side wall material layer, wherein the side wall material layer conformally covers the isolation material layer and exposes the pseudo fin part of the isolation material layer; and removing the side wall material layer on the isolation material layer and the pseudo fin part to form the side wall.
10. The method of claim 6, wherein a height of the dummy fin covered by the sidewall is one-third to two-thirds of a total height of the dummy fin.
11. The method of forming a semiconductor structure of claim 1, wherein the fin portion comprises a buffered strained fin portion and a channel fin portion on the buffered strained fin portion;
the semiconductor structure is PMOS, the buffer strain fin part and the channel fin part are both made of SiGe, and the molar volume percentage of Ge in the channel fin part is higher than that of Ge in the buffer strain fin part;
or the semiconductor structure is an NMOS, the buffer strain fin part is made of SiGe, and the channel fin part is made of Si;
in the step of forming the isolation structure, the isolation structure covers part of the side wall of the channel fin part; or the top surface of the isolation structure covers part of the side wall of the buffer strain fin part; or the top surface of the isolation structure is flush with the top surface of the buffer strain fin portion.
12. The method of forming a semiconductor structure of claim 11, wherein the step of forming the buffered strained fin portion comprises: forming a buffer strain fin part on the substrate exposed out of the pseudo fin part by adopting an epitaxial growth method;
the step of forming the channel fin includes: after the buffer strain fin part is formed, forming the channel fin part on the buffer strain fin part by adopting an epitaxial growth method;
or forming a channel fin part material layer on the buffer strain fin part by adopting the epitaxial growth method, covering the pseudo fin part by the channel fin part material layer, and etching back the channel fin part material layer with partial thickness to form the channel fin part.
13. The method of forming a semiconductor structure of claim 11, wherein a height of the buffered strained fin is between one-third and two-thirds of a height of the fin.
14. The method of forming a semiconductor structure of claim 1, wherein the spacer layer has a thickness of 3 nm to 8 nm.
15. The method of forming a semiconductor structure of claim 1, wherein a material of the isolation layer comprises one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
16. A semiconductor structure, comprising:
a substrate;
an isolation layer separated from the substrate;
a fin portion located on the isolation layer;
and the isolation structure is positioned on the substrate with the exposed fin part and covers part of the side wall of the fin part.
17. The semiconductor structure of claim 16, wherein the fin includes a bottom fin and a top fin on the bottom fin, the bottom fin being wider than the top fin in a direction perpendicular to an extension of the fin;
the side wall of the bottom fin portion is flush with the side wall of the isolation layer.
18. The semiconductor structure of claim 17, wherein a difference in width between the bottom fin and the top fin is 6 nm to 20 nm perpendicular to an extension direction of the fins.
19. The semiconductor structure of claim 17, wherein a height of the bottom fin is one-third to two-thirds of the fin height.
20. The semiconductor structure of claim 16, wherein the fin comprises a buffered strained fin and a channel fin on the buffered strained fin;
the semiconductor structure is PMOS, the buffer strain fin part and the channel fin part are both made of SiGe, and the molar volume percentage of Ge in the channel fin part is higher than that of Ge in the buffer strain fin part;
or, the semiconductor structure is an NMOS, the buffer strain fin portion is made of SiGe, and the channel fin portion is made of Si.
21. The semiconductor structure of claim 20, wherein a height of the buffered strained fin is one-third to two-thirds of a height of the fin.
22. The semiconductor structure of claim 16, wherein the spacer layer has a thickness of 3 nm to 8 nm.
23. The semiconductor structure of claim 16, wherein a material of the isolation layer comprises one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130037869A1 (en) * 2011-08-10 2013-02-14 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method of semiconductor device
US20170033220A1 (en) * 2015-07-31 2017-02-02 Taiwan Semiconductor Manufacturing Company Semiconductor device including fin structures disposed over buffer structures and manufacturing method thereof
CN106558614A (en) * 2015-09-30 2017-04-05 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN107615490A (en) * 2015-06-26 2018-01-19 英特尔公司 In sacrificial core via cladding transistor fin-shaped into

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130037869A1 (en) * 2011-08-10 2013-02-14 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method of semiconductor device
CN107615490A (en) * 2015-06-26 2018-01-19 英特尔公司 In sacrificial core via cladding transistor fin-shaped into
US20170033220A1 (en) * 2015-07-31 2017-02-02 Taiwan Semiconductor Manufacturing Company Semiconductor device including fin structures disposed over buffer structures and manufacturing method thereof
CN106409680A (en) * 2015-07-31 2017-02-15 台湾积体电路制造股份有限公司 Semiconductor device including fin structures and manufacturing method thereof
CN106558614A (en) * 2015-09-30 2017-04-05 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

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