CN112928164B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN112928164B CN112928164B CN201911236067.4A CN201911236067A CN112928164B CN 112928164 B CN112928164 B CN 112928164B CN 201911236067 A CN201911236067 A CN 201911236067A CN 112928164 B CN112928164 B CN 112928164B
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- 238000000034 method Methods 0.000 title claims abstract description 156
- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 230000008569 process Effects 0.000 claims abstract description 97
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 69
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 239000000463 material Substances 0.000 claims description 40
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 31
- 239000001301 oxygen Substances 0.000 claims description 31
- 229910052760 oxygen Inorganic materials 0.000 claims description 31
- 239000007789 gas Substances 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 20
- 238000009832 plasma treatment Methods 0.000 claims description 4
- 230000005855 radiation Effects 0.000 claims 2
- 230000009286 beneficial effect Effects 0.000 abstract description 15
- 230000015572 biosynthetic process Effects 0.000 abstract description 13
- 239000010410 layer Substances 0.000 description 289
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 230000002349 favourable effect Effects 0.000 description 9
- 230000007547 defect Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 238000009826 distribution Methods 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- 239000006227 byproduct Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 4
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- IFYDWYVPVAMGRO-UHFFFAOYSA-N n-[3-(dimethylamino)propyl]tetradecanamide Chemical compound CCCCCCCCCCCCCC(=O)NCCCN(C)C IFYDWYVPVAMGRO-UHFFFAOYSA-N 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000003949 trap density measurement Methods 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/205—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A semiconductor structure and a method for forming the same, the method for forming the semiconductor structure comprises: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate; forming a first oxide layer on the top and the side wall of the fin part and the surface of the substrate by adopting a plasma enhanced atomic layer deposition process, wherein the output power adopted by the plasma enhanced atomic layer deposition process for forming the first oxide layer is first power; and forming a second oxide layer on the first oxide layer by adopting a plasma enhanced atomic layer deposition process, wherein the output power adopted by the plasma enhanced atomic layer deposition process for forming the second oxide layer is second power, the second power is larger than the first power, and the second oxide layer and the first oxide layer are used for forming a gate oxide layer. The embodiment of the invention is beneficial to improving the formation quality of the gate oxide layer, further beneficial to improving the electrical property of the gate oxide layer and correspondingly optimizing the property of the semiconductor structure.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate structure on the channel is accordingly deteriorated, and the difficulty of pinching off the channel by the gate voltage is also increased, so that the phenomenon of subthreshold leakage (Subthreshold leakage), namely the so-called short channel effect (SCE: short-channel effects) occur more easily.
Accordingly, to reduce the impact of short channel effects, semiconductor processes are gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) from at least two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit short channel effect; and finfets have better compatibility with existing integrated circuit fabrication than other devices.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the forming quality of a gate oxide layer.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate; forming a first oxide layer on the top and the side wall of the fin part and the surface of the substrate by adopting a plasma enhanced atomic layer deposition process, wherein the output power adopted by the plasma enhanced atomic layer deposition process for forming the first oxide layer is first power; and forming a second oxide layer on the first oxide layer by adopting a plasma enhanced atomic layer deposition process, wherein the output power adopted by the plasma enhanced atomic layer deposition process for forming the second oxide layer is second power, the second power is larger than the first power, and the second oxide layer and the first oxide layer are used for forming a gate oxide layer.
Optionally, the method for forming the semiconductor structure further includes: after the first oxide layer is formed, before the second oxide layer is formed on the first oxide layer, the first oxide layer is subjected to first ultraviolet irradiation treatment, so that the compactness of the first oxide layer is improved.
Optionally, the method for forming the semiconductor structure further includes: after the first oxide layer is formed, before the second oxide layer is formed on the first oxide layer, the first oxide layer is subjected to microwave treatment, so that the compactness of the first oxide layer is improved.
Optionally, the first power is 50W to 200W.
Optionally, the second power is 300W to 500W.
Optionally, the thickness of the first oxide layer isTo->
Optionally, the process parameters of the first ultraviolet irradiation treatment include: the temperature is 0 ℃ to 100 ℃ and the irradiation time is 1min to 120min.
Optionally, in the step of forming the second oxide layer, the thickness of the second oxide layer isTo->
Optionally, after the second oxide layer is formed, the method for forming a semiconductor structure further includes: and carrying out second ultraviolet irradiation treatment on the second oxide layer, wherein the second ultraviolet irradiation treatment is suitable for improving the density of the second oxide layer.
Optionally, performing a second ultraviolet irradiation treatment on the second oxide layer in an oxygen-containing gas atmosphere; alternatively, after the second ultraviolet irradiation treatment is performed, the method for forming a semiconductor structure further includes: and performing second plasma treatment on the second oxide layer in an oxygen-containing gas atmosphere.
Optionally, the process parameters of the second ultraviolet irradiation treatment include: the temperature is 0 ℃ to 100 ℃ and the irradiation time is 1min to 120min.
Optionally, the second oxide layer is subjected to a second ultraviolet irradiation treatment in an atmosphere of an oxygen-containing gas, wherein the oxygen-containing gas is oxygen, and the flow rate of the oxygen is 0sccm to 500sccm.
Optionally, the material of the first oxide layer includes silicon oxide.
Optionally, the material of the second oxide layer includes silicon oxide.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: the substrate comprises a substrate and a fin part protruding out of the substrate; the first oxide layer is positioned on the top and the side wall of the fin part and the surface of the substrate, and is formed through a plasma enhanced atomic layer deposition process, and the output power adopted by the plasma enhanced atomic layer deposition process for forming the first oxide layer is first power; the second oxide layer is positioned on the first oxide layer, the second oxide layer is formed through a plasma enhanced atomic layer deposition process, the output power adopted by the plasma enhanced atomic layer deposition process for forming the second oxide layer is second power, the second power is larger than the first power, and the second oxide layer and the first oxide layer form a gate oxide layer.
Optionally, the thickness of the first oxide layer isTo->
Optionally, the thickness of the second oxide layer isTo->
Optionally, the material of the first oxide layer includes silicon oxide.
Optionally, the material of the second oxide layer includes silicon oxide.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming the semiconductor structure, the first oxide layer and the second oxide layer are formed through a plasma enhanced atomic layer deposition process, and the growth modes of the first oxide layer and the second oxide layer are the same, so that the properties (such as internal stress, compactness and the like) of the first oxide layer and the second oxide layer are relatively close, the adhesiveness between the first oxide layer and the second oxide layer is relatively good, interface defects are relatively few, the formation quality of the gate oxide layer is improved, the electrical property of the gate oxide layer is improved, and the performance of the semiconductor structure is correspondingly optimized.
In addition, the output power adopted by the plasma enhanced atomic layer deposition process for forming the first oxide layer is first power, the output power adopted by the plasma enhanced atomic layer deposition process for forming the second oxide layer is second power, and the second power is larger than the first power.
In the alternative, the first oxide layer is further subjected to the first ultraviolet irradiation treatment before the second oxide layer is formed, so that the density of the first oxide layer is improved, the forming quality of the first oxide layer is improved, the higher density of the first oxide layer is also beneficial to improving the blocking effect of the first oxide layer on oxygen-containing gas when the second oxide layer is formed, the fin portion is further prevented from being consumed, the loss of the fin portion is reduced, and the dimension of the fin portion is precisely controlled.
Drawings
Fig. 1 to 3 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
fig. 4 to 8 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention;
FIG. 9 is a TDDB Weber distribution graph of a semiconductor structure formed using a method of an embodiment of the present invention;
FIG. 10 is a graph showing the etch rate of a gate oxide layer formed by a wet etch process per unit time using a method in accordance with an embodiment of the present invention;
fig. 11 is a schematic diagram of a local structure of a fin portion and a gate oxide layer formed by using a forming method according to an embodiment of the present invention, and a consumption amount generated for the fin portion.
Detailed Description
The devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed by combining a forming method of a semiconductor structure.
Referring to fig. 1 to 3, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, a base is provided, the base comprising a substrate 1 and a fin 2 protruding from the substrate 1.
Referring to fig. 2, a thermal oxidation growth process is used to convert the top and sidewall of the fin 2, and a portion of the thickness of the substrate 1 surface, into a first oxide layer 3.
Referring to fig. 3, a second oxide layer 4 is formed on the first oxide layer 3 by using a plasma enhanced atomic layer deposition process, and the second oxide layer 4 and the first oxide layer 3 form a gate oxide layer 5.
In the method for forming the semiconductor structure, the first oxide layer 3 is formed by a thermal oxidation growth process, and the material of the first oxide layer 3 formed by the thermal oxidation growth process has high density and few impurity defects, thereby being beneficial to improving the quality of the gate oxide layer 5 film; the second oxide layer 4 is formed by a plasma enhanced atomic layer deposition process, which is beneficial to reducing the consumption of the fin 2.
However, the first oxide layer 3 and the second oxide layer 4 are formed by different processes, and the materials of the first oxide layer 3 and the second oxide layer 4 are different in characteristics, for example: density, internal stress, etc., which easily causes interface defects at the interface of the first oxide layer 3 and the second oxide layer 4, resulting in poor formation quality of the gate oxide layer 5, and thus easily affecting the electrical properties of the gate oxide layer 5, for example: insulation properties, breakdown resistance, etc., resulting in poor device performance.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate; forming a first oxide layer on the top and the side wall of the fin part and the surface of the substrate by adopting a plasma enhanced atomic layer deposition process, wherein the output power adopted by the plasma enhanced atomic layer deposition process for forming the first oxide layer is first power; and forming a second oxide layer on the first oxide layer by adopting a plasma enhanced atomic layer deposition process, wherein the output power adopted by the plasma enhanced atomic layer deposition process for forming the second oxide layer is second power, the second power is larger than the first power, and the second oxide layer and the first oxide layer are used for forming a gate oxide layer.
In the method for forming the semiconductor structure, the first oxide layer and the second oxide layer are formed through a plasma enhanced atomic layer deposition process, and the growth modes of the first oxide layer and the second oxide layer are the same, so that the properties (such as internal stress, compactness and the like) of the first oxide layer and the second oxide layer are relatively close, the adhesiveness between the first oxide layer and the second oxide layer is relatively good, interface defects are relatively few, the formation quality of the gate oxide layer is improved, the electrical property of the gate oxide layer is improved, and the performance of the semiconductor structure is correspondingly optimized.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 4 to 8 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 4, a base is provided, the base comprising a substrate 100 and a fin 110 protruding from the substrate 100.
The substrate 100 provides a process platform for a process recipe.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates.
The fin 110 is used to provide a conductive channel for a fin field effect transistor (FinFET) during operation.
In this embodiment, the material of the fin portion 110 is the same as the material of the substrate 100, and the material of the fin portion 110 is silicon. In other embodiments, the material of the fin portion may be a semiconductor material suitable for forming the fin portion, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the fin portion may be different from the material of the substrate.
Referring to fig. 5, a first oxide layer 120 is formed on the top and the sidewall of the fin 110 and the surface of the substrate 100 by using a plasma enhanced atomic layer deposition process, and the output power used by the plasma enhanced atomic layer deposition process for forming the first oxide layer 120 is the first power.
The first oxide layer 120 is used to form a gate oxide layer.
In this embodiment, the material of the first oxide layer 120 is silicon oxide. Silicon oxide is a gate oxide material commonly used in semiconductor processes, which is beneficial to improving process compatibility.
In this embodiment, the first oxide layer 120 is formed by an atomic layer deposition process. The atomic layer deposition process is based on Self-limiting reaction process of atomic layer deposition process, and the film obtained by deposition can reach the thickness of single-layer atoms, because the atomic layer deposition process can accurately deposit one atomic layer in each period, the atomic layer deposition process is selected to be favorable for accurately controlling the thickness of the first oxide layer 120 and enabling the thickness of the first oxide layer 120 to be smaller so as to meet the process requirements, and in addition, the film prepared by ALD process has the characteristics of good bonding strength, consistent film layer thickness, good component uniformity, good shape retention and the like, and is favorable for improving the thickness uniformity and film quality of the first oxide layer 120.
Specifically, the first oxide layer 120 is formed using a plasma enhanced atomic layer deposition (Plasma enhanced atomic layer deposition, PEALD) process. By selecting a plasma enhanced atomic layer deposition process, the consumption of the fin 110 is further reduced.
The output power of the plasma enhanced atomic layer deposition process for forming the first oxide layer 120 is the first power. The first power is not excessively high, the output power is used to control the energy carried by the plasma, if the first power is excessively high, the energy of the plasma reaching the surface of the fin 110 is relatively high, which easily causes excessive consumption of the fin 110, on the one hand, and the plasma is directional to the fin 110, if the first power is excessively high, the anisotropy of the plasma is relatively high, and compared with the plasma contacting the top surface of the fin 110, the plasma contacting the side wall of the fin 110 is relatively less, which easily causes relatively low uniformity of the thickness of the first oxide layer 120 formed on the top of the fin 110 and the side wall of the fin 110. For this reason, in this embodiment, the first power is less than or equal to 200W, so that the thickness uniformity of the first oxide layer 120 is improved while reducing the consumption of the fin 110.
Specifically, in this embodiment, the first power is 50W to 200W.
The thickness of the first oxide layer 120 is not too small nor too large. If the thickness of the first oxide layer 120 is too small, it is easy to cause poor film quality of the first oxide layer 120, for example: poor film continuity, high defect density, etc., and moreover,the output power adopted in the subsequent formation of the second oxide layer on the first oxide layer 120 through the plasma enhanced atomic layer deposition process is second power, the second power is larger than the first power, and the blocking effect of the first oxide layer 120 on the oxygen-containing gas in the formation of the second oxide layer is easily reduced due to the excessively small thickness of the first oxide layer 120; if the thickness of the first oxide layer 120 is too large, a second oxide layer is formed on the first oxide layer 120, the second oxide layer and the first oxide layer 120 are used for forming a gate oxide layer, the thickness of the first oxide layer 120 is too large, the thickness of the gate oxide layer is easy to be too large, the thickness of the first oxide layer 120 is too large, the consumption of the fin portion 110 is easy to be too much, and the first oxide layer 120 is further subjected to ultraviolet irradiation treatment to improve the compactness of the first oxide layer 120, the thickness of the first oxide layer 120 is too large, ultraviolet is difficult to penetrate the first oxide layer 120, and incomplete treatment or poor treatment uniformity of the first oxide layer 120 are easy to be caused. For this purpose, in this embodiment, the thickness of the first oxide layer 120 isTo->For example:etc.
Referring to fig. 6 in combination, the method for forming the semiconductor structure further includes: after the first oxide layer 120 is formed, a first ultraviolet (UV cure) treatment 130 is performed on the first oxide layer 120, which is adapted to increase the density of the first oxide layer 120.
By performing the first ultraviolet irradiation (UV cure) 130 on the first oxide layer 120, the density of the first oxide layer 120 is improved, which is favorable for improving the film quality of the first oxide layer 120, and the density of the first oxide layer 120 is higher, which is favorable for improving the blocking effect of the first oxide layer 120 on the oxygen-containing gas in the subsequent step of forming the second oxide layer, and further is favorable for reducing the consumption of the fin portion 110 generated during the subsequent step of forming the second oxide layer.
Furthermore, the ultraviolet rays have high energy, and by performing the ultraviolet irradiation 130 on the first oxide layer 120, the ultraviolet rays can generate less consumption of the fin portion 110, and by-products (e.g., -CH) in the first oxide layer 120 2 CH 3 By-product) and the by-product is diffused from the first oxide layer 120, thereby reducing the content of impurities such as the by-product in the first oxide layer 120, improving the bonding probability of silicon-oxygen bonds in the first oxide layer 120, correspondingly improving the density of the first oxide layer 120, and further improving the film quality of the first oxide layer 120.
In addition, by performing the first ultraviolet irradiation (UV cure) process 130, it is also advantageous to improve the density of the first oxide layer 120 without consuming the fin 110.
The temperature of the first ultraviolet irradiation treatment 130 is not preferably too low nor too high. If the temperature of the first ultraviolet irradiation treatment 130 is too low, the treatment rate and treatment effect of the first ultraviolet irradiation treatment 130 are easily lowered; if the temperature of the first ultraviolet irradiation treatment 130 is too high, damage to the structure of the fin 110 is likely to occur. For this reason, in the present embodiment, if the temperature of the first ultraviolet irradiation treatment 130 is 0 ℃ to 100 ℃, for example: 10 ℃,20 ℃,30 ℃ and the like
In the present embodiment, the irradiation time of the first ultraviolet irradiation treatment 130 is 1min to 120min.
In the present embodiment, after the first oxide layer 120 is formed, the first oxide layer 120 is subjected to a first ultraviolet irradiation (UV cure) treatment 130, and the densification of the first oxide layer 120 is suitably improved.
In other embodiments, the method for forming a semiconductor structure further includes: after the first oxide layer is formed, before the second oxide layer is formed on the first oxide layer, the first oxide layer is subjected to microwave treatment, so that the compactness of the first oxide layer is improved.
The microwave treatment can generate high-energy microwaves, break the connection bonds of byproducts in the buffer layer, remove impurities in the buffer layer, and further improve the density of the first oxide layer and the quality of the film.
Referring to fig. 7, a second oxide layer 140 is formed on the first oxide layer 120 by using a plasma enhanced atomic layer deposition process, and an output power used by the plasma enhanced atomic layer deposition process for forming the second oxide layer 140 is a second power, where the second power is greater than the first power, and the second oxide layer 140 and the first oxide layer 120 are used to form a gate oxide layer 150.
In the embodiment of the present invention, the first oxide layer 120 and the second oxide layer 140 are formed by a plasma enhanced atomic layer deposition process, and the growth modes of the first oxide layer 120 and the second oxide layer 140 are the same, so that the properties (such as internal stress, quality, etc.) of the materials of the first oxide layer 120 and the second oxide layer 140 are relatively close, the adhesion between the first oxide layer 120 and the second oxide layer 140 is relatively good, and the interface defects are relatively few, thereby being beneficial to improving the formation quality of the gate oxide layer 150, further being beneficial to improving the electrical property of the gate oxide layer 150, and correspondingly optimizing the performance of the semiconductor structure.
In this embodiment, the material of the second oxide layer 140 is the same as the material of the first oxide layer 120, and the material of the second oxide layer 140 is silicon oxide, which is beneficial to improving the process compatibility.
In this embodiment, the second oxide layer 140 is formed by an atomic layer deposition process. The atomic layer deposition process is based on Self-limiting reaction process of atomic layer deposition process, and the film obtained by deposition can reach the thickness of single-layer atoms, because the atomic layer deposition process can accurately deposit one atomic layer in each period, the atomic layer deposition process is selected to be favorable for accurately controlling the thickness of the second oxide layer 140 and making the thickness of the second oxide layer 140 smaller so as to meet the process requirements, and in addition, the film prepared by ALD process has the characteristics of good bonding strength, consistent film layer thickness, good component uniformity, good shape retention and the like, and is favorable for improving the thickness uniformity and film quality of the second oxide layer 140.
In this embodiment, the second oxide layer 140 is formed using a plasma enhanced atomic layer deposition (Plasma enhanced atomic layerdeposition, PEALD) process. By selecting a plasma enhanced atomic layer deposition process, the consumption of the fin 110 is further reduced.
By making the second power greater than the first power, that is, by forming the first oxide layer 120 with a lower output power and then forming the second oxide layer 140 with a higher output power, the formation quality of the second oxide layer 140 is advantageously improved compared to directly forming the gate oxide layer with a plasma enhanced atomic layer deposition process and using a higher output power with a plasma enhanced atomic layer deposition process, and the first oxide layer 120 can act as a barrier to the oxygen-containing gas when forming the second oxide layer 140, so that even if the second oxide layer 140 is formed with a higher output power, the loss generated to the fin 110 is smaller, and in addition, the oxygen-containing gas used when forming the second oxide layer 140 can also react with the first oxide layer 120, thereby further improving the compactness of the first oxide layer 120.
Therefore, the second power is not too low, otherwise it is difficult to ensure that the second oxide layer 140 has a high formation quality. For this purpose, in this embodiment, the second power is at least 300W.
Specifically, in this embodiment, the second power is 300W to 500W, so that the process compatibility is improved and the consumption of the fin 110 is reduced while the second oxide layer 140 has higher film quality.
In this embodiment, the thickness of the second oxide layer 140 is as follows, according to the required thickness of the gate oxide layer 150 and the thickness of the first oxide layer 120To->For example: />Etc.
Referring to fig. 8 in combination, after forming the second oxide layer 140, the method for forming a semiconductor structure further includes: the second oxide layer 140 is subjected to a second ultraviolet irradiation treatment 160, which is adapted to increase the density of the second oxide layer 140.
The temperature of the second ultraviolet irradiation treatment 160 is not preferably too low nor too high. If the temperature of the second ultraviolet irradiation treatment 160 is too low, the treatment rate and treatment effect of the second ultraviolet irradiation treatment 160 are easily lowered; if the temperature of the second ultraviolet irradiation process 160 is too high, damage to the structure of the fin 110 may easily occur. For this reason, in the present embodiment, the temperature of the second ultraviolet irradiation treatment 160 is 0 ℃ to 100 ℃, for example: 10 ℃,20 ℃,30 ℃ and the like
In this embodiment, the irradiation time of the second ultraviolet irradiation treatment 160 is 1min to 120min.
In this embodiment, the second oxide layer 140 is subjected to a second ultraviolet irradiation treatment 160 in an oxygen-containing gas atmosphere.
By performing the second ultraviolet irradiation treatment 160 in an oxygen-containing gas atmosphere, the bonding amount of silicon and oxygen in the second oxide layer 140 is advantageously increased, and further, the density of the second oxide layer 140 is advantageously further increased.
In this embodiment, the second ultraviolet irradiation 160 is performed on the second oxide layer 140 in an atmosphere of an oxygen-containing gas, and the oxygen-containing gas is preferably oxygen, and the flow rate of the oxygen gas is preferably not too small or too large. If the gas flow rate of the oxygen is too small, the effect of improving the density of the second oxide layer 140 is not obvious easily; if the flow of oxygen is too high, the fin 110 is easily consumed. For this reason, in the present embodiment, the gas flow rate of the oxygen is 0sccm to 500sccm, for example: 100sccm,150sccm,200sccm,300sccm, etc.
In the present embodiment, the second ultraviolet irradiation treatment 160 is performed on the second oxide layer 140 in an oxygen-containing gas atmosphere. In other embodiments, after the second ultraviolet irradiation treatment, the method for forming a semiconductor structure may further include: and performing second plasma treatment on the second oxide layer in an oxygen-containing gas atmosphere.
The second plasma treatment is performed on the second oxide layer in an oxygen-containing gas atmosphere after the second ultraviolet irradiation treatment, which is also beneficial to improving the density of the second oxide layer.
The method further comprises the following steps of forming a gate structure crossing the fin portion 110 on the gate oxide layer 150, and forming source-drain doped regions in the fin portion 110 at two sides of the gate structure. The following process steps are not described in detail here.
Referring to fig. 9 in combination, curve #2 in fig. 9 shows a TDDB (Time Dependent Dielectric Breakdown ) weibull distribution (Weibull Distribution) plot for a semiconductor structure formed using a method of an embodiment of the present invention, and curve #1 shows a TDDB weibull distribution plot for a semiconductor structure formed in accordance with the prior art. The abscissa is Time to Failure (unit: seconds). As can be seen from FIG. 9, the TDDB weibull distribution curve of the semiconductor structure formed by the embodiment of the invention has a larger slope beta and R than the TDDB weibull distribution curve of the semiconductor structure of the prior art 2 (Coefficient of determination, determining coefficient) is closer to 1, and the reliability of the semiconductor structure formed by the embodiment of the invention is better.
Referring to table 1 in combination, there are shown some of the electrical parameters of a semiconductor structure formed using the method of an embodiment of the present invention, and some of the electrical parameters of a semiconductor structure formed using the prior art.
As can be seen from table 1, compared with the semiconductor structure formed by the prior art, the equivalent electrical thickness (EOT) of the semiconductor structure of the embodiment of the present invention is smaller, and the interface trap density (Interfacial trap density, DIT) and the contact potential difference (Contact potential difference voltage, vcpd) are also smaller, which indicates that the film quality of the gate oxide layer 150 formed by the embodiment of the present invention is better, the electrical performance is better, and the performance of the semiconductor structure is improved by the method of the embodiment of the present invention.
| Electrical parameters | Embodiments of the invention | Prior Art |
| EOT[50A] | 40.52 | 42.80 |
| DIT[1/cm2*eV] | 1.08E+12 | 2.15E+12 |
| Vcpd[V]Avg | -0.05 | -0.33 |
TABLE 1
Referring to fig. 10 in combination, the Wet Etching Rate (WER) of the Wet etching process for the gate oxide layer formed by the method according to the embodiment of the present invention and the Wet etching rate of the Wet etching process for the gate oxide layer formed by the prior art are shown, and as can be seen from fig. 10, the etching rate of hydrofluoric acid (DHF) for the gate oxide layer according to the embodiment of the present invention isHydrofluoric acid in unit time to the prior artThe etching rate of the gate oxide layer formed by the technology is +.>Compared with the prior art, the etching rate of hydrofluoric acid (DHF) to the gate oxide layer in the embodiment of the invention is lower in unit time, which indicates that the gate oxide layer formed in the embodiment of the invention is more resistant to etching, and the film quality (for example, density) of the gate oxide layer formed in the embodiment of the invention is better.
Referring to fig. 11 in combination, a schematic diagram of a local structure of a fin portion and a gate oxide layer formed by using the forming method according to the embodiment of the present invention and a consumption amount generated for the fin portion 110 are shown, and fig. 11 also shows a schematic diagram of a structure of a fin portion and a gate oxide layer formed by using the first and second prior arts, respectively, and a consumption amount generated for the fin portion. Taking the material of the fin part as silicon and the material of the silicon oxide as an example, wherein Bare Si represents the fin part; the oxidation represents a natural oxide layer formed on the surface of the fin part; in the first prior art, thermal OX represents silicon oxide formed by a Thermal oxidation growth process, and High Power ALDOX represents silicon oxide formed by a plasma enhanced atomic layer deposition process with higher output Power; in the second prior art, high Power ALDOX represents silicon oxide formed by adopting a plasma enhanced atomic layer deposition process with higher output Power in the second prior art; in the embodiment of the present invention, low Power ALDOX indicates that the embodiment of the present invention uses silicon oxide formed by a plasma enhanced atomic layer deposition process with a lower output Power as the first oxide layer, and High Power ALDOX indicates that the embodiment of the present invention uses silicon oxide formed by a plasma enhanced atomic layer deposition process with a higher output Power as the second oxide layer.
As can be seen from FIG. 11, the gate oxide layer is formed by the method of the first prior art, and the loss to silicon (SiLoss) isThat is, the formation of the gate oxide layer by the method of the first prior art produces the fin portionIs +.>Forming a gate oxide layer by a method of the second prior art, wherein the Loss (Si Loss) of silicon is +.>That is, the formation of the gate oxide layer by the method of the second prior art results in a loss of +.>The gate oxide layer 160 is formed by the method of the embodiment of the invention, and the loss (SiLoss) of silicon is +.>That is, the method of the embodiment of the present invention is adopted to form the gate oxide 160 to generate about +.>The consumption of the fin portion 110 can be remarkably reduced by adopting the method of the embodiment of the invention.
Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 8, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a base, wherein the base includes a substrate 100 and a fin portion 110 protruding from the substrate 100; the first oxide layer 120 is located on the top and the side wall of the fin portion 110 and on the surface of the substrate 100, the first oxide layer 120 is formed by a plasma enhanced atomic layer deposition process, and the output power adopted by the plasma enhanced atomic layer deposition process for forming the first oxide layer 120 is a first power; the second oxide layer 140 is located on the first oxide layer 120, the second oxide layer 140 is formed by a plasma enhanced atomic layer deposition process, the output power adopted by the plasma enhanced atomic layer deposition process for forming the second oxide layer 140 is a second power, the second power is greater than the first power, and the second oxide layer 140 and the first oxide layer 120 form a gate oxide layer 150.
In the embodiment of the present invention, the first oxide layer 120 and the second oxide layer 140 are formed by a plasma enhanced atomic layer deposition process, and the growth modes of the first oxide layer 120 and the second oxide layer 140 are the same, so that the properties (such as internal stress, quality, etc.) of the materials of the first oxide layer 120 and the second oxide layer 140 are relatively close, the adhesion between the first oxide layer 120 and the second oxide layer 140 is relatively good, and the interface defects are relatively few, thereby being beneficial to improving the formation quality of the gate oxide layer 150, further being beneficial to improving the electrical property of the gate oxide layer 150, and correspondingly optimizing the performance of the semiconductor structure.
The substrate 100 provides a process platform for a process recipe.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates.
The fin 110 is used to provide a conductive channel for a fin field effect transistor (FinFET) during operation.
In this embodiment, the material of the fin portion 110 is the same as the material of the substrate 100, and the material of the fin portion 110 is silicon. In other embodiments, the material of the fin portion may be a semiconductor material suitable for forming the fin portion, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the fin portion may be different from the material of the substrate.
In this embodiment, the material of the first oxide layer 120 is silicon oxide. Silicon oxide is a gate oxide material commonly used in semiconductor processes, which is beneficial to improving process compatibility.
The first oxide layer 120 is formed by a plasma enhanced atomic layer deposition process, which is favorable for precisely controlling the thickness of the first oxide layer 120 and making the thickness of the first oxide layer 120 smaller to meet the process requirements.
The first power is smaller than the second power, and the first power is smaller, which is beneficial to reducing the consumption of the fin 110 when the first oxide layer 120 is formed and improving the thickness uniformity of the first oxide layer 120.
The thickness of the first oxide layer 120 is not too small nor too large. If the thickness of the first oxide layer 120 is too small, it is easy to cause poor film quality of the first oxide layer 120, for example: the film continuity is poor, the defect density is high, etc., and the output power of the plasma enhanced atomic layer deposition process when forming the second oxide layer 140 is a second power, the second power is larger than the first power, and the thickness of the first oxide layer 120 is too small, so that the blocking effect of the first oxide layer 120 on the oxygen-containing gas when forming the second oxide layer 140 is easily reduced; if the thickness of the first oxide layer 120 is too large, the thickness of the gate oxide layer 150 is easily too large, and the thickness of the first oxide layer 120 is also easily too large to consume the fin 110 too much. For this purpose, in this embodiment, the thickness of the first oxide layer 120 isTo->For example:etc.
In this embodiment, the material of the second oxide layer 140 is the same as the material of the first oxide layer 120, and the material of the second oxide layer 140 is silicon oxide, which is beneficial to improving the process compatibility.
The second oxide layer 140 is formed by a plasma enhanced atomic layer deposition process, which is favorable for precisely controlling the thickness of the second oxide layer 140 and making the thickness of the second oxide layer 140 smaller to meet the process requirements.
By making the second power larger than the first power, the second power is made larger, which is advantageous to improve the formation quality of the second oxide layer 140, and in addition, the oxygen-containing gas used in forming the second oxide layer 140 can also react with the first oxide layer 120, thereby further improving the density of the first oxide layer 120.
In this embodiment, the thickness of the second oxide layer 140 is as follows, according to the required thickness of the gate oxide layer 150 and the thickness of the first oxide layer 120To->For example: />Etc.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (19)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate;
forming a first oxide layer on the top and the side wall of the fin part and the surface of the substrate by adopting a plasma enhanced atomic layer deposition process, wherein the output power adopted by the plasma enhanced atomic layer deposition process for forming the first oxide layer is first power;
and forming a second oxide layer on the first oxide layer by adopting a plasma enhanced atomic layer deposition process, wherein the output power adopted by the plasma enhanced atomic layer deposition process for forming the second oxide layer is second power, the second power is larger than the first power, and the second oxide layer and the first oxide layer are used for forming a gate oxide layer.
2. The method of forming a semiconductor structure of claim 1, further comprising: after the first oxide layer is formed, before the second oxide layer is formed on the first oxide layer, the first oxide layer is subjected to first ultraviolet irradiation treatment, so that the compactness of the first oxide layer is improved.
3. The method of forming a semiconductor structure of claim 1, further comprising: after the first oxide layer is formed, before the second oxide layer is formed on the first oxide layer, the first oxide layer is subjected to microwave treatment, so that the compactness of the first oxide layer is improved.
4. The method of forming a semiconductor structure of claim 1, wherein the first power is 50W to 200W.
5. The method of forming a semiconductor structure of claim 1, wherein the second power is 300W to 500W.
6. The method of forming a semiconductor structure according to claim 1, wherein the first oxide layer has a thickness ofTo->
7. The method of forming a semiconductor structure of claim 2, wherein the process parameters of the first ultraviolet radiation treatment comprise: the temperature is 0 ℃ to 100 ℃ and the irradiation time is 1min to 120min.
8. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming the second oxide layer, a thickness of the second oxide layer isTo->
9. The method of forming a semiconductor structure of claim 1, wherein after forming the second oxide layer, the method of forming a semiconductor structure further comprises: and carrying out second ultraviolet irradiation treatment on the second oxide layer, wherein the second ultraviolet irradiation treatment is suitable for improving the density of the second oxide layer.
10. The method for forming a semiconductor structure according to claim 9, wherein the second oxide layer is subjected to a second ultraviolet irradiation treatment in an oxygen-containing gas atmosphere;
alternatively, after the second ultraviolet irradiation treatment is performed, the method for forming a semiconductor structure further includes: and performing second plasma treatment on the second oxide layer in an oxygen-containing gas atmosphere.
11. The method of forming a semiconductor structure of claim 9, wherein the process parameters of the second ultraviolet radiation treatment comprise: the temperature is 0 ℃ to 100 ℃ and the irradiation time is 1min to 120min.
12. The method according to claim 10, wherein the second oxide layer is subjected to a second ultraviolet irradiation treatment in an atmosphere containing oxygen, wherein the oxygen-containing gas is oxygen, and a gas flow rate of the oxygen is 0sccm to 500sccm.
13. The method of forming a semiconductor structure of claim 1, wherein the material of the first oxide layer comprises silicon oxide.
14. The method of forming a semiconductor structure of claim 1, wherein the material of the second oxide layer comprises silicon oxide.
15. A semiconductor structure, comprising:
the substrate comprises a substrate and a fin part protruding out of the substrate;
the first oxide layer is positioned on the top and the side wall of the fin part and the surface of the substrate, and is formed through a plasma enhanced atomic layer deposition process, and the output power adopted by the plasma enhanced atomic layer deposition process for forming the first oxide layer is first power;
the second oxide layer is positioned on the first oxide layer, the second oxide layer is formed through a plasma enhanced atomic layer deposition process, the output power adopted by the plasma enhanced atomic layer deposition process for forming the second oxide layer is second power, the second power is larger than the first power, and the second oxide layer and the first oxide layer form a gate oxide layer.
16. The semiconductor structure of claim 15, wherein a thickness of the first oxide layer isTo the point of
17. The semiconductor structure of claim 15, wherein the second oxide layer has a thickness ofTo the point of
18. The semiconductor structure of claim 15, wherein the material of the first oxide layer comprises silicon oxide.
19. The semiconductor structure of claim 15, wherein the material of the second oxide layer comprises silicon oxide.
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| CN106847685A (en) * | 2015-12-07 | 2017-06-13 | 中芯国际集成电路制造(上海)有限公司 | The forming method of high-K metal gate transistor |
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