CN112889130A - 半导体器件的封装方法 - Google Patents
半导体器件的封装方法 Download PDFInfo
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- CN112889130A CN112889130A CN201880098913.8A CN201880098913A CN112889130A CN 112889130 A CN112889130 A CN 112889130A CN 201880098913 A CN201880098913 A CN 201880098913A CN 112889130 A CN112889130 A CN 112889130A
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- Prior art keywords
- voltage
- semiconductor substrate
- controller
- conductive layer
- time delay
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000004806 packaging method and process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 239000002245 particle Substances 0.000 claims description 19
- 230000005855 radiation Effects 0.000 claims description 17
- 239000002800 charge carrier Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 238000005224 laser annealing Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 7
- 239000010931 gold Substances 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 238000005192 partition Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000002123 temporal effect Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910004613 CdTe Inorganic materials 0.000 description 1
- 229910004611 CdZnTe Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000009738 saturating Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- -1 silicon nitride Chemical class 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
本文公开了一种方法,所述方法包括:在半导体衬底的第一表面上形成第一导电层,其中第一导电层与半导体电接触;在第一导电层处,将支撑晶片接合到半导体衬底;使半导体衬底变薄。
Description
【技术领域】
本公开涉及半导体器件的封装方法。
【背景技术】
随着电子应用尺寸的缩小,集成电路(IC)封装器件的占地面积和厚度都减小了。驱动较小封装的开发的是对诸如存储卡、智能卡、蜂窝电话和便携式计算等便携式通信器件的需求。
【发明内容】
本文公开了一种方法,所述方法包括:在半导体衬底的第一表面上形成第一导电层,其中所述第一导电层与所述半导体电接触;在所述第一导电层处,将支撑晶片接合到所述半导体衬底;使所述半导体衬底变薄。
根据实施例,所述方法还包括在所述半导体衬底的与所述第一表面相对的第二表面上形成电触点。
根据实施例,所述方法还包括:获得其中具有电路的芯片;通过在所述第二表面处将所述芯片接合到所述半导体衬底,将所述电路电连接到所述电触点。
根据实施例,所述方法还包括封装所述芯片和所述半导体衬底。
根据实施例,所述方法还包括通过去除所述支撑晶片来暴露所述第一导电层的至少一部分。
根据实施例,所述方法还包括在所述半导体衬底中形成p-n结或p-i-n结。
根据实施例,所述第一表面是抛光的。
根据实施例,所述第一导电层包含金属。
根据实施例,所述金属包括Al、Au或其组合。
根据实施例,所述支撑晶片包含氧化硅层。
根据实施例,所述支撑晶片包含在接合之后与所述第一导电层接触的第二导电层。
根据实施例,所述方法还包括对所述半导体衬底进行激光退火。
根据实施例,所述方法还包括使所述半导体衬底变薄,使所述半导体衬底变薄包括在所述半导体衬底上进行化学机械平坦化,蚀刻所述半导体衬底或两者。
根据实施例,所述方法还包括将所述第一导电层电接地。
根据实施例,所述电路包括被配置为处理或分析从所述半导体衬底产生的电信号的电子系统。
根据实施例,所述电子系统包括接触垫。
根据实施例,所述电子系统包括:第一电压比较器,被配置为将所述接触垫的电压与第一阈值进行比较;第二电压比较器,被配置为将所述电压与第二阈值进行比较;计数器,被配置为记录由所述衬底吸收的辐射粒子的数量;控制器;其中,所述控制器被配置为从所述第一电压比较器确定所述电压的绝对值等于或超过所述第一阈值的绝对值的时间开始时间延迟;其中,所述控制器被配置为在所述时间延迟期间激活所述第二电压比较器;其中,所述控制器被配置为:如果所述第二电压比较器确定所述电压的绝对值等于或超过所述第二阈值的绝对值,则使所述计数器记录的数量增加1。
根据实施例,所述电子系统还包括电连接到所述接触垫的积分器,其中所述积分器被配置为从所述接触垫收集电荷载流子。
根据实施例,所述控制器被配置为在所述时间延迟开始或期满时激活所述第二电压比较器。
根据实施例,所述电子系统还包括电压表,其中所述控制器被配置为使得所述电压表在所述时间延迟期满时测量所述电压。
根据实施例,所述控制器被配置为基于在所述时间延迟期满时测量的电压值来确定辐射粒子的能量。
根据实施例,所述控制器被配置为将所述接触垫连接到电接地。
根据实施例,在所述时间延迟期满时,所述电压的变化率基本上为零。
根据实施例,在所述时间延迟期满时,所述电压的变化率基本上不为零。
【附图说明】
图1示意性地示出了半导体衬底的示例性横截面图。
图2A至图2G示意性地示出了根据实施例的方法。
图3A和图3B均示出了电子系统的组件图。
图4示意性地示出了流过半导体衬底的电触点的电流的时间变化(上部曲线),以及电触点的电压的相应时间变化(下部曲线),该电流是由入射在半导体衬底上的辐射粒子产生的电荷载流子引起的。
【具体实施方式】
图1示意性地示出了半导体衬底110的横截面图。衬底110具有第一表面110A和第二表面110B。第二表面110B与第一表面110A相对。第一表面110A、第二表面110B或两者可以是抛光的。衬底110的半导体可以是硅、锗、GaAs、CdTe、CdZnTe或其组合。衬底110的半导体可以是其他合适的半导体材料。衬底可以包括第一掺杂区111和本征区112。第一掺杂区111可以小于10微米厚。衬底110的总厚度可以是几百微米。
图2A至图2G示意性地示出了根据实施例的方法。
图2A示意性地示出了在衬底110的第一表面110A上形成第一导电层130。第一导电层130与衬底110电接触。如果存在第一掺杂区111,则第一导电层130可以与第一掺杂区111电接触。第一导电层130可以包含金属,比如Al、Au或其组合。第一导电层130可以包含其他合适的材料。第一导电层130的厚度可以小于1微米。
图2B示意性地示出了支撑晶片140在第一导电层130处接合到衬底110。支撑晶片140可以包含绝缘体层142。绝缘体可以是诸如氧化硅之类的氧化物,诸如氮化硅之类的氮化物,诸如氮氧化硅的氮氧化物,或其他合适的材料。支撑晶片140可以包含半导体层141。支撑晶片140可以包含在接合之后与第一导电层130接触的第二导电层143。第二导电层143包含金属,比如Al、Au或其组合。第二导电层143可以包含其他合适的材料。可以通过直接接合来接合支撑晶片140和衬底110。直接接合可以在高温下进行,但不一定如此。
图2C示意性地示出了衬底110可以被变薄。使衬底110变薄可以通过在衬底110的第二表面110B上进行化学机械平坦化、湿法蚀刻或其组合来进行。例如,变薄之后的衬底110可以具有200微米以下、100微米以下,50微米以下、20微米以下或5微米以下的厚度。第一导电层130可以被电接地。
图2D示意性地示出了电触点119可以形成在衬底110的第二表面110B上。图2D还示意性地示出了可以在衬底110中形成p-n结或p-i-n结。在第一掺杂区111存在于衬底中的示例中,具有离散部分114的第二掺杂区113可以形成在衬底110中。如果存在本征区112,则第二掺杂区113可以通过本征区112与第一掺杂区111分离。如果存在本征区112,则离散部分114可以通过第一掺杂区111或本征区112彼此分离。第一掺杂区111和第二掺杂区113具有相反类型的掺杂(例如,区域111是p型,区域113是n型,或者,区域111是n型,区域113是p型)。第二掺杂区113的各离散部分114与第一掺杂区111形成p-n结,或者与第一掺杂区111和本征区112形成p-i-n结。第一掺杂区111也可以具有离散部分。电触点119可以是金、铜、铂、钯、掺杂硅或其他合适的材料。电触点119可以分别与离散部分114电接触。在一个实施例中,例如在形成第二掺杂区113之后,在衬底110上进行激光退火。
图2E和图2F示意性地示出了可以获得其中包括电路的芯片120,并且电路可以电连接到电触点119,例如,通过在第二表面110B处将芯片120接合到衬底110。将芯片120接合到衬底110可以通过合适的技术,例如直接接合或倒装芯片接合。该电路可以包括被配置为处理或分析从衬底110产生的电信号的电子系统121。电子系统121可以包括接触垫125。接触垫125可以被配置为电连接到衬底110的电触点119之一。接触垫125可以是金属层或掺杂半导体层。例如,接触垫125可以是金、铜、铂、钯、掺杂硅等。
图2G示意性地示出了可以通过去除支撑晶片140来暴露第一导电层130的至少一部分。例如,可以将支撑晶片140磨掉,蚀刻掉或者与衬底110分离。图2G还示意性地示出了芯片120和衬底110可以被封装在例如矩阵925中。矩阵925可以是聚合物、玻璃或其他合适的材料。
图3A和图3B均示出了根据实施例的电子系统121的组件图。电子系统121可以包括第一电压比较器301、第二电压比较器302、计数器320、开关305、电压表306和控制器310。
第一电压比较器301被配置为将接触垫125的电压与第一阈值进行比较。第一电压比较器301可以被配置为直接监视电压,或者通过在一段时间内对流过接触垫125的电流进行积分来计算电压。第一电压比较器301可以由控制器310可控地激活或去激活。第一电压比较器301可以是连续比较器。即,第一电压比较器301可以被配置为连续激活并连续监视电压。第一阈值可以是一个入射辐射粒子在衬底110中可以产生的最大电压的5-10%、10%-20%、20-30%、30-40%或40-50%。最大电压可以取决于辐射粒子的能量、衬底110的材料和其他因素。例如,第一阈值可以是50mV、100mV、150mV或200mV。
第二电压比较器302被配置为将电压与第二阈值进行比较。第二电压比较器302可以被配置为直接监视电压,或者通过在一段时间内对流过接触垫125的电流进行积分来计算电压。第二电压比较器302可以由控制器310可控地激活或去激活。当第二电压比较器302被去激活时,第二电压比较器302的功耗可以小于在第二电压比较器302被激活时的功耗的1%、5%、10%或者20%。第二阈值的绝对值大于第一阈值的绝对值。如本文所使用的,实数x的术语“绝对值”或“模数”|x|是不考虑其符号的x的非负值。即,第二阈值可以是第一阈值的200%-300%。第二阈值可以是一个入射辐射粒子在衬底110中可以产生的最大电压的至少50%。例如,第二阈值可以是100mV、150mV、200mV、250mV或300mV。第二电压比较器302和第一电压比较器310可以是同一组件。即,系统121可以具有一个电压比较器,其可以在不同时间将电压与两个不同的阈值进行比较。
第一电压比较器301或第二电压比较器302可以包括一个或多个运算放大器或任何其他合适的电路。第一电压比较器301或第二电压比较器302可以具有使得电子系统121可在高通量的入射辐射下操作的高速。
计数器320被配置为记录到达衬底110的辐射粒子的数量。计数器320可以是软件组件(例如,存储在计算机存储器中的数量)或硬件组件(例如,4017IC和7490IC)。
控制器310可以是硬件组件,例如微控制器和微处理器。控制器310被配置为从第一电压比较器301确定电压的绝对值等于或超过第一阈值的绝对值(例如,电压的绝对值从低于第一阈值的绝对值增加为等于或高于第一阈值的绝对值的值)的时间开始时间延迟。这里使用绝对值是因为电压可以是负的或正的。控制器310可以被配置为在第一电压比较器301确定电压的绝对值等于或超过第一阈值的绝对值的时间之前,将第二电压比较器302、计数器320和第一电压比较器301的操作不需要的任何其他电路保持为去激活。时间延迟可以在电压变得稳定即电压的变化率基本上为零之前或之后期满。“电压的变化率基本上为零”的短语意指电压的时间变化小于0.1%/ns。“电压的变化率基本上不为零”的短语意指电压的时间变化至少为0.1%/ns。
控制器310可以被配置为在时间延迟期间(包括开始和期满)激活第二电压比较器302。在实施例中,控制器310被配置为在时间延迟开始时激活第二电压比较器302。术语“激活”意指使组件进入操作状态(例如,通过发送诸如电压脉冲或逻辑电平之类的信号,通过提供电力等)。术语“去激活”意指使组件进入非操作状态(例如,通过发送诸如电压脉冲或逻辑电平之类的信号,通过切断电力等)。操作状态可以具有比非操作状态更高的功耗(例如,为非操作状态的10倍,100倍,1000倍)。控制器310本身可以被去激活,直到当电压的绝对值等于或超过第一阈值的绝对值时第一电压比较器301的输出激活控制器310为止。
控制器310可以被配置为如果在时间延迟期间,第二电压比较器302确定电压的绝对值等于或超过第二阈值的绝对值,则使得由计数器320记录的数量增加1。
控制器310可以被配置为使得电压表306在时间延迟期满时测量电压。控制器310可以被配置为将接触垫125连接到电接地,以便使电压复位并对在接触垫125上累积的任何电荷载流子进行放电。在实施例中,接触垫125在时间延迟期满之后连接到电接地。在实施例中,接触垫125在有限的复位时间段内连接到电接地。控制器310可以通过控制开关305将接触垫125连接到电接地。开关可以是诸如场效应晶体管(FET)之类的晶体管。
在实施例中,系统121不具有模拟滤波器网络(例如,RC网络)。在实施例中,系统121没有模拟电路。
电压表306可以将其测量的电压作为模拟或数字信号馈送到控制器310。
电子系统121可以包括电连接到接触垫125的积分器309,其中积分器被配置为从接触垫125收集电荷载流子。积分器可以在放大器的反馈路径中包括电容器。这样配置的放大器称为电容互阻抗放大器(CTIA)。CTIA通过阻止放大器饱和而具有高动态范围,并通过限制信号路径中的带宽来提高信噪比。在一段时间(“积分期”)(例如,如图4所示,在t0到t1或t1-t2之间)内来自接触垫125的电荷载流子累积在电容器上。积分期期满后,对电容器电压进行采样,然后通过复位开关使电容器电压复位。积分器309可包括直接连接到接触垫125的电容器。
图4示意性地示出了由入射在衬底110上的辐射粒子产生的电荷载流子引起的流过接触垫125的电流的时间变化(上部曲线),以及接触垫125的电压的相应时间变化(下部曲线)。电压可以是电流相对于时间的积分。在时间t0,辐射粒子撞击衬底110,电荷载流子开始在衬底110中产生,电流开始流过接触垫125,并且接触垫125的电压的绝对值开始增加。在时间t1,第一电压比较器301确定电压的绝对值等于或超过第一阈值V1的绝对值,并且控制器310开始时间延迟TD1,并且控制器310可以在TD1开始时去激活第一电压比较器301。如果控制器310在t1之前被去激活,则控制器310在t1被激活。在TD1期间,控制器310激活第二电压比较器302。如这里使用的术语“在......期间”意指开始和期满(即结束)以及它们之间的任何时间。例如,控制器310可以在TD1期满时激活第二电压比较器302。如果在TD1期间,第二电压比较器302在时间t2确定电压的绝对值等于或超过第二阈值的绝对值,则控制器310使得由计数器320记录的数量增加1。在时间te,由辐射粒子产生的所有电荷载流子漂移出衬底110。在时间ts,时间延迟TD1期满。在图4的示例中,时间ts在时间te之后;即,在由辐射粒子产生的所有电荷载流子漂移出衬底110之后,TD1期满。因此,电压的变化率在ts处基本上为零。控制器310可以被配置为在TD1期满时或在t2或在其间的任何时间去激活第二电压比较器302。
控制器310可以被配置为使得电压表306在时间延迟TD1期满时测量电压。在实施例中,控制器310使电压表306在时间延迟TD1期满之后电压的变化率基本上变为零之后测量电压。此时刻的电压与由辐射粒子产生的电荷载流子的量成比例,其与辐射粒子的能量有关。控制器310可以被配置为基于电压表306测量的电压来确定辐射粒子的能量。确定能量的一种方法是对电压进行分区。计数器320可以具有用于各分区的子计数器。当控制器310确定辐射粒子的能量落入一分区中时,控制器310可以使在用于该分区的子计数器中记录的数量增加1。因此,电子系统121可能能够检测辐射图像并且可能能够分辨各辐射粒子的能量。
在TD1期满之后,控制器310在复位期RST内将接触垫125连接到电接地,以使得累积在接触垫125上的电荷载流子可以流到地并使电压复位。在RST之后,电子系统121准备好检测另一个入射辐射粒子。如果第一电压比较器301已经被去激活,则控制器310可以在RST期满之前的任何时间激活它。如果控制器310已经被去激活,则可以在RST期满之前激活它。
虽然本文已经公开了各个方面和实施例,但是其他方面和实施例对于本领域技术人员而言将是显而易见的。本文公开的各个方面和实施例是出于说明的目的而不意图是限制性的,真正的范围和精神由所附权利要求指示。
Claims (24)
1.一种方法,包括:
在半导体衬底的第一表面上形成第一导电层,其中,所述第一导电层与所述半导体电接触;
在所述第一导电层处,将支撑晶片接合到所述半导体衬底;
使所述半导体衬底变薄。
2.根据权利要求1所述的方法,还包括在所述半导体衬底的与所述第一表面相对的第二表面上形成电触点。
3.根据权利要求2所述的方法,还包括:
获得其中具有电路的芯片;
通过在所述第二表面处将所述芯片接合到所述半导体衬底,将所述电路电连接到所述电触点。
4.根据权利要求3所述的方法,还包括封装所述芯片和所述半导体衬底。
5.根据权利要求3所述的方法,还包括通过去除所述支撑晶片来暴露所述第一导电层的至少一部分。
6.根据权利要求1所述的方法,还包括在所述半导体衬底中形成p-n结或p-i-n结。
7.根据权利要求1所述的方法,其中,所述第一表面是抛光的。
8.根据权利要求1所述的方法,其中,所述第一导电层包含金属。
9.根据权利要求8所述的方法,其中,所述金属包括Al、Au或其组合。
10.根据权利要求1所述的方法,其中,所述支撑晶片包含氧化硅层。
11.根据权利要求1所述的方法,其中,所述支撑晶片包含在接合之后与所述第一导电层接触的第二导电层。
12.根据权利要求1所述的方法,还包括对所述半导体衬底进行激光退火。
13.根据权利要求1所述的方法,其中,使所述半导体衬底变薄包括在所述半导体衬底上进行化学机械平坦化,蚀刻所述半导体衬底或两者。
14.根据权利要求1所述的方法,还包括将所述第一导电层电接地。
15.根据权利要求3所述的方法,其中,所述电路包括被配置为处理或分析从所述半导体衬底产生的电信号的电子系统。
16.根据权利要求15所述的方法,其中,所述电子系统包括接触垫。
17.根据权利要求16所述的方法,其中,所述电子系统包括:
第一电压比较器,被配置为将所述接触垫的电压与第一阈值进行比较;
第二电压比较器,被配置为将所述电压与第二阈值进行比较;
计数器,被配置为记录由所述衬底吸收的辐射粒子的数量;
控制器;
其中,所述控制器被配置为从所述第一电压比较器确定所述电压的绝对值等于或超过所述第一阈值的绝对值的时间开始时间延迟;
其中,所述控制器被配置为在所述时间延迟期间激活所述第二电压比较器;
其中,所述控制器被配置为:如果所述第二电压比较器确定所述电压的绝对值等于或超过所述第二阈值的绝对值,则使所述计数器记录的数量增加1。
18.根据权利要求17所述的方法,其中,所述电子系统还包括电连接到所述接触垫的积分器,其中所述积分器被配置为从所述接触垫收集电荷载流子。
19.根据权利要求17所述的方法,其中,所述控制器被配置为在所述时间延迟开始或期满时激活所述第二电压比较器。
20.根据权利要求17所述的方法,其中,所述电子系统还包括电压表,其中所述控制器被配置为使得所述电压表在所述时间延迟期满时测量所述电压。
21.根据权利要求20所述的方法,其中,所述控制器被配置为基于在所述时间延迟期满时测量的电压值来确定辐射粒子的能量。
22.根据权利要求17所述的方法,其中,所述控制器被配置为将所述接触垫连接到电接地。
23.根据权利要求17所述的方法,其中,在所述时间延迟期满时,所述电压的变化率基本上为零。
24.根据权利要求17所述的方法,其中,在所述时间延迟期满时,所述电压的变化率基本上不为零。
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