CN112882295B - Display panel and display device - Google Patents
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- CN112882295B CN112882295B CN202110159686.9A CN202110159686A CN112882295B CN 112882295 B CN112882295 B CN 112882295B CN 202110159686 A CN202110159686 A CN 202110159686A CN 112882295 B CN112882295 B CN 112882295B
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- 239000002184 metal Substances 0.000 claims abstract description 209
- 239000000758 substrate Substances 0.000 claims abstract description 87
- 239000010410 layer Substances 0.000 claims description 353
- 239000011241 protective layer Substances 0.000 claims description 12
- 230000002093 peripheral effect Effects 0.000 claims description 9
- 230000005540 biological transmission Effects 0.000 claims description 3
- 238000005260 corrosion Methods 0.000 abstract description 8
- 230000007797 corrosion Effects 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 9
- 239000010408 film Substances 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000010409 thin film Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 239000000565 sealant Substances 0.000 description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133345—Insulating layers
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The application discloses display panel and display device is divided into display area and non-display area, includes: a first substrate and a second substrate disposed opposite to the first substrate; the first substrate includes: the structure comprises a substrate, a first metal layer, a first insulating layer, a second metal layer and a transparent conducting layer, wherein the first metal layer is arranged on the substrate; the first insulating layer is arranged on the first metal layer; the second metal layer is arranged on the first insulating layer; the transparent conducting layer is arranged below the second metal layer, and the transparent conducting layer and the second metal layer are mutually insulated through a first insulating layer; the first insulating layer is provided with a first through hole, the first through hole penetrates through the first insulating layer, the second metal layer covers the first through hole and is electrically connected with the transparent conducting layer, and the second metal layer is electrically connected with the transparent conducting layer through the first through hole so as to improve the corrosion resistance of the through hole of the display panel.
Description
Technical Field
The application relates to the technical field of display, in particular to a display device and a display panel.
Background
The display panel generally includes an array substrate and a color film substrate, the array substrate and the color film substrate are sealed by sealant, and the display panel is formed by sealing the array substrate and the color film substrate.
The array substrate generally adopts the design of via holes to realize the electrode connection between different metal layers, a plurality of via holes need to be formed on the array substrate, and generally the via holes cover the via holes through a transparent conducting layer and are connected to the corresponding metal layers, wherein, partial via holes may be positioned outside the frame glue, the transparent conducting layer on the via holes is easily corroded by water vapor, and the problem that the metal wires corresponding to the panel cannot transmit signals is caused.
Disclosure of Invention
The application aims to provide a display panel and a display device, and the anti-corrosion capability of a via hole of the display panel is improved.
The application discloses display panel is divided into display area and non-display area, includes: a first substrate and a second substrate disposed opposite to the first substrate; the first substrate includes: the structure comprises a substrate, a first metal layer, a first insulating layer, a second metal layer and a transparent conducting layer, wherein the first metal layer is arranged on the substrate; the first insulating layer is arranged on the first metal layer; the second metal layer is arranged on the first insulating layer; the transparent conducting layer is arranged below the second metal layer, and the transparent conducting layer and the second metal layer are mutually insulated through a first insulating layer; the first insulating layer is provided with a first through hole, the first through hole penetrates through the first insulating layer, and the second metal layer covers the first through hole and is electrically connected with the transparent conducting layer; the second metal layer is electrically connected with the transparent conductive layer through the first via hole.
Optionally, the transparent conductive layer is located between the first metal layer and the substrate, an extension portion is provided at a position where the transparent conductive layer exceeds the first metal layer, the first via hole is correspondingly disposed on the extension portion, and the second metal layer is connected to the extension portion through the first via hole.
Optionally, the transparent conductive layer is located between the first metal layer and the first insulating layer, an extension portion is provided at a position where the transparent conductive layer exceeds the first metal layer, the first via hole is provided on the extension portion, and the second metal layer is connected to the extension portion through the first via hole.
Optionally, the first metal layer is attached to the transparent conductive layer.
Optionally, a second insulating layer is disposed between the first metal layer and the transparent conductive layer, a second via hole is disposed at a position of the second insulating layer corresponding to the first metal layer, and the first metal layer is connected to the transparent conductive layer through the second via hole.
Optionally, a second insulating layer is further disposed between the transparent conductive layer and the first metal layer, a second via hole is disposed at a position of the second insulating layer corresponding to the first metal layer, and the transparent conductive layer is connected to the first metal layer through the second via hole.
Optionally, the first metal layer forms a first metal routing group, the second metal layer forms a second metal routing group, the first metal routing group is a peripheral routing line located in the non-display area, and the second metal routing group is a transmission signal line connected with the peripheral routing line in a one-to-one correspondence manner.
Optionally, at the first via position, the projections of the first metal layer and the second metal layer on the substrate do not overlap.
The application also discloses a display panel, is divided into display area and non-display area, includes: the array substrate is a color film substrate arranged opposite to the array substrate; the first substrate comprises a transparent conducting layer, a second insulating layer, a first metal layer, a first insulating layer, a second metal layer and a protective layer which are sequentially stacked; a first via hole and a second via hole are respectively formed above the transparent conducting layer; the first via hole penetrates through the second insulating layer and the first insulating layer, and the second metal layer covers the first via hole and is connected to the transparent conducting layer; the second via hole penetrates through the second insulating layer, and the first metal layer covers the first via hole and is connected to the transparent conductive layer; in the areas of the first via hole and the second via hole, the first metal layer and the second metal layer are not overlapped on the orthographic projection of the substrate.
The application also discloses a display device, which comprises the display panel and a backlight module for providing a light source for the display panel.
According to the application, the second metal layer is arranged above the transparent conducting layer, so that the second metal layer covers the first via hole and is connected to the transparent conducting layer, and the transparent conducting layer is easier to be corroded by water vapor relative to the metal layer; compared with a scheme of covering the first via hole through the transparent conducting layer, the scheme of the application enables the transparent conducting layer not to be exposed outside any more, and therefore risks of corrosion are reduced. In terms of manufacturing process, after the second metal layer is deposited, a second insulating layer is formed to protect the second metal layer, and the second insulating layer also covers the first via hole, so that the second metal layer covered on the first via hole is not easily corroded.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic diagram of a display panel according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a via of an embodiment of the present application;
FIG. 3 is a schematic diagram of a first via according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a first via according to another embodiment of the present application;
FIG. 5 is a schematic diagram of a first via and a second via of another embodiment of the present application;
FIG. 6 is a schematic diagram of a first via and a second via of another embodiment of the present application;
fig. 7 is a schematic diagram of a first metal routing group and a second metal routing group of a display panel according to an embodiment of the present application;
fig. 8 is a schematic diagram of a display device according to an embodiment of the present application.
Wherein, 1, a display device; 10. a display panel; 11. a display area; 12. a non-display area; 30. a backlight module; 100. a first substrate; 101. an array substrate; 110. a first metal layer; 111. a first metal routing group; 112. sub-routing; 120. a second metal layer; 121. a second metal wiring group; 122. a sub-connection line; 130. a via hole; 131. a first via hole; 132. a second via hole; 140. a transparent conductive layer; 150. a first insulating layer; 160. a second insulating layer; 170. a substrate; 200. a second substrate; 201. a color film substrate; 300. and (5) frame glue.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless stated otherwise, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and any variations thereof, are intended to cover a non-exclusive inclusion, which may have the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or combinations thereof.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The present application is described in detail below with reference to the figures and alternative embodiments.
As disclosed in fig. 1, the exemplary display panel 10 includes a first substrate 100 and a second substrate arranged opposite to each other, a sealant 300 is arranged between the first substrate 100 and the second substrate, and the first substrate 100 includes a substrate 170, a first metal layer 110, a first insulating layer 150, a second metal layer 120, a second insulating layer 160, a transition layer, and a protective layer, which are stacked at one time; the first metal layer 110 and the second metal layer 120 are correspondingly connected in a conductive manner through a via 130, and a protective layer is disposed on the via 130 for protection, but a general protective layer cannot resist the corrosion of external moisture for a long time, and particularly, in a high-humidity environment, the problem of via corrosion is caused.
In order to solve the above technical problem, the present application discloses a display panel 10, as shown in fig. 3, which is a schematic view of a display panel, the display panel 10 includes a first substrate 100 and a second substrate, the first substrate 100 includes: the semiconductor device includes a substrate 170, a first metal layer 110 and a second metal layer 120 formed on the substrate 170, and a first insulating layer 150 disposed between the first metal layer 110 and the second metal layer 120. A transparent conductive layer 140 is further disposed below the second metal layer 120, the transparent conductive layer 140 is electrically connected to the first metal layer 110, and the transparent conductive layer 140 is insulated from the second metal layer 120 by a first insulating layer 150; the first insulating layer 150 is provided with a first via hole 131 at a position corresponding to the transparent conductive layer 140, and the second metal layer 120 is electrically connected to the transparent conductive layer 140 through the first via hole 131.
The second metal layer 120 is disposed above the transparent conductive layer 140, so that the second metal layer 120 covers the first via hole 131 and is connected to the transparent conductive layer 140, and the transparent conductive layer 140 is more easily corroded by water vapor than the metal layer; compared with the scheme that the transparent conductive layer 140 covers the first via 131, the scheme of the application enables the transparent conductive layer 140 not to be exposed, and further reduces the risk of corrosion. In terms of manufacturing process, the first metal layer 110 and the second metal layer 120 of the present application are on the same layer as the metal layer where the gate and the source drain of the thin film transistor in the display area 11 are located, after the second metal layer 120 is deposited, a second insulating layer 160 is formed to protect the second metal layer 120, and the second insulating layer 160 also covers the first via hole 131, so that the second metal layer 120 covered on the first via hole 131 is not easily corroded, and as in the via hole 130 design of fig. 1, besides the need to deposit the second insulating layer 160, a protective layer needs to be deposited to protect the conductive layer on the via hole 130; moreover, even if the protective layer exists in the via hole 130 outside the sealant 300 in the non-display area 12, there is a greater risk of corrosion; therefore, the present application also saves the manufacturing process of the protective layer, and has better corrosion resistance compared with the transparent conductive layer 140 covering the via 130.
Specifically, the transparent conductive layer 140 is located above the first metal layer 110 and below the first insulating layer 150; the first metal layer 110 is attached to the transparent conductive layer 140.
In the present application, the thicknesses of the first metal layer 110 and the second metal layer 120 are less than the thickness of the first insulating layer 150, and the transparent conductive layer 140 is directly covered above the first metal layer 110, so that the direct contact makes the contact area between the first metal layer 110 and the transparent conductive layer 140 larger, the resistance smaller, and the impedance of signal transmission smaller; in terms of manufacturing process, only after the first metal layer 110 is patterned, the transparent conductive layer 140 is patterned, and the manufacturing process of the thin film transistor inside the display panel 10 is not changed, which is equivalent to the flatness inside the display panel 10.
The position of the transparent conductive layer 140 beyond the first metal layer 110 has an extension portion, that is, the transparent conductive layer 140 protrudes from the first metal layer 110 at the position of the first via hole 131, the first via hole 131 is disposed corresponding to the extension portion of the transparent conductive layer 140, and the extension portion is disposed to make the thickness of the first insulating layer 150 between the transparent conductive layer 140 at the first via hole 131 and the second metal layer 120 the thickest, so as to prevent the first insulating layer 150 from being too thin and being broken down by static electricity to affect the insulating property.
As shown in fig. 3, the projections of the first metal layer 110 and the second metal layer 120 on the substrate 170 are not coincident. In the present embodiment, the processes of the first metal layer 110 and the second metal layer 120, the second metal layer corresponding to the thin film transistor in the display area and the data line, and the first metal layer corresponding to the scan line layer are formed in the same layer, but are not necessarily connected to the first metal layer and the second metal layer in the display area, and the first metal layer and the second metal layer corresponding to the display area cannot be overlapped together. The first metal layer 110 and the second metal layer 120 in the non-display region are connected to each other, which may cause a short circuit in the in-plane process of the display region. Therefore, the processes of the first metal layer and the second metal layer in the corresponding non-display region are reduced, so that the projections of the first metal layer 110 and the second metal layer 120 on the substrate 170 are not overlapped.
As shown in fig. 4, in another embodiment, a display panel 10 is disclosed, the display panel 10 includes a first substrate 100 and a second substrate, the first substrate 100 includes: the semiconductor device includes a substrate 170, a first metal layer 110 and a second metal layer 120 formed on the substrate 170, and a first insulating layer 150 disposed between the first metal layer 110 and the second metal layer 120. A transparent conductive layer 140 is further disposed below the second metal layer 120, the transparent conductive layer 140 is electrically connected to the first metal layer 110, and the transparent conductive layer 140 and the second metal layer 120 are insulated from each other by a first insulating layer 150; a first via hole 131 is formed in a position of the first insulating layer 150 corresponding to the transparent conductive layer 140, and the second metal layer 120 is connected to the transparent conductive layer 140 through the first via hole 131.
The present embodiment is different from the previous embodiment in that the transparent conductive layer 140 is located below the first metal layer 110 and above the substrate 170; the first metal layer 110 is in direct contact with the transparent conductive layer 140, and the direct contact makes the contact area between the first metal layer 110 and the transparent conductive layer 140 larger, and the resistance smaller, so that the impedance of signal transmission is smaller. Similarly, since the insulating layer has a thicker thickness, in terms of the manufacturing process, only before the first metal layer 110 is patterned, the transparent conductive layer 140 may be patterned, without changing the manufacturing process of the thin film transistor inside the display panel 10, which is equivalent to the flatness inside the display panel 10; the difference is that, in the case of forming the transparent conductive layer 140 first, the transparent conductive layer 140 does not form a step as shown in fig. 2, the overall uniformity of the transparent conductive layer 140 is better, and disconnection of the transparent conductive layer 140 at the step is prevented.
Specifically, the projections of the first metal layer 110 and the second metal layer 120 on the substrate 170 are not coincident; the transparent conductive layer 140 has an extension portion beyond the first metal layer 110, and the second via 132 is disposed corresponding to the extension portion of the transparent conductive layer 140.
As shown in fig. 5, in another embodiment, a display panel 10 is disclosed, which includes a first substrate 100, wherein the first substrate 100 is divided into a display area 11 and a non-display area 12, and the non-display area 12 of the first substrate 100 includes a substrate 170, a transparent conductive layer 140, a second insulating layer 160, a first metal layer 110, a first insulating layer 150, a second metal layer 120, and a protective layer, which are stacked at one time.
The region between the first insulating layer 150 and the second insulating layer 160 where the first metal layer 110 is disposed is a first metal wiring region, and the region where the first insulating layer 150 and the second insulating layer 160 are in direct contact is a non-wiring region; the second insulating layer 160 forms a second via 132 at the position of the first metal routing area, and the first metal layer 110 is connected to the transparent conductive layer 140 through the second via 132; the first insulating layer 150 and the second insulating layer 160 form a first via 131 at the position of the non-routing region, and the second metal layer 120 is connected to the transparent conductive layer 140 through the first via 131. The transparent conductive layer 140 is located below the first metal layer 110 and above the substrate 170; a second insulating layer 160 is disposed between the first metal layer 110 and the transparent conductive layer 140.
The difference between the present embodiment and the previous embodiment is that the first metal layer 110 and the transparent conductive layer 140 are insulated from each other, and the process of the thin film transistor in the display area 11 is different in that the transparent conductive layer 140 needs to be deposited before the first metal layer 110 is formed, and the second insulating layer 160, the first metal layer 110, the first insulating layer 150, the second insulating layer 160 and the passivation layer are sequentially formed. In order to maintain the flatness, the transparent conductive layer 140 and the insulating layer may be formed below the first metal layer 110 in the process of the display region 11; suitable for different types of thin film transistors, such as a thin film transistor in which the transparent conductive layer 140 is disposed under the first metal layer 110. Moreover, the second via hole 132 is also formed in the first metal layer 110, the second metal layer 120 covers the first via hole 131 and is connected to the transparent conductive layer 140, the first metal layer 110 covers the second via hole 132 and is connected to the transparent conductive layer 140, so that the transparent conductive layer 140 is located below the first metal layer 110 to better protect the transparent conductive layer 140, and the protective layer is disposed on the second metal layer 120, so that the original film layer of the display panel 10 is not changed, and the via hole 130 is not easily corroded by merely adjusting the position of the film layer.
Specifically, the depth of the second via 132 is smaller than the depth of the first via 131, and the projection of the first metal layer 110 and the projection of the second metal layer 120 on the substrate 170 are not coincident. The position of the transparent conductive layer 140 beyond the first metal layer 110 has an extension, and the second via 132 is disposed corresponding to the extension of the transparent conductive layer 140.
As shown in fig. 6, an array substrate 101 is disclosed, wherein a non-display region 12 of the array substrate 101 includes a substrate 170, a first metal layer 110, a second insulating layer 160, a transparent conductive layer 140, a first insulating layer 150, a second metal layer 120, and a protective layer, which are stacked at one time; the region where the first metal layer 110 is disposed is a first metal routing region, the first insulating layer 150 forms a first via 131 at a corresponding position of the first metal routing region, and the transparent conductive layer 140 is connected to the first metal layer 110 through a second via 132; the second insulating layer 160 is provided with a first via 131 at a position corresponding to the transparent conductive layer 140, and the second metal layer 120 is connected to the transparent conductive layer 140 through the first via 131.
Different from the previous embodiment, the transparent conductive layer 140 is formed above the first metal layer 110, the transparent conductive layer 140 covers the second via hole 132 and is connected to the first metal layer 110, the second metal layer 120 covers the first via hole 131 and is connected to the transparent conductive layer 140, and the transparent conductive layer 140 is disposed above the first metal layer 110, so that the distance between the transparent conductive layer 140 and the second metal layer 120 is closer, the deep hole of the first via hole 131 is smaller, and the first via hole 131 is closer to the outer side of the film layer.
As another embodiment of the present application, a method for applying the design of the first via hole of the present application to a specific position of a display panel is disclosed, and fig. 7 shows a schematic diagram of a first metal routing group 111 of a display panel 10, where the first metal routing group 111 surrounds three edges of the display panel 10; a plurality of second metal routing groups 121 are formed on the second metal layer 120, and the plurality of second metal routing groups 121 are respectively connected with the first metal routing group 111 through a plurality of contact holes 130; the multiple groups of second metal routing groups 121 are respectively connected to different electrostatic discharge blocks, and the electrostatic discharge routing in this application is provided with multiple groups, which are respectively arranged at different positions of the first metal routing group 111, so that the electrostatic discharge on the first metal routing group 111 is realized.
Wherein the first metal layer 110 and the second metal layer 120 in the present application belong to the same layer as the first metal layer 110 and the second metal layer 120 in the display area 11 of the display panel 10; in the present application, the first substrate 100 is an array substrate 101, and the second substrate 200 is a color filter substrate 201. The first metal layer forms a first metal wiring group, the second metal layer forms a second metal wiring group, the first metal wiring group is peripheral wiring located in a non-display area, and the second metal wiring group is transmission signal lines which are connected with the peripheral wiring in a one-to-one correspondence mode; it should be noted that, in the present application, the first metal routing group 111, i.e. the sub-routing 112, is a peripheral routing of the non-display region 12 and provides a driving signal voltage (e.g. VGH, VGL, CLK, VCOM, etc.) for the display panel 10, and the second metal routing group 121, i.e. the sub-connecting line 122, is an electrostatic discharge (ESD) routing, and conducts the Static electricity of the peripheral routing of the non-display region 12 to the outside of the display panel 10 through the contact hole 130, so as to prevent the peripheral routing of the non-display region 12 from failing due to ESD.
As another embodiment of the present application with reference to fig. 1-8, a display device 1 is disclosed, where the display device 1 includes a display panel 10 and a backlight module 30 for providing a light source for the display panel 10, the display panel 10 is divided into a display area 11 and a non-display area 12, and includes: the color filter substrate comprises an array substrate 101 and a color filter substrate 201 arranged opposite to the array substrate 101; a sealant 300 is arranged between the array substrate 101 and the color film substrate 201, and the sealant 300 is arranged in the non-display area 12; the array substrate 101 includes a transparent conductive layer 140, a second insulating layer 160, a first metal layer 110, a first insulating layer 150, a second metal layer 120, and a protective layer 180, which are sequentially stacked corresponding to the non-display region 12; a first via hole 131 and a second via hole 132 are respectively formed above the transparent conductive layer; the first via hole 131 penetrates through the second insulating layer 160 and the first insulating layer 150, and the second metal layer 120 covers the first via hole 131 and is connected to the transparent conductive layer 140; the second via 132 penetrates through the second insulating layer 160, and the first metal layer 110 covers the first via 131 and is connected to the transparent conductive layer 140; in the area of the first via 131 and the second via 132, the first metal layer 110 and the second metal layer 120 are not overlapped on the orthographic projection of the substrate.
It should be noted that, on the premise of not affecting the implementation of the specific embodiment, the limitations of the steps involved in the present disclosure are not considered as limiting the order of the steps, and the steps written in the foregoing may be executed first, or executed later, or even executed simultaneously, and as long as the present disclosure can be implemented, all the steps should be considered as belonging to the protection scope of the present disclosure.
The technical solution of the present application can be widely applied to various display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, MVA (Multi-Domain Vertical Alignment) display panel, and of course, other types of display panels, such as OLED (Organic Light-Emitting Diode) display panel, which can be applied to the above solutions.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (6)
1. A display panel divided into a display area and a non-display area, comprising:
a first substrate;
a second substrate disposed opposite to the first substrate;
the first substrate includes:
a substrate, a first electrode and a second electrode,
a first metal layer disposed on the substrate;
a first insulating layer disposed on the first metal layer;
a second metal layer disposed on the first insulating layer; a second insulating layer is further arranged on the second metal layer; and
the transparent conducting layer is arranged below the second metal layer, and the transparent conducting layer and the second metal layer are mutually insulated through a first insulating layer;
the first insulating layer is provided with a first via hole, the first via hole penetrates through the first insulating layer, the second metal layer covers the first via hole and is electrically connected with the transparent conductive layer, and the transparent conductive layer is electrically connected with the first metal layer;
the transparent conducting layer is positioned between the first metal layer and the substrate, an extending part is arranged at the position, beyond the first metal layer, of the transparent conducting layer, the first via hole is correspondingly arranged on the extending part, and the second metal layer is connected with the extending part through the first via hole;
the film layer of the transparent conducting layer is on a plane and has no offset.
2. The display panel according to claim 1, wherein the first metal layer is in direct contact with the transparent conductive layer.
3. The display panel according to claim 1, wherein the first metal layer forms a first metal routing group, the second metal layer forms a second metal routing group, the first metal routing group is a peripheral routing located in a non-display area, and the second metal routing group is a transmission signal line connected with the peripheral routing in a one-to-one correspondence manner.
4. The display panel of claim 1, wherein at the first via location, an orthographic projection of the first metal layer and the second metal layer on the substrate does not overlap.
5. A display panel divided into a display area and a non-display area, comprising:
an array substrate;
the color film substrate is arranged opposite to the array substrate;
the array substrate comprises a substrate, a transparent conducting layer, a second insulating layer, a first metal layer, a first insulating layer, a second metal layer and a protective layer which are sequentially stacked;
a first through hole and a second through hole are formed above the transparent conductive layer; the depth of the second via hole is smaller than that of the first via hole;
the first via hole penetrates through the second insulating layer and the first insulating layer, and the second metal layer covers the first via hole and is connected to the transparent conductive layer;
the second via hole penetrates through the second insulating layer, and the first metal layer covers the second via hole and is connected to the transparent conductive layer;
in the areas of the first via hole and the second via hole, the first metal layer and the second metal layer are not overlapped on the orthographic projection of the substrate;
the display panel is an IPS (In-Plane Switching);
the film layer of the transparent conducting layer is on a plane and has no offset.
6. A display device comprising the display panel of any one of claims 1 to 5 and a backlight module for providing a light source to the display panel.
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| CN113540184B (en) * | 2021-06-16 | 2023-11-28 | 合肥维信诺科技有限公司 | Display panel and preparation method thereof |
| CN113703238A (en) | 2021-09-09 | 2021-11-26 | 武汉华星光电技术有限公司 | Array substrate and electronic device |
| CN115719747B (en) * | 2022-10-31 | 2023-10-20 | 惠科股份有限公司 | Driving substrate and display device |
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| CN104020593A (en) * | 2014-05-30 | 2014-09-03 | 深圳市华星光电技术有限公司 | Array substrate, manufacturing method and liquid crystal display panel |
| CN104319274B (en) * | 2014-11-14 | 2017-03-29 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display floater and display device |
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| CN108255353B (en) * | 2016-12-29 | 2021-04-02 | 南京瀚宇彩欣科技有限责任公司 | Embedded touch display panel |
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