CN118016676A - Array substrate and display panel - Google Patents

Array substrate and display panel Download PDF

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Publication number
CN118016676A
CN118016676A CN202410190276.4A CN202410190276A CN118016676A CN 118016676 A CN118016676 A CN 118016676A CN 202410190276 A CN202410190276 A CN 202410190276A CN 118016676 A CN118016676 A CN 118016676A
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China
Prior art keywords
metal layer
substrate
array substrate
holes
vias
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CN202410190276.4A
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Chinese (zh)
Inventor
王洪惠
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to CN202410190276.4A priority Critical patent/CN118016676A/en
Publication of CN118016676A publication Critical patent/CN118016676A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The application discloses an array substrate and a display panel, which can solve the problems of connection failure or impedance increase of upper-layer wiring and lower-layer wiring. The array substrate includes: a substrate; the first metal layer comprises a first wiring; a first insulating layer including a first via; the second metal layer comprises a connecting wire; a second insulating layer including a second via; the third metal layer comprises a second wiring; the first via hole is overlapped with the first wiring in the direction perpendicular to the plane of the substrate, the connecting wiring is connected with the first wiring through the first via hole, the second via hole is overlapped with the connecting wiring, and the second wiring is connected with the connecting wiring through the second via hole; wherein the second metal layer comprises a material having a higher corrosion resistance than the third metal layer.

Description

Array substrate and display panel
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a display panel.
Background
Currently, TFT-LCD (Thin Film Transistor-Liquid CRYSTAL DISPLAY, thin film transistor Liquid crystal display) has been widely used for display screens of mobile phones, televisions, notebook computers, and the like. In the liquid crystal display panel or the array substrate, the wiring in the upper metal layer is connected with the wiring in the lower metal layer through the via hole in the insulating layer.
However, the wires in the upper metal layer and the wires in the lower metal layer are easily corroded by water vapor and the like at the connection parts of the vias, so that the connection of the vias fails, and the connection failure or the impedance of the wires in the upper metal layer and the wires in the lower metal layer is increased.
Disclosure of Invention
The embodiment of the application provides an array substrate and a display panel, which can solve the problems that in the prior art, the connection part of a via hole is easy to be corroded by water vapor and the like, so that the connection failure of the via hole is caused, and the connection failure or the impedance increase of a wiring in an upper metal layer and a wiring in a lower metal layer are caused.
In a first aspect of an embodiment of the present application, there is provided an array substrate, including:
A substrate;
the first metal layer is arranged on one side of the substrate and comprises at least one first wire;
the first insulating layer is arranged on one side, far away from the substrate, of the first metal layer, and comprises at least one first via hole;
The second metal layer is arranged on one side, far away from the substrate, of the first insulating layer and comprises at least one connecting wire;
the second insulating layer is arranged on one side, far away from the substrate, of the second metal layer, and comprises at least one second via hole;
The third metal layer is arranged on one side, far away from the substrate, of the second insulating layer and comprises at least one second wiring;
The first via hole and the first wiring are overlapped in the direction perpendicular to the plane of the substrate, and the connecting wiring is connected with the first wiring through the first via hole;
The second via hole is overlapped with the connecting wire in the direction perpendicular to the plane of the substrate, and the second wire is connected with the connecting wire through the second via hole;
wherein the second metal layer comprises a material having a higher corrosion resistance than the third metal layer.
In some embodiments, the second metal layer comprises at least two metal sublayers, at least one of the metal sublayers of the second metal layer being more corrosion resistant than the third metal layer.
In some embodiments, the material of the second metal layer includes at least one of titanium, chromium, and nickel.
In some embodiments, the material of the third metal layer includes at least one of transparent conductive metal oxide, copper, and aluminum.
In some embodiments, the first insulating layer includes a plurality of the first vias and the second insulating layer includes a plurality of the second vias;
At least part of the second through holes are overlapped with the corresponding first through holes in the direction perpendicular to the plane of the substrate; or/and (or)
At least part of the second through holes and the first through holes are arranged in a staggered mode.
In some embodiments, the number of first vias is the same as the number of second vias;
And in the direction perpendicular to the plane of the substrate, the second through holes and the first through holes are arranged in a staggered mode or overlapped mode.
In some embodiments, the number of first vias is less than the number of second vias;
In the direction perpendicular to the plane of the substrate, the first through holes are overlapped with the corresponding second through holes, and part of the second through holes are staggered with the first through holes.
In some embodiments, the number of first vias is greater than the number of second vias;
In the direction perpendicular to the plane of the substrate, the second through holes are overlapped with the corresponding first through holes, and part of the first through holes and the second through holes are arranged in a staggered mode.
In some embodiments, the array substrate includes a plurality of thin film transistors, and at least one of a pixel electrode and a common electrode;
the first metal layer further comprises a gate electrode of the thin film transistor;
the first insulating layer is a gate insulating layer;
The second metal layer further comprises a source electrode and a drain electrode of the thin film transistor;
the third metal layer further includes the pixel electrode or the common electrode.
In some embodiments, the array substrate includes a display area and a non-display area around the display area, and the first trace, the connection trace, and the second trace are all located in the non-display area.
In a second aspect of the embodiments of the present application, a display panel is provided, including an array substrate as described in any one of the above.
In the array substrate and the display panel provided by the embodiment of the application, the connecting wires are additionally arranged, the second wires are connected with the connecting wires through the second through holes, and the connecting wires are connected with the first wires through the first through holes, so that the second wires are connected with the first wires through the connecting wires, the second through holes and the first through holes, and the total resistance of the first wires and the second wires before corrosion failure is reduced, and the total resistance of the first wires and the second wires after corrosion failure is reduced. In the second aspect, since the second metal layer includes a material having higher corrosion resistance than the third metal layer, the second metal layer can block the corrosion from further extending to the first wiring, thereby ensuring normal connection of the plurality of first vias. In a third aspect, when a certain second via hole corrodes, the electrical signal is transmitted through the second via hole and the plurality of first via holes except the corroded second via hole, so that the total resistance of the first wiring and the second wiring after corrosion failure can be further reduced. In the fourth aspect, in the related art, the third metal layer or the second wire does not corrode, but the water vapor and the like reach the first wire through the second wire, so that the first wire corrodes, and therefore, the second metal layer or the connection wire in the embodiment of the application blocks the path of the water vapor reaching the first wire, so that the first wire is ensured not to corrode.
Drawings
FIG. 1 is a schematic diagram illustrating a partial top view of a film layer of an array substrate according to an embodiment of the present application;
FIG. 2 is a schematic cross-sectional view taken along the line C-C in FIG. 1, in accordance with an embodiment of the present application;
FIG. 3 is a schematic cross-sectional view taken along line D-D in FIG. 1, in accordance with an embodiment of the present application;
FIG. 4 is a schematic diagram of an equivalent circuit of the array substrate in FIG. 2 according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a portion of the via failure in the equivalent circuit of FIG. 4 according to an embodiment of the present application;
FIG. 6 is a schematic diagram illustrating a partial top view of a film layer of an array substrate according to an embodiment of the present application;
FIG. 7 is a schematic cross-sectional view of a first array substrate according to an embodiment of the present application at or in the direction of the dotted line C-C;
FIG. 8 is a schematic cross-sectional view taken along line D-D in FIG. 6, in accordance with an embodiment of the present application;
Fig. 9 is an equivalent circuit schematic diagram of a first array substrate according to an embodiment of the present application;
fig. 10 is a schematic diagram of a partial via failure in an equivalent circuit of a first array substrate according to an embodiment of the present application;
FIG. 11 is a schematic cross-sectional view of a second array substrate according to an embodiment of the present application at or in the dotted line C-C;
FIG. 12 is a schematic diagram of a partial via failure in an equivalent circuit of a second array substrate according to an embodiment of the present application;
FIG. 13 is a schematic cross-sectional view of a third array substrate according to an embodiment of the present application at or in the direction of the dotted line C-C;
fig. 14 is a schematic diagram of a partial via failure in an equivalent circuit of a third array substrate according to an embodiment of the present application;
FIG. 15 is a schematic cross-sectional view of a fourth array substrate according to an embodiment of the present application at or in the direction of the dotted line C-C;
fig. 16 is a schematic diagram illustrating a partial via failure in an equivalent circuit of a fourth array substrate according to an embodiment of the present application.
Detailed Description
In order to better understand the technical solutions provided by the embodiments of the present specification, the following detailed description of the technical solutions of the embodiments of the present specification is made through the accompanying drawings and the specific embodiments, and it should be understood that the specific features of the embodiments of the present specification are detailed descriptions of the technical solutions of the embodiments of the present specification, and not limit the technical solutions of the present specification, and the technical features of the embodiments of the present specification may be combined with each other without conflict.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. The term "two or more" includes two or more cases.
Referring to fig. 1 to 5, fig. 1 is a schematic partial top view of a portion of a film layer of an array substrate according to an embodiment of the present application; FIG. 2 is a schematic cross-sectional view taken along the line C-C in FIG. 1, in accordance with an embodiment of the present application; FIG. 3 is a schematic cross-sectional view taken along line D-D in FIG. 1, in accordance with an embodiment of the present application; FIG. 4 is a schematic diagram of an equivalent circuit of the array substrate in FIG. 2 according to an embodiment of the present application; FIG. 5 is a schematic diagram of a portion of the via failure in the equivalent circuit of FIG. 4 according to an embodiment of the present application; a part of the film layer of the array substrate is illustrated in fig. 1.
In the related art, the array substrate or the display panel includes at least one of the first metal layer 12, the first insulating layer 13 and the second insulating layer 15, and the third metal layer 16, the first metal layer 12 includes the first trace 121, the third metal layer 16 includes the second trace 161, the first insulating layer 13 or/and the second insulating layer 15 includes the large through hole 1351, and the second trace 161 is connected to the first trace 121 through the large through hole 1351, so as to realize the electrical connection between the first trace 121 and the second trace 161. However, corrosion is likely to occur at the connection portion of the large through hole 1351, for example, by moisture, oxygen, or the like, resulting in failure of the connection of the second trace 161 to the first trace 121 through the large through hole 1351, as shown in fig. 5, such that the connection of the second trace 161 to the first trace 121 fails or the impedance increases, and the cross ("x" number) in fig. 5 indicates that the connection at the portion of one large through hole 1351 is corroded to fail. As a result of the analysis by the inventors, it was found that, particularly in a narrow-frame product, the first trace 121, the second trace 161, and the large through hole 1351 are located in the non-display region, the connection portion is more easily corroded by moisture or the like, and the connection failure or the increase in impedance of the second trace 161 and the first trace 121 becomes worse.
In view of the above, the present application provides an array substrate and a display panel, which can solve the above-mentioned problems.
The application provides an array substrate, comprising: a substrate; the first metal layer is arranged on one side of the substrate and comprises at least one first wire; the first insulating layer is arranged on one side, far away from the substrate, of the first metal layer and comprises at least one first via hole; the second metal layer is arranged on one side, far away from the substrate, of the first insulating layer and comprises at least one connecting wire; the second insulating layer is arranged on one side, far away from the substrate, of the second metal layer and comprises at least one second via hole; the third metal layer is arranged on one side, far away from the substrate, of the second insulating layer and comprises at least one second wiring; the first via hole and the first wiring are overlapped in the direction perpendicular to the plane of the substrate, and the connecting wiring is connected with the first wiring through the first via hole; the second via hole is overlapped with the connecting wire in the direction perpendicular to the plane of the substrate, and the second wire is connected with the connecting wire through the second via hole; wherein the second metal layer comprises a material having a higher corrosion resistance than the third metal layer.
The application also provides a display panel comprising the array substrate.
The application also provides a display device comprising the array substrate or/and the display panel.
Referring to fig. 6 to 9, fig. 6 is a schematic partial top view of a portion of a film layer of an array substrate according to an embodiment of the application; FIG. 7 is a schematic cross-sectional view of a first array substrate according to an embodiment of the present application at or in the direction of the dotted line C-C; FIG. 8 is a schematic cross-sectional view taken along line D-D in FIG. 6, in accordance with an embodiment of the present application; fig. 9 is an equivalent circuit schematic diagram of a first array substrate according to an embodiment of the present application; fig. 10 is a schematic diagram of a partial via failure in an equivalent circuit of a first array substrate according to an embodiment of the present application.
The application provides an array substrate 100, wherein the array substrate 100 comprises a base 11, a first metal layer 12, a first insulating layer 13, a second metal layer 14, a second insulating layer 15 and a third metal layer 16. The first metal layer 12 is disposed on one side of the substrate 11, and the first metal layer 12 includes at least one first trace 121; the first insulating layer 13 is disposed on a side of the first metal layer 12 away from the substrate 11, and the first insulating layer 13 includes at least one first via 131; the second metal layer 14 is disposed on a side of the first insulating layer 13 away from the substrate 11, and the second metal layer 14 includes at least one connection trace 141; the second insulating layer 15 is disposed on a side of the second metal layer 14 away from the substrate 11, where the second insulating layer 15 includes at least one second via 151; the third metal layer 16 is disposed on a side of the second insulating layer 15 away from the substrate 11, and the third metal layer 16 includes at least one second trace 161; the first via 131 and the first trace 121 are overlapped in a direction perpendicular to a plane of the substrate 11, and the connection trace 141 is connected to the first trace 121 through the first via 131; the second via 151 is overlapped with the connection trace 141 in a direction perpendicular to the plane of the substrate 11, and the second trace 161 is connected with the connection trace 141 through the second via 151; wherein the second metal layer 14 comprises a material having a higher corrosion resistance than the third metal layer 16.
Illustratively, the material of the substrate 11 may be glass or a flexible substrate, without limitation.
Illustratively, as shown in fig. 7, the direction perpendicular to the plane of the substrate 11 is the first direction Y.
In the present application, the connection trace 141 is additionally provided, the second trace 161 is connected to the connection trace 141 through the second via 151, and the connection trace 141 is connected to the first trace 121 through the first via 131, so that the second trace 161 is connected to the first trace 121 through the connection trace 141, the second via 151, and the first via 131.
As shown in fig. 4, taking 3 large through holes 1351 as an example, in the related art, the total resistance of the first trace 121 and the second trace 161 is R Total (S) , the resistance of the line segment of the first trace 121 between two adjacent large through holes 1351 is R, and the resistance of the line segment of the second trace 161 between two adjacent large through holes 1351 is R, then the following is satisfied As shown in FIG. 5, when one of the connection sites in 3 large through holes 1351 is corroded (the cross in FIG. 5 indicates that the connection at one of the large through holes 1351 is corroded to fail), then/>
As shown in fig. 7, taking 3 second vias 151 and 3 first vias 131 as an example, before the connection sites fail,As shown in FIG. 8, when one connection site of 3 second vias 151 is corroded (the cross in FIG. 8 indicates that the connection at one second via 151 site is corroded and fails), then the/>
Thus, prior to failure by corrosion, the related art R Total (S) of fig. 4 is 1.5 times greater than the example of fig. 7, and thus embodiments of the present application reduce the total resistance of the first trace 121 and the second trace 161. After the corrosion occurs and fails, compared to the related art in fig. 5, the electrical signal may also be transferred through the second via 151 and the plurality of first vias 131 except for the corroded second via 151 in the example of fig. 8, so that the total resistance of the first trace 121 and the second trace 161 in the example of fig. 8 is also smaller. Thus, the present application reduces the total resistance of not only the first trace 121 and the second trace 161 before the occurrence of the corrosion failure, but also the first trace 121 and the second trace 161 after the occurrence of the corrosion failure.
In addition, when corrosion occurs at a portion of a certain second via hole 151, since the second metal layer 14 includes a material having higher corrosion resistance than the third metal layer 16, the second metal layer 14 can prevent the corrosion from further extending onto the first trace 121, thereby ensuring normal connection of the plurality of first via holes 131.
In the application, the connecting wire 141 is additionally arranged, the second wire 161 is connected with the connecting wire 141 through the second via hole 151, and the connecting wire 141 is connected with the first wire 121 through the first via hole 131, so that the second wire 161 is connected with the first wire 121 through the connecting wire 141, the second via hole 151 and the first via hole 131, and the total resistance of the first wire 121 and the second wire 161 before corrosion failure is reduced, and the total resistance of the first wire 121 and the second wire 161 after the corrosion failure is reduced. In the second aspect, since the second metal layer 14 includes a material having higher corrosion resistance than the third metal layer 16, the second metal layer 14 may block the corrosion from further extending onto the first trace 121, thereby ensuring normal connection of the plurality of first vias 131. In the third aspect, when corrosion occurs in a certain second via hole 151, an electrical signal is transmitted through the second via hole 151 and the plurality of first via holes 131 except the corroded second via hole 151, and it is further ensured that the total resistance of the first trace 121 and the second trace 161 after corrosion failure occurs can be reduced. In the fourth aspect, in the related art, the third metal layer 16 or the second wire 161 does not corrode, but moisture or the like reaches the first wire 121 through the second wire 161, so that the first wire 121 corrodes, and therefore, the second metal layer 14 or the connecting wire 141 in the embodiment of the present application blocks the path of the moisture reaching the first wire 121, so that the first wire 121 is ensured not to corrode.
In some embodiments, the second metal layer 14 includes at least two metal sublayers, at least one metal sublayer of the second metal layer 14 being more corrosion resistant than the third metal layer 16.
Illustratively, the second metal layer 14 includes at least two metal sublayers, and as long as one metal sublayer has higher corrosion resistance than the third metal layer 16, the corrosion may be blocked from further extending onto the first trace 121, thereby ensuring proper connection of the plurality of first vias 131. For example, the second metal layer 14 is a titanium/aluminum/titanium laminate structure.
In the case of other embodiments, where the second metal layer 14 includes a sub-metal layer of a plurality of mixed materials, the second metal layer 14 includes a material or element having a higher corrosion resistance than the third metal layer 16, the corrosion may be blocked from further extending onto the first trace 121, thereby ensuring proper connection of the plurality of first vias 131.
In some embodiments, the material of the second metal layer 14 includes at least one of titanium, chromium, nickel.
In some embodiments, the material of the third metal layer 16 includes at least one of transparent conductive metal oxide, copper, aluminum.
By way of example, the transparent conductive metal oxide may be Indium Tin Oxide (ITO).
On the one hand, the transparent conductive metal oxide, copper and aluminum materials are easy to corrode in a water vapor environment; on the other hand, the transparent conductive metal oxide, copper and aluminum are not compact enough, the water and gas isolation capability is not enough, and the water vapor can permeate the film layers of the materials to corrode the metal film layers below the via holes.
The titanium, chromium and nickel materials have good corrosion resistance, and water vapor cannot enter the lower metal film layer through the materials, so that the corrosion problem is avoided.
Referring to fig. 11 to 16, fig. 11 is a schematic cross-sectional view of a second array substrate according to an embodiment of the application at or in the direction of the C-C dashed line; FIG. 12 is a schematic diagram of a partial via failure in an equivalent circuit of a second array substrate according to an embodiment of the present application; FIG. 13 is a schematic cross-sectional view of a third array substrate according to an embodiment of the present application at or in the direction of the dotted line C-C; fig. 14 is a schematic diagram of a partial via failure in an equivalent circuit of a third array substrate according to an embodiment of the present application; FIG. 15 is a schematic cross-sectional view of a fourth array substrate according to an embodiment of the present application at or in the direction of the dotted line C-C; fig. 16 is a schematic diagram illustrating a partial via failure in an equivalent circuit of a fourth array substrate according to an embodiment of the present application.
Note that, fig. 7, 11, 13, and 15 are schematic cross-sectional views of the dashed line C-C in fig. 6, although fig. 13 and 15 do not correspond to the number of vias in fig. 6, because they are not illustrated in fig. 6, or fig. 13 and 15 illustrate a plurality of vias.
In some embodiments, the first insulating layer 13 includes a plurality of first vias 131, and the second insulating layer 15 includes a plurality of second vias 151; in the direction perpendicular to the plane of the substrate 11, at least a portion of the second vias 151 and the corresponding first vias 131 are overlapped, or/and at least a portion of the second vias 151 and the first vias 131 are offset.
Illustratively, at least a portion of the second via 151 overlaps the corresponding first via 131 in a direction perpendicular to the plane of the substrate 11.
In other examples, at least a portion of the second via 151 is offset from the first via 131.
In some embodiments, as shown in fig. 7 and 11, the number of first vias 131 is the same as the number of second vias 151. Fig. 7 and 11 illustrate that the plurality of second vias 151 and the plurality of first vias 131 are disposed offset or overlapping each other in a direction perpendicular to the plane of the substrate 11.
In the example of fig. 7, the number of first vias 131 is the same as the number of second vias 151; the second vias 151 and the first vias 131 are stacked in a direction perpendicular to the plane of the substrate 11. The thickness of the metal layer or the conductive layer is very large at the second via 151 and the first via 131, so that the resistance to water vapor permeation and the resistance to water vapor corrosion are enhanced.
In the example of fig. 11, the number of first vias 131 is the same as the number of second vias 151; in the direction perpendicular to the plane of the substrate 11, the second vias 151 and the first vias 131 are all arranged in a staggered manner, as shown in fig. 11 and 12, when corrosion occurs at a second via 151, the second insulating layer 13 has a good water vapor blocking effect because the first via 131 adjacent to the corrosion is covered by the second insulating layer 13, and the second insulating layer 13 protects the first via 131, so that water vapor can be prevented from reaching the first via 131.
Further, the material of the second insulating layer 16 is an inorganic material, so that water vapor can be better blocked.
In the present application, the overlapping arrangement of the two structures in the direction perpendicular to the plane of the substrate 11 means that the orthographic projections of the two structures on the substrate 11 at least partially overlap, for example, the second via 151 overlaps the first via 131 in the direction perpendicular to the plane of the substrate 11, which means that the orthographic projections of the second via 151 (which may refer to the region including the edge of the second via 151) on the substrate 11 at least partially overlap with the orthographic projections of the first via 131 (which may refer to the region including the edge of the first via 131) on the substrate 11.
In the present application, the offset arrangement of the two structures in the direction perpendicular to the plane of the substrate 11 means that the orthographic projections of the two structures on the substrate 11 do not overlap, for example, the second via 151 and the first via 131 are offset in the direction perpendicular to the plane of the substrate 11, which means that the orthographic projections of the second via 151 (which may refer to the region including the edge of the second via 151) on the substrate 11 and the orthographic projections of the first via 131 (which may refer to the region including the edge of the first via 131) do not overlap.
In some embodiments, as shown in fig. 13, the number of first vias 131 is less than the number of second vias 151; in the direction perpendicular to the plane of the substrate 11, the first via holes 131 are overlapped with the corresponding second via holes 151, and part of the second via holes 151 and the first via holes 131 are arranged in a staggered manner.
As shown in fig. 13 and 14, the second vias 151 include the same number of first sub-vias 1511 as the first vias 131, and at least one second sub-via 1512, where the first sub-vias 1511 are overlapped with the corresponding first vias 131 in the first direction Y, and the second sub-vias 1512 are offset from the first vias 131.
As shown in fig. 13 and 14, when the first sub-via 1511 is corroded, the signal may be continuously connected or transmitted through the second sub-via 1512 adjacent thereto, so that the total resistance of the first trace 121 and the second trace 161 after the corrosion failure is unchanged or the total resistance of the first trace 121 and the second trace 161 after the corrosion failure is increased to be smaller.
In some embodiments, as shown in fig. 15, the number of first vias 131 is greater than the number of second vias 151; in the direction perpendicular to the plane of the substrate 11, the second vias 151 are all overlapped with the corresponding first vias 131, and part of the first vias 131 and the second vias 151 are arranged in a staggered manner.
As shown in fig. 15 and 16, the first via 131 includes third sub-vias 1311, which are the same in number as the second vias 151, and at least one fourth sub-via 1312, and in the first direction Y, the third sub-via 1311 is disposed overlapping the corresponding second via 151, and the fourth sub-via 1312 and the second via 151 are both disposed offset.
As shown in fig. 15 and 16, when the second via 151 and the corresponding third sub-via 1311 are corroded, signals may be continuously connected or transmitted through the fourth sub-via 1312 adjacent thereto, so that the total resistance of the first trace 121 and the second trace 161 after corrosion failure increases less.
In some embodiments, the extending direction of the connecting trace 141 is consistent with the extending direction of the first trace 121, and one connecting trace 141 corresponds to the plurality of first vias 131.
In other embodiments, the connecting wires 141 are in a block shape and island shape, and one connecting wire corresponds to at least 3 first through holes 131 and at least 3 second through holes 151, so as to achieve the effects of preventing corrosion and reducing resistance.
In some embodiments, the array substrate 100 includes a plurality of thin film transistors, and at least one of a pixel electrode and a common electrode;
the first metal layer 12 also includes the gate of the thin film transistor;
the first insulating layer 13 is a gate insulating layer;
The second metal layer 14 also includes a source and a drain of the thin film transistor;
the third metal layer 16 further includes a pixel electrode or a common electrode.
The array substrate 100 includes a plurality of thin film transistors, and pixel electrodes and a common electrode for driving liquid crystal molecules to rotate to display an image. The array substrate 100 includes a pixel electrode or the array substrate 100 includes a pixel electrode and a common electrode, and the pixel electrode is electrically connected to a corresponding thin film transistor.
Illustratively, the first metal layer 12 forms both the first trace 121 and the gate of the thin film transistor, and the first trace 121 and the gate of the thin film transistor are disposed in the same material. The second metal layer 14 forms the connecting trace 141 and the source and drain of the thin film transistor, and the connecting trace 141 and the source and drain of the thin film transistor are disposed in the same material. The third metal layer 16 forms the second wire 161 and the pixel electrode at the same time, the second wire 161 and the pixel electrode are disposed in the same layer and are disposed in the same material, or the third metal layer 16 forms the second wire 161 and the common electrode at the same time, and the second wire 161 and the common electrode are disposed in the same layer and are disposed in the same material. The first wiring, the first insulating layer, the connecting wiring 141, the second insulating layer 15 and the second wiring 151 are arranged on the same layer as the plurality of functional layers or the functional wirings of the array, so that the manufacturing process steps of the array substrate 100 are reduced, and meanwhile, the first wiring, the connecting wiring 141 and the second wiring 151 can also well provide electrical signals with various functions in the array substrate 100.
In some embodiments, the array substrate 100 includes a display area and a non-display area around the display area, and the first trace 121, the connection trace 141, and the second trace 161 are all located in the non-display area.
For example, in the non-display area, the second trace 161 is more likely to contact water vapor, and the problem of corrosion in the non-display area is more serious.
For example, the first wiring 121, the connection wiring 141, and the second wiring 161 may be used to provide a clock signal of a gate driving circuit, a start signal of the gate driving circuit, a common signal of a display area common electrode, and the like.
In the present application, there is also provided a method for manufacturing an array substrate, wherein the array substrate 100 of any one of the above-mentioned embodiments may be manufactured by using the method for manufacturing an array substrate, the method for manufacturing an array substrate comprising the steps of: s10, S20, S30, S40, S50 and S60.
S10, providing a substrate 11.
S20, forming a first metal layer 12 on the substrate 11, and patterning the first metal layer 12 to form at least one first trace 121.
S30, forming a first insulating layer 13 on the first metal layer 12, and patterning the first insulating layer 13 to form at least one first via 131.
S40, forming a second metal layer 14 on the first insulating layer 13, and patterning the second metal layer 14 to form at least one connection trace 141, where the connection trace 141 is connected to the corresponding first trace 121 through the first via 131.
S50, forming a second insulating layer 15 on the second metal layer 14, and patterning the second insulating layer 15 to form at least one second via 151.
S60, a third metal layer 16 is formed on the second insulating layer 15, and at least one second trace 161 is formed by patterning the third metal layer 16, where the second trace 161 is connected to the corresponding connection trace 141 through the second via 151.
The present application also provides a display panel including the array substrate 100 of any one of the above.
The display panel may be a liquid crystal display panel, for example, but is not limited thereto.
For example, when the display panel is a liquid crystal display panel, the display panel may further include a color film substrate disposed opposite to the array substrate 100, and the display panel further includes a liquid crystal layer disposed between the color film substrate and the array substrate 100.
In the foregoing embodiments, the descriptions of the embodiments are focused on, and for those portions of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.
While preferred embodiments of the present description have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present specification without departing from the spirit or scope of the specification. Thus, if such modifications and variations of the present specification fall within the scope of the claims and the equivalents thereof, the present specification is also intended to include such modifications and variations.

Claims (11)

1. An array substrate, characterized by comprising:
A substrate;
the first metal layer is arranged on one side of the substrate and comprises at least one first wire;
the first insulating layer is arranged on one side, far away from the substrate, of the first metal layer, and comprises at least one first via hole;
The second metal layer is arranged on one side, far away from the substrate, of the first insulating layer and comprises at least one connecting wire;
the second insulating layer is arranged on one side, far away from the substrate, of the second metal layer, and comprises at least one second via hole;
The third metal layer is arranged on one side, far away from the substrate, of the second insulating layer and comprises at least one second wiring;
The first via hole and the first wiring are overlapped in the direction perpendicular to the plane of the substrate, and the connecting wiring is connected with the first wiring through the first via hole;
The second via hole is overlapped with the connecting wire in the direction perpendicular to the plane of the substrate, and the second wire is connected with the connecting wire through the second via hole;
wherein the second metal layer comprises a material having a higher corrosion resistance than the third metal layer.
2. The array substrate of claim 1, wherein the second metal layer comprises at least two metal sublayers, at least one of the metal sublayers of the second metal layer being more corrosion resistant than the third metal layer.
3. The array substrate of claim 1, wherein the material of the second metal layer comprises at least one of titanium, chromium, and nickel.
4. The array substrate of claim 1, wherein the material of the third metal layer comprises at least one of transparent conductive metal oxide, copper, and aluminum.
5. The array substrate of any one of claims 1 to 4, wherein the first insulating layer comprises a plurality of the first vias and the second insulating layer comprises a plurality of the second vias;
At least part of the second through holes are overlapped with the corresponding first through holes in the direction perpendicular to the plane of the substrate; or/and (or)
At least part of the second through holes and the first through holes are arranged in a staggered mode.
6. The array substrate of claim 5, wherein the number of first vias is the same as the number of second vias;
And in the direction perpendicular to the plane of the substrate, the second through holes and the first through holes are arranged in a staggered mode or overlapped mode.
7. The array substrate of claim 5, wherein the number of first vias is less than the number of second vias;
In the direction perpendicular to the plane of the substrate, the first through holes are overlapped with the corresponding second through holes, and part of the second through holes are staggered with the first through holes.
8. The array substrate of claim 5, wherein the number of first vias is greater than the number of second vias;
In the direction perpendicular to the plane of the substrate, the second through holes are overlapped with the corresponding first through holes, and part of the first through holes and the second through holes are arranged in a staggered mode.
9. The array substrate according to any one of claims 1 to 4, wherein the array substrate includes a plurality of thin film transistors and at least one of a pixel electrode and a common electrode;
the first metal layer further comprises a gate electrode of the thin film transistor;
the first insulating layer is a gate insulating layer;
The second metal layer further comprises a source electrode and a drain electrode of the thin film transistor;
the third metal layer further includes the pixel electrode or the common electrode.
10. The array substrate of any one of claims 1 to 4, wherein the array substrate comprises a display region and a non-display region around the display region, the first trace, the connection trace, and the second trace are all located in the non-display region.
11. A display panel comprising the array substrate according to any one of claims 1 to 10.
CN202410190276.4A 2024-02-20 2024-02-20 Array substrate and display panel Pending CN118016676A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202410190276.4A CN118016676A (en) 2024-02-20 2024-02-20 Array substrate and display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202410190276.4A CN118016676A (en) 2024-02-20 2024-02-20 Array substrate and display panel

Publications (1)

Publication Number Publication Date
CN118016676A true CN118016676A (en) 2024-05-10

Family

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Family Applications (1)

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CN202410190276.4A Pending CN118016676A (en) 2024-02-20 2024-02-20 Array substrate and display panel

Country Status (1)

Country Link
CN (1) CN118016676A (en)

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