CN112867236B

CN112867236B - IC package substrate and method for manufacturing IC package substrate

Info

Publication number: CN112867236B
Application number: CN202110082734.9A
Authority: CN
Inventors: 石新红; 周华梅; 黄剑; 张军; 黄丽君; 付海涛
Original assignee: Shanghai Meadville Science and Technology Co Ltd
Current assignee: Shanghai Meadville Science and Technology Co Ltd
Priority date: 2021-01-21
Filing date: 2021-01-21
Publication date: 2023-06-06
Anticipated expiration: 2041-01-21
Also published as: CN112867236A

Abstract

The invention provides an IC package substrate and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing a core plate with a first surface and a second surface opposite to each other, forming a plurality of first holes in the core plate from the first surface, filling a first conductive material in the first holes, forming a plurality of second holes in the core plate from the second surface, filling a second conductive material in the second holes, wherein the first conductive material in the first holes forms first conductive columns, and the second conductive material in the second holes forms second conductive columns to dissipate heat. In the manufacturing of the IC packaging substrate, the heat dissipation of the printed circuit board is realized through the high-density through holes, the existing manufacturing method of the buried copper block is replaced based on the through hole filling mode, the heat dissipation structure and the circuit layer can be further manufactured, the heat dissipation effect of the circuit board is improved, the stability of the structure is improved, the manufacturing process is simplified, the process efficiency is improved, and the manufacturing method is suitable for batch production.

Description

IC package substrate and method for manufacturing IC package substrate

Technical Field

The invention belongs to the field of circuit board manufacturing, in particular to an IC packaging substrate and a manufacturing method of the IC packaging substrate, and in particular relates to a printed circuit board and a manufacturing method of the printed circuit board.

Background

Along with the development of diversification, multifunction and high integration of electronic products in the modern society, the high-density and diversified structural design of the PCB is promoted. In particular, with the advent of the 5G age, high frequency and high speed PCBs are becoming more and more widely used. High frequency high speed PCBs are required to provide high speed, low loss, low delay, high quality signal transmission, and to accommodate high power consumption environments of high frequency high power devices. The larger the internal power consumption of the PCB and the crowded heat dissipation channel, the whole heat can be rapidly increased, and the electrical performance of the PCB is easily reduced or even damaged during long-term operation. Therefore, it is particularly important to solve the heat dissipation problem of the PCB.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an IC package substrate and a method for manufacturing the IC package substrate, which are used for solving the problems of heat dissipation and the like of the printed circuit board of the IC package substrate technology in the prior art.

To achieve the above and other related objects, the present invention provides a method for manufacturing an IC package substrate, the method comprising the steps of:

providing a core plate having opposed first and second faces;

first perforating the core plate from the first face to form a number of first holes in the core plate;

Filling a first conductive material in the first hole, wherein the first conductive material extends to at least the first face;

forming a plurality of second holes in the core plate by performing a second hole opening from the second face to the core plate, wherein a space is reserved between the first holes and the second holes;

filling a second conductive material in the second hole, wherein the second conductive material extends to at least the second face;

the first conductive material in the first hole forms a first conductive column, the second conductive material in the second hole forms a second conductive column, and the first conductive column and the second conductive column are formed in the core board to dissipate heat.

Optionally, the step of filling the first hole with the first conductive material includes:

forming a first conductive layer of a first thickness on at least the first hole inner wall and the first surface around the first hole;

forming a first dry film exposing the first hole on at least the first face;

forming a second conductive layer in the first hole to form the first conductive pillar;

and/or the step of filling the second conductive material in the second hole comprises:

forming a third conductive layer of a second thickness on at least the second hole inner wall and the second face around the second hole;

Forming a second dry film exposing the second hole on at least the second face;

a fourth conductive layer is formed in the second hole to form the second conductive post.

Optionally, the first hole and the second hole penetrate through the core board, the first conductive layer is formed on the surfaces of the first face and the second face at the same time, the third conductive layer is formed on the first conductive layer on the surfaces of the first face and the second face, and the first conductive layer and the second conductive layer form a circuit preparation layer located on two sides of the core board.

Optionally, the first conductive layer and the third conductive layer are both flash plated; the first thickness is approximately the same as the second thickness.

Optionally, a plurality of first windows are formed in the first dry film, the first windows correspondingly expose the first holes, and the distance between the first windows and the edges of the first holes is 20-200 μm; and/or a plurality of second windows are formed in the second dry film, the second windows correspondingly expose the second holes, and the distance between the second windows and the edges of the second holes is 20-200 mu m.

Optionally, the second conductive layer adopts a pulse plating process, so that the surface of the second conductive layer is not higher than the surface of the first dry film; and/or the second conductive layer adopts a pulse electroplating process, so that the surface of the fourth conductive layer is not higher than the surface of the second dry film.

Optionally, the step of removing the dry film after forming the second conductive layer in the first hole is further included, so as to obtain the first conductive post flush with the surface of the first conductive layer; and/or, the step of removing the second dry film after forming the fourth conductive layer in the second hole is further included, so as to obtain the second conductive post which is flush with the surface of the third conductive layer.

Optionally, the manufacturing method further comprises the steps of: and carrying out an nth opening on the core plate to form a plurality of nth holes in the core plate, wherein N is more than or equal to 3, and the first opening to the nth opening are alternately carried out on a first face and a second face of the core plate.

Optionally, the first hole includes a plurality of first hole unit columns, the second hole includes a plurality of second hole unit columns, where the first hole unit columns and the second hole unit columns are alternately arranged at intervals, and the second holes in the second hole unit columns are correspondingly located between adjacent first holes in adjacent first hole unit columns.

The invention also provides an IC package substrate manufactured by the manufacturing method of the IC package substrate according to any one of the schemes, and the IC package substrate comprises:

A core plate having opposed first and second faces;

a plurality of first holes formed in the core plate from the first face;

a plurality of second holes formed in the core plate from the second face;

a first conductive material filled in the first hole and extending at least to the first face;

a second conductive material filled in the second hole and extending at least to the second face;

Optionally, the first conductive material includes a first conductive layer and a second conductive layer, the first conductive layer is formed at least on the inner wall of the first hole and the first surface around the first hole, and the second conductive layer is filled in the first hole; and/or the second conductive material comprises a third conductive layer and a fourth conductive layer, wherein the third conductive layer is at least formed on the inner wall of the second hole and the second surface around the second hole, and the fourth conductive layer is filled in the second hole.

As described above, the IC package substrate and the manufacturing method of the IC package substrate realize heat dissipation of the printed circuit board through the high-density through holes, replace the existing manufacturing method of the buried copper block based on the mode of filling holes of the through holes, can also manufacture the heat dissipation structure and the circuit layer, improve the heat dissipation effect of the circuit board, improve the stability of the structure, simplify the manufacturing process, improve the process efficiency and be suitable for batch production.

Drawings

Fig. 1 is a flow chart illustrating an exemplary IC package substrate manufacturing process according to the present invention.

Fig. 2 is a schematic diagram of a core board provided in the fabrication of an exemplary IC package substrate according to the present invention.

Fig. 3 is a schematic diagram illustrating a first opening performed in the fabrication of an IC package substrate according to an example of the present invention.

Fig. 4 is a schematic diagram illustrating formation of a first conductive layer in manufacturing an IC package substrate according to an exemplary embodiment of the invention.

Fig. 5 is a schematic diagram illustrating formation of a first dry film in manufacturing an IC package substrate according to an embodiment of the invention.

Fig. 6 is a schematic diagram illustrating formation of a second conductive layer in manufacturing an IC package substrate according to an exemplary embodiment of the present invention.

Fig. 7 is a schematic diagram of an exemplary IC package substrate manufactured by polishing according to the present invention.

Fig. 8 is a schematic diagram illustrating formation of a first conductive pillar in manufacturing an IC package substrate according to an exemplary embodiment of the invention.

Fig. 9 is a schematic diagram illustrating a second opening performed in the fabrication of an IC package substrate according to an example of the present invention.

Fig. 10 is a schematic layout diagram illustrating formation of a first hole and a second hole in fabrication of an IC package substrate according to an example of the present invention.

Fig. 11 is a schematic diagram illustrating formation of a third conductive layer in manufacturing an IC package substrate according to an exemplary embodiment of the invention.

Fig. 12 is a schematic diagram illustrating formation of a second dry film in manufacturing an IC package substrate according to an example of the present invention.

Fig. 13 is a schematic diagram illustrating formation of a fourth conductive layer in manufacturing an IC package substrate according to an embodiment of the invention.

Fig. 14 is a schematic diagram illustrating polishing in manufacturing an IC package substrate according to an example of the present invention.

Fig. 15 is a schematic diagram illustrating formation of a second conductive pillar in manufacturing an IC package substrate according to an exemplary embodiment of the present invention.

Fig. 16 shows a comparison of the positioning method in an example of the present invention with the positioning method of the prior art.

Fig. 17 shows SEM images of the first and second hole distributions and the holes obtained by the prior art method in an example of the present invention.

Fig. 18 shows a flash plating process route diagram provided in an example of the invention.

Description of element reference numerals

100. Core board

100a first side

100b second side

101. A first hole

102. A first conductive layer

103. First dry film

103a first window

104. Second conductive layer

105. First conductive column

106. First conductive material

107. Second hole

108. Third conductive layer

109. Circuit preparation layer

110. Second dry film

110a second window

111. Fourth conductive layer

112. Second conductive column

113. Second conductive material

S1 to S5 steps

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present. In addition, "between … …" as used in the present invention includes two end points.

In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.

As shown in fig. 1, the present invention provides a method for manufacturing an IC package substrate, in particular to a method for manufacturing a printed circuit board, which includes the following steps:

s1, providing a core plate, wherein the core plate is provided with a first surface and a second surface which are opposite;

s2, carrying out first punching on the core plate from the first surface to form a plurality of first holes in the core plate;

s3, filling a first conductive material in the first hole, wherein the first conductive material at least extends to the first face;

S4, carrying out second punching on the core plate from the second surface to form a plurality of second holes in the core plate, wherein a space is reserved between the first holes and the second holes;

s5, filling a second conductive material in the second hole, wherein the second conductive material at least extends to the second face;

The method for manufacturing an IC package substrate according to the present invention will be described in detail with reference to the accompanying drawings, wherein the above-mentioned order is not strictly representative of the manufacturing order of the method for manufacturing an IC package substrate protected by the present invention, and those skilled in the art can vary the order of steps according to actual processes. Wherein fig. 1 only shows steps of an IC package substrate in an example.

First, as shown in S1 and fig. 2 in fig. 1, a core plate 100 is provided, the core plate 100 having opposite first and

second faces

100a and 100b. Wherein the core plate 100 may include: different resin adhesives adopted by the board comprise phenolic resin, epoxy resin, polyester resin, bismaleimide modified triazine resin (BT), polyimide resin (PI), diphenylene ether resin (PPO), maleimide-styrene resin (MS), polycyanate resin, polyolefin resin and the like, wherein the thickness of the core board 100 can be 20-5 mm, for example, 50 μm and 100 μm, and the structure for preparing the circuit board can also comprise the existing processes of cutting, inner layer pattern manufacturing and the like.

In an example, the first and

second faces

100a, 100b may be front and back faces of a core plate, e.g., corresponding to the upper and lower faces in fig. 2.

Next, as shown in S2 in fig. 1 and fig. 3, the core plate 100 is perforated from the first face 100a for the first time to form a plurality of first holes 101 in the core plate 100.

As an example, the process of performing the first opening may employ mechanical drilling. In one example, the drill rate is between 20-500krpm, which may be 50krpm, 100krpm, 200krpm; the feeding speed is between 3 and 100mm/s, and can be 10mm/s, 20mm/s and 50mm/s; the retracting speed is between 1 and 500mm/s, and can be 10mm/s, 100mm/s and 200mm/s. Adaptable to different holes. In addition, in an example, in order to be beneficial to ensuring the verticality of the hole wall, a double-edge single-groove drilling tool is preferably adopted, the swinging of the drilling tool is small when the rotating speed is high, the cutting tool is stable, the alignment precision is high, and the precision of the hole diameter is higher than that of the single edge. The friction area between the drill bit and the hole wall during drilling can be reduced, the obtained hole wall is smooth, the hole type is good, and the selection of the drill bit is very important for the hole type, so that the double-sided drilling process is realized.

In addition, in an example, especially for the through hole with high precision requirement, the backing plate selects phenolic backing plate (with high density, less impurity and less orifice burr) during drilling, and the cover plate selects aluminum sheet containing water-soluble LE coating, so that the lubricity and heat dissipation performance can be increased, and the hole position precision can be effectively improved, for example: for a bore diameter of 0.05-0.3mm, when the rotating speed is 100-200krpm and the feed speed is 10-50mm/s, the drilling precision Cpk is only 1-2 by adopting a common rate cover plate, and the drilling precision Cpk is 2-3 by adopting an aluminum sheet containing a water-soluble LE coating.

The number and positions of the first holes 101 may be set according to actual requirements. Additionally, in one example, as shown in fig. 3, the first hole 101 may extend through the core plate 100 to facilitate subsequent process design. In other examples, the first hole 101 may also extend into the core plate 100 to a depth that does not extend through the core plate 100. In addition, in other examples, the first hole 101 may be prepared as an inclined hole to meet the heat dissipation requirement. In this embodiment, a vertical hole is selected.

Next, as shown in S3 in fig. 1 and fig. 4-8, the first hole 101 is filled with a first conductive material 106, and the first conductive material 106 extends at least to the first face 100a. The first conductive material 106 in the first hole 101 forms a first conductive post 105, so that heat can be dissipated from the obtained printed circuit board based on the first conductive post 105.

Wherein, in an example where the first hole 101 has not penetrated through the core board 100, the first conductive material 106 may be filled in the first hole 101 and extend to the first surface 100a, and a metal line may be prepared based on the first conductive material 106 located on the first surface 100 a.

In another example, as shown in fig. 8, the first hole 101 penetrates the core plate 100, and the first conductive material 106 fills the first hole 101 and extends to the first face 100a and the second face 100b, and a double-sided metal line may be prepared based on the first conductive material 106 located on the first face 100a and the second face 100 b.

As an example, as shown in fig. 4-8, the step of filling the first hole 101 with the first conductive material 106 includes:

as shown in fig. 4, first, a first conductive layer 102 having a first thickness is formed on at least the inner wall of the first hole 101 and the surface of the first surface 100a around the first hole 101; of course, when the first hole 101 penetrates the core board 100, the first conductive layer 102 is also formed on the surface of the second face 100 b.

Specifically, the first conductive layer 102 is prepared by a flash plating process, the flash plating process adopts direct current or pulse plating, the copper thickness in the hole/hole opening copper thickness is controlled to be greater than 120%, and can be 130%, 150% and 180%, wherein the copper thickness in the hole/hole opening copper thickness is defined as TP value. In one example, pulse plating is used during flash plating, and a strong reverse current is used for reverse plating time, wherein in one example the strong reverse current is selected to be between 20-45ASD, preferably between 35-40 ASD. Further, the ratio of the reverse time/total period is controlled to be 4% -5%, so that the TP value is controlled to be 120% -150%. In the reverse direction, the orifice is a high current region, and the dissolution speed is far higher than that of the hole, so that the copper thickness in the hole is obviously thicker than that of the orifice. Is favorable for the liquid medicine exchange during the later hole filling. Holes are not easy to generate in the later hole filling process. Meanwhile, in order to further control the copper thickness of the surface, a plating solution containing iron ions is used in the electroplating process. In normal electroplating, the concentration of iron ions is typically 0.1-5g/l, whereas in the present system, the concentration of iron ions is raised to 5-20g/l.

In one example, as shown in FIG. 18, a specific flash process roadmap is provided, where t _1old /t _fwd Forward plating between two reverse pulses at positive time (ms)&Interruption time; t is t _1new /t _total =one cycle time (ms) -forward electroplating&Interrupt&Reverse pulseTime; t is t ₂ lt _rev Reverse time (ms) -anodic pulse time on cathode; t is t ₃ /lt _{start_P} Positive plating time before interruption; t is t ₄ /t _p Time to break (ms) -time to slow down crystallization of copper crystals; i.e _avr =average current-average plating current on the cathode; i.e _rev Reverse current-current on board "when anode" plate surface; i.e _fwd Positive current-plating current at cathode.

In addition, the process of performing PTH is also included before flash plating, and can be performed by adopting the prior art process. For example, it may be that: alkaline degreasing (which may be one or two), 2 or 3 times of countercurrent flushing, coarsening (microetching), secondary countercurrent flushing, pre-dip, activation, secondary countercurrent flushing, debonding, secondary countercurrent flushing, sinking, secondary countercurrent flushing and acid washing (which may be added).

As shown in fig. 5, next, a first dry film 103 exposing the first hole 101 is formed on at least the first face 100 a; wherein the first dry film 103 is formed on the surface of the first conductive layer 102. Of course, when the first hole 101 penetrates the core board 100, the first dry film 103 is also formed on the second face 100b, that is, the surface of the first conductive layer 102 formed on the second face 100 b.

As an example, the first dry film 103 is selected to be a polyacrylic acid system dry film, and may be a positive or negative dry film. In one example, the copper surface is roughened by a method of roughening, such as super roughening, sand blasting, microetching, etc., before electroplating, and then film-pressing electroplating is performed, so that the problem of plating penetration caused by poor bonding force between the dry film and the copper surface, which may occur during electroplating, is advantageously prevented. In addition, the development point is controlled to be 50-70%, for example, 55% or 60% in development.

As an example, a plurality of first windows 103a are formed in the first dry film 103, and the first windows 103a correspondingly expose the first holes 101, and a distance between the first windows and edges of the first holes 101 is between 20-200 μm, for example, 60 μm, 65 μm, 80 μm, and 90 μm. The distance from the edge of the first hole 101 may be the distance between the surface of the inner wall of the hole and the inner wall of the first window 103a, which is formed by the first conductive layer 102 after the first conductive layer 102 is formed. For example, the first hole 101 is circular, and the first window 103a is circular, and the two windows are concentrically formed, and the distance is the difference between the radii of the two windows.

As shown in fig. 6-8, finally, a second conductive layer 104 is formed in the first hole 101 to form the first conductive pillar 105. In one example, the first conductive pillar 105 may be obtained by: as shown in fig. 6, a second conductive layer 104 is formed in the first hole 101 after the first dry film 103 is formed, preferably, the second conductive layer 104 is formed by using a pulse plating process, so that the surface of the second conductive layer 104 is not higher than the surface of the first dry film 103, the second conductive layer 104 is formed by using a pulse plating process, and the plating of the second conductive layer 104 is matched with a flash plating process for forming the first conductive layer 102, so as to fill the first hole 101.

As shown in fig. 7, the second conductive layer 104 on the surface is removed, and the first dry film 103 is attached to the second conductive layer for polishing until the first dry film 103 is substantially completely removed; finally, as shown in fig. 8, the remaining first dry film 103 is removed, and the first conductive pillars 105 are obtained. Wherein, the grinding plate can adopt modes of 3M grinding plate, thinning and adding 3M grinding plate, electrochemical polishing and the like. And (3) adopting a plate grinding mode until the dry film is polished to part of copper leakage, carrying out film stripping treatment, and removing a small amount of residual dry film.

Specifically, the material of the second conductive layer 104 may be the same as or different from the material of the first conductive layer 102, both may be copper, of course, both may be different, the first conductive pillars 105 may be prepared based on the second conductive material layer 104, and a suitable material of the second conductive layer 104 may be selected based on the first conductive layer, so as to facilitate heat dissipation, and meanwhile, the first conductive layer 102 is formed on the surface of the core board, a metal circuit may be prepared, and reasonable material arrangement may be performed based on the first conductive layer.

Next, as shown in S4 in fig. 1 and fig. 9-10, the core plate 100 is perforated a second time from the second face 100b to form a plurality of second holes 107 in the core plate 100, the first holes 101 and the second holes 107 having a space therebetween. The number and positions of the second holes 107 may be set according to actual requirements. Additionally, in one example, as shown in fig. 9, the second holes 107 may extend through the core plate 100 to facilitate subsequent process design. In other examples, the second hole 107 may also extend into the core plate 100 to a depth that does not extend through the core plate 100. In addition, in other examples, the second hole 107 may be prepared as an inclined hole to meet the heat dissipation requirement. In this embodiment, a vertical hole is selected.

In an example, as shown in fig. 10, the first hole 101 includes a plurality of first hole unit columns, the second hole 107 includes a plurality of second hole unit columns, where the first hole unit columns and the second hole unit columns are alternately arranged at intervals, and the second holes in the second hole unit columns are correspondingly located between adjacent first holes in adjacent first hole unit columns. That is, during secondary drilling, the holes may be designed in the interval between the first holes, and it may be considered that the first holes 101 and the second holes 107 form a hexagonal arrangement structure, so that the density of the through holes may be improved, the number and the density of the holes may be increased, the local heat conducting performance may be improved, and the heat dissipating performance of the circuit board may be improved. Further, the first hole 101 and the second hole 107 of the present invention are formed by double-sided perforation, so that warpage caused by single-sided stress can be reduced; and secondary drilling is carried out after electroplating is completed, so that the strength of the local area is increased. When the holes are too dense, carbonization can occur due to heat concentration, and the plate surface is blackened and yellow. After the hole density is increased, the problem of hole deviation and hole connection easily occurs.

As an example, the second hole 107 may be formed by mechanical drilling. In one example, the drill rate is between 20-500krpm, which may be 50krpm, 100krpm, 200krpm; the feeding speed is between 3 and 100mm/s, and can be 10mm/s, 20mm/s and 50mm/s; the retracting speed is between 1 and 500mm/s, and can be 10mm/s, 100mm/s and 200mm/s. Adaptable to different holes. In addition, in an example, in order to be beneficial to ensuring the verticality of the hole wall, a double-edge single-groove drilling tool is preferably adopted, the swinging of the drilling tool is small when the rotating speed is high, the cutting tool is stable, the alignment precision is high, and the precision of the hole diameter is higher than that of the single edge. The friction area between the drill bit and the hole wall during drilling can be reduced, the obtained hole wall is smooth, the hole type is good, and the selection of the drill bit is very important for the hole type, so that the double-sided drilling process is realized.

In another example, the method further includes the step of fabricating the pilot hole after forming the first hole, wherein the density may be increased by drilling from the second side at the time of the second drilling. Currently, it is common practice to use L-holes, or four through holes for positioning. The deviation of drilling positioning is +/-25um, and when holes are dense, the problem of connecting holes is easy to generate. In this example, the alignment may be: in order to effectively prevent the positioning deviation, N positioning holes are drilled after the X-plane (first hole is formed), for example, N is 6 or more for positioning of the Y-plane (second hole is formed). Thereby reducing positional deviation due to deformation and warpage of the drilling plate. In addition, referring to fig. 16, in an example, N pilot holes drilled by the present invention form a circle. The circle centers of the N large circles are grabbed as positioning points when the holes are drilled next time (the second holes are formed), so that the problem of alignment precision caused by low roundness and the like of the burrs of the orifices of the single holes can be avoided.

As an example, the first hole 101 and the second hole 107 are identical in shape and size. Of course, in other examples, the shapes may be the same or different. In addition, as shown in fig. 17, an SEM image of the distribution of the first and second holes of the prior art and the design of the present application is provided. For example, single-sided drilling is adopted, when the diameter of the holes is 0.2mm, and the disc spacing is 0.2mm, the number of holes in the 5 x 5cm area is 15378, when the scheme is adopted, the first-sided drilling is completed, and then the mode of secondary drilling is adopted, so that the number of holes in the area is 30752 holes, and the number is increased by about one time.

As an example, the first hole 101 is in a truncated cone shape from the first surface to the second surface; the second hole 107 is truncated cone-shaped from the second surface to the first surface. That is, for forming the first hole 101, in this example, an inverted truncated cone-shaped first hole 101 is prepared, and the dimension of the upper-lower cross section is large from the first face down (the direction of the first face toward the second face); for forming the second hole 107, in this example, an inverted truncated cone-shaped second hole 107 is prepared, and the dimension of the upper-lower cross section is large upper-lower as viewed from the second face downward (the direction of the second face toward the first face).

Finally, as shown in S5 of fig. 1 and fig. 11-15, a second conductive material 113 is filled in the second hole 107, and the second conductive material 113 extends at least to the second surface 100b. The second conductive material 113 in the second hole 107 forms a second conductive post 112, so that heat can be dissipated from the obtained printed circuit board based on the second conductive post 112.

Wherein, in an example, the second hole 107 has not penetrated through the core board 100, the second conductive material 113 may be filled in the second hole 107 and extend to the second face 100b, and a metal line may be prepared based on the second conductive material 113 located on the second face 100b.

In another example, as shown in fig. 15, the second hole 107 penetrates the core board 100, the second conductive material 113 fills the second hole 107 and extends to the first face 100a and the second face 100b, and a double-sided metal line may be prepared based on the second conductive material 113 located on the first face 100a and the second face 100 b.

As an example, as shown in fig. 11 to 15, the step of filling the second hole 107 with the second conductive material 113 includes:

as shown in fig. 11, first, a third conductive layer 108 of a second thickness is formed on at least the inner wall of the second hole 107 and the second surface 100b around the second hole 107; of course, when the second hole 107 penetrates the core 100, the third conductive layer 108 is also formed on the second face 100 b. In this embodiment, the third conductive layer 108 is formed on the surface of the first conductive layer 102, and the third conductive layer and the first conductive layer may be used together as the subsequent circuit preparation layer 109 to prepare the metal wiring.

In an example, the first thickness is equal to the second thickness, i.e., the first thickness and the second thickness may be half the thickness of the target metal (target line layer thickness), although the same here means that the values of the half thicknesses may fluctuate over a range. Of course, the first thickness and the second thickness may also have other proportional relationships, so as to be suitable for the arrangement of the subsequent circuit, for example, the second thickness is required to be 2-5 times of the first thickness, so as to meet the shape of the subsequent circuit pattern. That is, the subsequent line preparation can be efficiently performed based on the process of the present invention.

In an example, the first conductive layer 102 and the third conductive layer 108 are the same material, such as copper; in other examples, the materials of the two may also be different, resulting in a desired metal line based on the different materials.

Specifically, the third conductive layer 108 is prepared by a flash plating process. Flash plating adopts direct current or pulse plating, and the copper thickness in the hole/hole opening copper thickness is controlled to be more than 120 percent and can be 130 percent, 150 percent and 180 percent, wherein the copper thickness in the hole/hole opening copper thickness is defined as TP value. In one example, pulse plating is used during flash plating, and a strong reverse current is used for reverse plating time, wherein in one example the strong reverse current is selected to be between 20-45ASD, preferably between 35-40 ASD. Further, the ratio of the reverse time/total period is controlled to be 4% -5%, so that the TP value is controlled to be 120% -150%. In the reverse direction, the orifice is a high current region, and the dissolution speed is far higher than that of the hole, so that the copper thickness in the hole is obviously thicker than that of the orifice. Is favorable for the liquid medicine exchange during the later hole filling. Holes are not easy to generate in the later hole filling process. Meanwhile, in order to further control the copper thickness of the surface, a plating solution containing iron ions is used in the electroplating process. In normal electroplating, the concentration of iron ions is typically 0.1-5g/l, whereas in the present system, the concentration of iron ions is raised to 5-20g/l.

In one example, as shown in FIG. 18, a specific flash process roadmap is provided, where t _1old /t _fwd Forward plating between two reverse pulses at positive time (ms)&Interruption time; t is t _1new /t _total =one cycle time (ms) -forward electroplating&Interrupt&Reverse pulse time; t is t ₂ lt _rev Reverse time (ms) -anodic pulse time on cathode; t is t ₃ /lt _{start_P} Positive plating time before interruption; t is t ₄ /t _p Time to break (ms) -time to slow down crystallization of copper crystals; i.e _avr =average current-average plating current on the cathode; i.e _rev Reverse current-current on board "when anode" plate surface; i.e _fwd Positive current-plating current at cathode.

As shown in fig. 12, next, a second dry film 110 exposing the second hole 107 is formed at least on the second face 100 b; wherein the second dry film 110 is formed on the surface of the third conductive layer 108. Of course, when the second hole 107 penetrates the core board 100, the second dry film 110 is also formed on the first face 100a, that is, the surfaces of the third conductive layer 108 formed on the second face 100b and the first face 100 a.

As an example, the material and forming process of the second dry film 110 may be the same as those of the first dry film 103. In addition, the second dry film 110 further has a second window 110a, and the second window 110a is disposed in correspondence with the first window 103 a.

As shown in fig. 13-15, finally, a fourth conductive layer 111 is formed in the second hole 107 to form the second conductive post 112. The second conductive pillar 112 may be formed by referring to the first conductive pillar 105. For example, as shown in fig. 13, a fourth conductive layer 111 is formed in the second hole 107 after the second dry film 110 is formed, and preferably, the fourth conductive layer 111 is formed by a pulse plating process such that the surface of the fourth conductive layer 111 is not higher than the surface of the second dry film 110; the fourth conductive layer 111 adopts a pulse plating process, and the plating of the fourth conductive layer 111 is matched with a flash plating process for forming the third conductive layer 108, so as to fill the second hole 107. Continuing, as shown in fig. 14, removing the fourth conductive layer 111 on the surface, and grinding the second dry film 110 until the second dry film 110 is substantially completely removed; finally, as shown in fig. 15, the remaining second dry film 110 is removed, and the second conductive pillars 112 are obtained.

Specifically, the material of the fourth conductive layer 111 may be the same or different from the material of the third conductive layer 108, both may be copper, of course, both may be different, the second conductive pillars 112 may be prepared based on the fourth conductive material layer 111, and a suitable material of the fourth conductive layer 111 may be selected based on the second conductive pillars, so as to facilitate heat dissipation, and at the same time, the third conductive layer 108 is formed on the core board, a metal circuit may be prepared, and reasonable material arrangement may be performed based on the metal circuit.

As an example, the method for manufacturing a printed wiring board of the present invention further includes the steps of: and opening the core plate 100 for the nth time to form a plurality of nth holes in the core plate, wherein N is greater than or equal to 3, and the first opening to the nth opening are alternately performed on a first face 100a and a second face 100b of the core plate. That is, the core plate 100 may be perforated with a plurality of alternately front and rear surfaces to form the final through holes for heat dissipation, and preferably, the number of times of perforation is selected to be even, so that the front and rear surfaces of the substrate are subjected to the same number of perforation processes. And forming the heat dissipation holes which need to be laid out through a plurality of hole opening processes.

The invention prepares a high-density through hole heat dissipation PCB, and in other comparative examples, various designs are available for solving the heat dissipation problem of the PCB, such as high heat conduction material design, thick copper substrate, metal substrate, dense heat dissipation hole design, embedded copper block design, etc., and the high heat conduction metal copper block or other metal blocks are usually directly embedded in the printed circuit board, thereby solving the heat dissipation problem of the circuit board. However, the process of embedding a high thermal conductivity metal copper block or other metal block into a circuit board has the following drawbacks: in the production process, the high-thermal-conductivity metal copper block or other metal blocks are buried by full manual operation, so that the production efficiency is low, the mass production cannot be realized, and the production cost is high; the binding force between the high-thermal-conductivity metal copper block or other metal blocks and the plate is poor, and the problems of thermal reliability such as layering, bursting and the like easily occur after lamination, so that the rejection rate is high. The invention provides a manufacturing method of a high-density through hole heat dissipation PCB, which can effectively solve the defects by replacing the existing manufacturing method of a buried copper block by a through hole filling mode.

In addition, as shown in fig. 15 and referring to fig. 1-14, the invention further provides an IC package substrate, and in particular relates to a printed circuit board. The printed circuit board is manufactured by adopting the manufacturing method of the IC packaging substrate according to any one of the schemes, and the IC packaging substrate comprises:

A core plate 100 having opposed first and

second faces

100a, 100b;

a plurality of first holes 101 formed in the core plate 100 from the first face 100a;

a plurality of second holes 107 formed in the core plate 100 from the second face 100b;

a first conductive material 106 filled in the first hole 101 and extending at least to the first face 100a;

a second conductive material 113 filled in the second hole 107 and extending at least to the second face 100b;

wherein the first conductive material 106 in the first hole 101 forms a first conductive post 105, the second conductive material 113 in the second hole 107 forms a second conductive post 112, and the first conductive post 105 and the second conductive post 112 are formed in the core 100 for heat dissipation.

As an example, the first conductive material 106 includes a first conductive layer 102 and a second conductive layer 104, it will be understood by those skilled in the art that, of course, the second conductive layer 104 is modified to obtain the first conductive pillars 105, so, in fig. 8, the first conductive material 106 is labeled on the final structure for easy understanding, the first conductive layer 102 is formed at least on the inner wall of the first hole 101 and the surface of the first surface 100a around the first hole, and the second conductive layer 104 is filled in the first hole 101; and/or the second conductive material 113 includes a third conductive layer 108 and a fourth conductive layer 111, where fig. 15 shows that the third conductive layer 108 is formed at least on the inner wall of the second hole 107 and the surface of the second face 100b around the second hole, and the fourth conductive layer 111 is filled in the second hole 107 as described in fig. 8.

As an example, the first hole 101 and the second hole 107 are formed through the core 100, the first conductive layer 102 is formed on the surfaces of the first surface 100a and the second surface 100b at the same time, the third conductive layer 108 is formed on the first conductive layer 102 on the surfaces of the first surface 100a and the second surface 100b, and the first conductive layer 102 and the second conductive layer 108 constitute a wire preparation layer 109 on both sides of the core 100 for preparing metal wire routing.

As an example, the first hole 101 includes a plurality of first hole unit columns, and the second hole 107 includes a plurality of second hole unit columns, where the first hole unit columns and the second hole unit columns are alternately arranged at intervals, and the second holes in the second hole unit columns are correspondingly located between adjacent first holes in adjacent first hole unit columns.

In summary, according to the IC package substrate and the method for manufacturing the IC package substrate, heat dissipation of the printed circuit board is realized through the high-density through holes, and the conventional method for manufacturing the buried copper block is replaced by a through hole filling mode, so that the heat dissipation structure and the circuit layer can be manufactured, the heat dissipation effect of the circuit board is improved, the stability of the structure is improved, the manufacturing process is simplified, the process efficiency is improved, and the method is suitable for batch production. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. The manufacturing method of the IC packaging substrate is characterized by comprising the following steps of:

providing a core plate having opposed first and second faces;

after the first holes are filled with the first conductive material, carrying out second opening on the core plate from the second surface so as to form a plurality of second holes in the core plate, wherein the first holes and the second holes are spaced, and both the first holes and the second holes penetrate through the core plate;

the first conductive material in the first hole forms a first conductive column, and the first conductive material on the inner wall of the first hole and the first surface around the first hole is used as a first conductive layer; the second conductive material in the second hole forms a second conductive post, the second conductive material on the second surface around the inner wall of the second hole and the second hole is used as a second conductive layer, and the first conductive post and the second conductive post are formed in the core plate to dissipate heat.

2. The method of manufacturing an IC package substrate according to claim 1, wherein the step of filling the first hole with the first conductive material includes:

forming a first dry film exposing the first hole on at least the first face;

forming a second dry film exposing the second hole on at least the second face;

3. The method of manufacturing an IC package substrate according to claim 2, wherein the first conductive layer is formed on the surfaces of the first face and the second face at the same time, the third conductive layer is formed on the first conductive layer on the surfaces of the first face and the second face, and the first conductive layer and the second conductive layer constitute a wiring preparation layer located on both sides of the core board.

4. The method of manufacturing an IC package substrate according to claim 3, wherein the first conductive layer and the third conductive layer are flash plated; the first thickness is approximately the same as the second thickness.

5. The method of manufacturing an IC package substrate according to claim 2, wherein a plurality of first windows are formed in the first dry film, the first windows correspondingly expose the first holes, and a distance between the first windows and edges of the first holes is between 20 μm and 200 μm; and/or a plurality of second windows are formed in the second dry film, the second windows correspondingly expose the second holes, and the distance between the second windows and the edges of the second holes is 20-200 mu m.

6. The method of manufacturing an IC package substrate according to claim 2, wherein the second conductive layer is formed by a pulse plating process so that a surface of the second conductive layer is not higher than a surface of the first dry film; and/or the second conductive layer adopts a pulse electroplating process, so that the surface of the fourth conductive layer is not higher than the surface of the second dry film.

7. The method of manufacturing an IC package substrate according to claim 2, further comprising a step of removing the dry film after forming the second conductive layer in the first hole, so as to obtain the first conductive pillar flush with the surface of the first conductive layer; and/or, the step of removing the second dry film after forming the fourth conductive layer in the second hole is further included, so as to obtain the second conductive post which is flush with the surface of the third conductive layer.

8. The method of manufacturing an IC package substrate according to claim 1, further comprising the steps of: and carrying out an nth opening on the core plate to form a plurality of nth holes in the core plate, wherein N is more than or equal to 3, and the first opening to the nth opening are alternately carried out on a first face and a second face of the core plate.

9. The method according to any one of claims 1 to 8, wherein the first hole includes a plurality of columns of first hole unit columns, the second hole includes a plurality of columns of second hole unit columns, the first hole unit columns and the second hole unit columns are alternately arranged at intervals, and the second holes in the second hole unit columns are correspondingly located between adjacent first holes in adjacent first hole unit columns.

10. An IC package substrate manufactured by the method for manufacturing an IC package substrate according to any one of claims 1 to 9, characterized in that the IC package substrate comprises:

a core plate having opposed first and second faces;

a plurality of first holes formed in the core plate from the first face;

a plurality of second holes formed in the core plate from the second face;

the first hole and the second hole penetrate through the core board, the first conductive material in the first hole forms a first conductive column, the first conductive material on the first surface around the inner wall of the first hole and the first hole is used as a first conductive layer, the second conductive material in the second hole forms a second conductive column, the second conductive material on the second surface around the inner wall of the second hole and the second hole is used as a second conductive layer, and the first conductive column and the second conductive column are formed in the core board to dissipate heat.

11. The IC package substrate of claim 10, wherein the first conductive material comprises a first conductive layer and a second conductive layer, the first conductive layer being formed at least on the first hole inner wall and the first face surface around the first hole, the second conductive layer being filled in the first hole; and/or the second conductive material comprises a third conductive layer and a fourth conductive layer, wherein the third conductive layer is at least formed on the inner wall of the second hole and the second surface around the second hole, and the fourth conductive layer is filled in the second hole.

12. The IC package substrate of claim 11, wherein the first conductive layer is formed on both surfaces of the first and second sides, and the third conductive layer is formed on the first conductive layer on both surfaces of the first and second sides, the first and second conductive layers constituting a circuit preparation layer on both sides of the core board.

13. The IC package substrate of any one of claims 10-12, wherein the first hole comprises a plurality of columns of first hole cell columns and the second hole comprises a plurality of columns of second hole cell columns, wherein the first hole cell columns and the second hole cell columns are alternately arranged at intervals, and the second holes in the second hole cell columns are correspondingly positioned between adjacent first holes in adjacent first hole cell columns.