CN112816850B - Aging test system and method convenient for real-time monitoring and integrated circuit chip - Google Patents
Aging test system and method convenient for real-time monitoring and integrated circuit chip Download PDFInfo
- Publication number
- CN112816850B CN112816850B CN202011587956.8A CN202011587956A CN112816850B CN 112816850 B CN112816850 B CN 112816850B CN 202011587956 A CN202011587956 A CN 202011587956A CN 112816850 B CN112816850 B CN 112816850B
- Authority
- CN
- China
- Prior art keywords
- test
- pwm signal
- integrated circuit
- circuit chip
- aging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 254
- 230000032683 aging Effects 0.000 title claims abstract description 74
- 238000012544 monitoring process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 title claims description 8
- 230000002431 foraging effect Effects 0.000 claims abstract description 4
- 230000001360 synchronised effect Effects 0.000 claims abstract description 4
- 230000007958 sleep Effects 0.000 claims description 16
- 230000002159 abnormal effect Effects 0.000 claims description 12
- 238000010998 test method Methods 0.000 claims description 5
- 230000006870 function Effects 0.000 description 28
- 238000010586 diagram Methods 0.000 description 9
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000005059 dormancy Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Environmental & Geological Engineering (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The application discloses an integrated circuit chip convenient for monitoring an aging test result in real time, which comprises a timer, a controller and a control program running on the controller; the integrated circuit chip is used for aging test, and is characterized in that: the controller controls the timer to output a first PWM signal representing a burn-in test item and a second PWM signal synchronized with the first PWM signal and representing test data based on the operation of the control program; the control program is defined to output the first PWM signal having different frequencies based on different burn-in test items.
Description
Technical Field
The present invention relates to integrated circuit testing, and more particularly to integrated circuit burn-in testing.
Background
The aging test item is a process for simulating the corresponding condition strengthening experiment of various factors related to the product under the actual use condition on the aging condition of the product, and common aging mainly comprises high and low temperature aging, illumination aging, moist heat circulation, hot air aging and the like. The integrated circuit aging test items generally include flash memory erasing and reading test, clock switching test, reset test, dormancy awakening test, power failure restart test and the like.
For example, the automatic aging test device for the integrated circuit chip provided by patent No. CN105319494A, the test result of the chip does not need to be output to the tester for verification, the aging test program in the memory module automatically completes verification, a large amount of external communication time is saved, and real-time verification can be achieved, so that the time cost is saved and the whole test process can be monitored. The flicker frequency of the state display lamp indicates different test results, the state of the chip in the aging process is monitored in real time, and the test results are clear at a glance.
However, the above-described conventional technique has failed to solve the problem that, when the test items are plural, the specific test items currently being performed at that time cannot be determined from the test results, and thus the test results of the respective test items cannot be determined in real time.
Disclosure of Invention
In view of the foregoing, in one aspect, the present invention provides an integrated circuit chip for facilitating real-time monitoring of a result of a burn-in test, including a timer, a controller, and a control program running on the controller; the integrated circuit chip is used for burn-in test, wherein the controller controls the timer to output a first PWM signal representing a burn-in test item and a second PWM signal synchronized with the first PWM signal and representing test data based on the operation of the control program;
the control program is defined to output the first PWM signal having different frequencies based on different burn-in test items.
Advantageously, the control program is defined as: each of the test items corresponds to a first PWM signal of one frequency.
Advantageously, the aging test item includes a flash memory read-write function test or a clock switching function test or a sleep wake-up function test or a reset function test or a power-down restart function test.
Advantageously, the integrated circuit chip is an MCU or a DSP or MPU.
On the other hand, the invention also provides an aging test method convenient for real-time monitoring, which comprises the following steps: initializing an integrated circuit chip controller, defining a control program running in the controller according to the requirement of an aging test item, and controlling a timer to output a first PWM signal and a second PWM signal, wherein the first PWM signal corresponds to different frequencies under different aging test items, and the second PWM signal synchronously outputs data of various aging tests; installing an aging test device on the integrated circuit chip which is defined by the control program; selecting the aging test items and the sequence on an aging test device, and starting testing; observing the frequency of the displayed first PWM signal waveform to determine an ongoing test item; and observing the synchronously output second PWM signal, reading out the test data value, and judging whether the test of the chip is abnormal.
Advantageously, the control program is defined as: each of the test items corresponds to a first PWM signal of one frequency.
Advantageously, the aging test item includes at least one of a flash memory read-write function test, a clock switching function test, a sleep wakeup function test, a reset function test and a power failure restart function test.
In another aspect, the present invention further provides an aging test system convenient for real-time monitoring, including: the integrated circuit chip of claim 1 to be burn-in tested; and an aging test device for aging testing the integrated circuit chip, the aging test device including a chip mounting unit for connecting with the integrated circuit chip pins; the display unit is used for displaying the output signal waveform of the integrated circuit chip; the aging test system also comprises a setting unit used for selecting the aging test items and the sequence to be performed according to the requirements.
Advantageously, the system includes a plurality of integrated circuit chips, wherein the definition of the control program and the setting of the test items in each integrated circuit chip are independent of each other, and a plurality of sets of the first PWM and second PWM signal waveforms corresponding to the plurality of integrated circuit chips are displayed on the display unit.
Advantageously, the test environment of the burn-in test is a high and low temperature burn-in test or a light burn-in test or a damp and hot cycle test or a hot air burn-in test.
The aging test system or method or the integrated circuit chip for aging test provided by the embodiment has the beneficial effects that the frequency corresponding to each test item on the first PWM signal is different through software definition, so that the test of which the chip is positioned can be easily determined in real time according to the waveform of the first PWM signal, and the test result of each test is obtained by combining the waveform data of the synchronously output second PWM signal, thereby clearly knowing which test is abnormal. In addition, the software defined mode also makes the structure simpler.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a block diagram of an aging test system convenient for real-time monitoring according to an embodiment of the present invention;
FIG. 2 is a block diagram of an integrated circuit chip that facilitates real-time monitoring of burn-in test results in accordance with an embodiment of the present invention;
FIG. 3 is a waveform diagram of an aging test that facilitates real-time monitoring according to an embodiment of the present invention;
fig. 4 is a flowchart of an aging testing method convenient for real-time monitoring according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In the description of the present application, unless explicitly stated or limited otherwise, the terms "first", "second", and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; the term "plurality" means two or more unless specified or indicated otherwise; the terms "connected," "mounted," and the like are to be construed broadly and include, for example, fixed or removable connections or integral or electrical connections; may be directly connected or indirectly connected through an intermediate. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Example one
As shown in fig. 1, the aging test system for real-time monitoring is provided in this embodiment. The burn-in test system includes an integrated circuit chip to be subjected to a burn-in test, as shown in fig. 2, which is a structure diagram of the integrated circuit chip in this embodiment. The chip comprises a controller, a timer and a self-defined control program (hereinafter referred to as the control program) running on the controller, wherein the controller controls the timer to output PWM (Pulse width modulation) signals based on the running of the self-defined control program, the control program is defined to control a first channel and a second channel of the timer to respectively output a first PWM signal and a second PWM signal based on an aging test item, and the first PWM signals correspond to different frequencies under different aging test items, and the second PWM signals synchronously output data of various aging tests. The system also comprises an aging test device, wherein the aging test device comprises a chip mounting unit which is used for mounting the integrated circuit chip and is in communication connection with the pins of the integrated circuit chip; the aging test device also comprises a display unit for displaying the waveform of the output signal of the integrated circuit chip or the self parameter information of the aging test device; the aging test device also comprises a setting unit used for selecting aging test items and sequences to be carried out according to requirements.
Specifically, one embodiment of the implementation principle of the aging test system is that the items to be subjected to the aging test sequentially are flash memory read-write, clock switching, and sleep wake-up test. The above control program is defined as: during the flash memory read-write test, the first PWM signal outputs a first frequency f1 waveform; during the clock switching function test, the first PWM signal outputs a second frequency f2 waveform at the time; during the sleep wake-up function test, the first PWM signal outputs a third frequency f3 waveform; in addition, the first PWM signal is not output at intervals of each test or during the start or end of all tests. In synchronization with the above-described timing, the second PWM signal outputs test data for each test.
The waveform diagrams of the first PWM signal and the second PWM signal are both displayed on the display unit of the burn-in test apparatus, as shown in fig. 2, which is a waveform diagram of the chip burn-in test in this embodiment.
Therefore, as can be seen from the waveform diagram, after the flash memory erasing and writing, clock switching, sleep wakeup test items are sequentially selected by the setting unit and the test is started, when the first PWM signal with the frequency of f1 appears on the display unit, it can be determined that the flash memory erasing and writing test period is in the present time, and the second PWM signal output synchronously is the test data of the flash memory erasing and writing test, and whether the erasing and writing function of the chip is abnormal is determined according to the test data value. The method for judging the occurrence of the abnormality may be: the width of the PWM signal (frequency determination) exceeds the standard range (equivalent to the value of the test data exceeding the standard range, the standard range for each test being different) or a waveform interruption occurs during the test (equivalent to no data output). When the first PWM signal with the frequency f2 appears on the display unit, it can be determined that the display unit is in the clock switching function test period, and the second PWM signal output synchronously is the test data of the clock switching function test, and it is determined whether the clock switching function of the chip is abnormal according to the test data. When the first PWM signal with the frequency f3 appears on the display unit, it can be determined that the display unit is in the sleep/wake-up function test period, and the second PWM signal output synchronously is the test data of the sleep/wake-up function test, and whether the sleep/wake-up function of the chip is abnormal is determined according to the test data. When the first PWM signal is no longer present on the display unit, it can be determined that the burn-in test has stopped operating.
Alternatively, it may be defined that the first PWM signal is outputted at a plurality of frequencies for a period of one test item, for example, a designated frequency combination different from other test items.
Alternatively, the aging test environment may be a high and low temperature aging test, or a light aging test, or a wet and heat cycle test, or a hot air aging test.
Optionally, the test items may also be a reset test and a power-down restart test.
Alternatively, one or more integrated circuit chips may be used to perform the burn-in test. If the number of the chips is multiple, items to be tested of each chip are mutually independent, the definitions of the control programs are mutually independent (namely, the test items among the chips and the corresponding relations between the test items and the frequencies of the first PWM signals can be the same or different), the setting unit of the aging test device can independently set the test items and the sequence of each chip, and a plurality of groups of waveforms of the first PWM signals and the second PWM signals corresponding to the chips are displayed on the display unit, so that the test results of each chip can be read according to the waveform diagrams of the corresponding groups.
The present embodiment also provides an integrated circuit chip including a controller, a timer, and a control program as described above running on the controller.
Alternatively, the integrated circuit chip may be an MCU (micro controller Unit), a DSP (Digital Signal Processing), or an MPU (micro processor Unit).
The aging test system or the integrated circuit chip provided by the embodiment has the beneficial effects that through software definition, the frequency corresponding to each test item on the first PWM signal is different, so that the test of each test item can be easily determined in real time according to the waveform of the first PWM signal, and the test result of each test item is obtained by combining the waveform data of the second PWM signal output synchronously, so that the test of which test item is abnormal can be clearly known. In addition, the software defined mode also makes the structure simpler.
Example two
As shown in fig. 3, a flowchart of an aging test method convenient for real-time monitoring is provided in this embodiment. The aging test method comprises the following steps:
and step S1, initializing the MCU, defining a control program of the integrated circuit chip according to the aging test items to be performed, and operating the program on a controller of the integrated circuit chip to control a first channel and a second channel of the timer to output a first PWM signal and a second PWM signal respectively, wherein the first PWM signals correspond to different frequencies under different aging test items, and the second PWM signals synchronously output data of each aging test item.
And step S2 of mounting the integrated circuit chip defined by the control program on a chip mounting unit of the burn-in test apparatus.
In step S3, the burn-in test items and sequence to be performed are selected on the burn-in test apparatus, and the test is started.
Step S4, observing the first PWM signal waveform displayed on the display unit, determines the test item being performed.
And step S5, observing the second PWM signal of the corresponding stage of synchronous output, reading out the test data value, and judging whether the test of the chip is abnormal according to the test data value.
Specifically, one embodiment of the above flow is that the items to be subjected to the aging test are flash memory read/write, clock switching, and sleep wake-up test.
In step S1, the control program is defined as: during the flash memory read-write test, the first PWM signal outputs a first frequency f1 waveform; during the clock switching function test, the first PWM signal outputs a second frequency f2 waveform at the time; during the sleep wakeup function test, the first PWM signal outputs a waveform with a third frequency f 3; in addition, the first PWM signal is not output at intervals of each test or during the start or end of all tests. In synchronization with the above-described timing, the second PWM signal outputs test data for each test.
In step S2, the integrated circuit chip subjected to the above-described step S1 is mounted on the chip mounting unit of the burn-in apparatus, and the pins of the integrated circuit chip are brought into communication with the chip mounting unit.
In step S3, a flash erase/write test, a clock switching test, and a sleep wakeup test are sequentially selected from the setting unit of the aging test apparatus, and then the test is started.
In steps S4 and S5, when the first PWM signal with frequency f1 appears on the display unit, it can be determined that the flash memory is in the flash memory erasing/writing test period, and the second PWM signal output synchronously is the test data of the flash memory erasing/writing test, and it is determined whether the erasing/writing function of the chip is abnormal according to the test data value. The method for judging the occurrence of the abnormality may be: the width of the PWM signal (frequency determination) exceeds the standard range (equivalent to the value of the test data exceeding the standard range, the standard range for each test being different) or a waveform interruption occurs during the test (equivalent to no data output). When the first PWM signal with the frequency f2 appears on the display unit, it can be determined that the display unit is in the clock switching function test period, and the second PWM signal output synchronously is the test data of the clock switching function test, and it is determined whether the clock switching function of the chip is abnormal according to the test data. When the first PWM signal with the frequency f3 appears on the display unit, it can be determined that the display unit is in the sleep/wake-up function test period, and the second PWM signal output synchronously is the test data of the sleep/wake-up function test, and whether the sleep/wake-up function of the chip is abnormal is determined according to the test data. When the first PWM signal is no longer present on the display unit, it can be determined that the burn-in test has stopped operating.
Alternatively, it is also possible to define that the first PWM signal is outputted at a plurality of frequencies for one test item period, for example, a designated combination of frequencies different from other test items.
Alternatively, the aging test environment may be a high and low temperature aging test, or a light aging test, or a wet and heat cycle test, or a hot air aging test.
Optionally, the test items may also be a reset test and a power-down restart test.
Alternatively, one or more integrated circuit chips may be used to perform the burn-in test. If the number of the chips is multiple, items to be tested of each chip are mutually independent, the definitions of the control programs are mutually independent (namely, the test items among the chips and the corresponding relations between the test items and the frequencies of the first PWM signals can be the same or different), the setting unit of the aging test device can independently set the test items and the sequence of each chip, and a plurality of groups of waveforms of the first PWM signals and the second PWM signals corresponding to the chips are displayed on the display unit, so that the test results of each chip can be read according to the waveform diagrams of the corresponding groups.
Alternatively, the integrated circuit chip may be an MCU (micro controller Unit), a DSP (Digital Signal Processing), or an MPU (micro processor Unit).
The aging test method provided by the embodiment has the beneficial effects that through software definition, the frequencies corresponding to each test item on the first PWM signal are different, so that the test result of each test can be easily obtained by determining which test the chip is in according to the waveform of the first PWM signal in real time and combining with the waveform data of the second PWM signal synchronously output, and the abnormal test can be clearly known. In addition, the software defined mode also makes the structure simpler.
The above description is only for the preferred embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (8)
1. An integrated circuit chip comprises a timer, a controller and a control program running on the controller; the integrated circuit chip is used for aging test, and is characterized in that:
the controller controls the timer to output a first PWM signal representing a burn-in test item and a second PWM signal synchronized with the first PWM signal and representing test data based on the operation of the control program;
the control program is defined to output the first PWM signal having different frequencies based on different burn-in test items;
the control program is defined as: each test item corresponds to a first PWM signal with one frequency;
the first PWM signal is used for determining a test item in which the integrated circuit chip is positioned, and the second PWM signal is used for representing a test result of the test item in which the integrated circuit chip is positioned.
2. The integrated circuit chip of claim 1, wherein the burn-in test items comprise at least one of a flash read-write function test, a clock switching function test, a sleep wake-up function test, a reset function test, and a power-down restart function test.
3. An integrated circuit chip according to claim 1 or 2, wherein the integrated circuit chip is an MCU or a DSP or MPU.
4. A aging test method convenient for real-time monitoring is characterized by comprising the following steps:
initializing an integrated circuit chip controller, defining a control program running in the controller according to the requirements of aging test items to control a timer to output a first PWM signal and a second PWM signal, wherein the first PWM signal corresponds to different frequencies under different aging test items, and the second PWM signal synchronously outputs data of each aging test item;
installing an aging test device on the integrated circuit chip which is defined by the control program;
selecting the aging test items and the sequence on an aging test device, and starting testing;
observing the frequency of the displayed first PWM signal waveform, and determining an ongoing test item;
observing the second PWM signal which is synchronously output, reading out a test data value, and judging whether the test of the chip is abnormal;
the control program is defined as: each of the test items corresponds to a first PWM signal with one frequency;
the first PWM signal is used for determining a test item in which the integrated circuit chip is positioned, and the second PWM signal is used for representing a test result of the test item in which the integrated circuit chip is positioned.
5. The method of claim 4, wherein the burn-in test items comprise a flash read-write function test or a clock switching function test or a sleep wake-up function test or a reset function test or a power-down restart function test.
6. An aging test system convenient for real-time monitoring, comprising:
an integrated circuit chip as claimed in claim 1 or 2 to be subjected to burn-in testing; and
the aging test device is used for performing aging test on the integrated circuit chip and comprises a chip mounting unit which is used for being connected with pins of the integrated circuit chip; the display unit is used for displaying the output signal waveform of the integrated circuit chip; the aging test system also comprises a setting unit used for selecting the aging test items and the sequence to be performed according to the requirements.
7. The system of claim 6, comprising a plurality of integrated circuit chips, wherein the definition of the control program and the setting of the test items in each integrated circuit chip are independent of each other, and wherein a plurality of sets of the first PWM and second PWM signal waveforms corresponding to the plurality of integrated circuit chips are displayed on the display unit.
8. The system of claim 6, wherein the test environment of the burn-in test is a high and low temperature burn-in test or a light burn-in test or a thermal-humid cycle test or a hot air burn-in test.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011587956.8A CN112816850B (en) | 2020-12-29 | 2020-12-29 | Aging test system and method convenient for real-time monitoring and integrated circuit chip |
| CN202210320882.4A CN114839505B (en) | 2020-12-29 | 2020-12-29 | Aging test device for MCU chip and integrated circuit chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011587956.8A CN112816850B (en) | 2020-12-29 | 2020-12-29 | Aging test system and method convenient for real-time monitoring and integrated circuit chip |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210320882.4A Division CN114839505B (en) | 2020-12-29 | 2020-12-29 | Aging test device for MCU chip and integrated circuit chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112816850A CN112816850A (en) | 2021-05-18 |
| CN112816850B true CN112816850B (en) | 2022-06-17 |
Family
ID=75855298
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011587956.8A Active CN112816850B (en) | 2020-12-29 | 2020-12-29 | Aging test system and method convenient for real-time monitoring and integrated circuit chip |
| CN202210320882.4A Active CN114839505B (en) | 2020-12-29 | 2020-12-29 | Aging test device for MCU chip and integrated circuit chip |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210320882.4A Active CN114839505B (en) | 2020-12-29 | 2020-12-29 | Aging test device for MCU chip and integrated circuit chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN112816850B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113325766B (en) * | 2021-05-26 | 2023-05-30 | 珠海格力电器股份有限公司 | Drive control chip and heating ventilation equipment |
| CN117368688A (en) * | 2023-09-22 | 2024-01-09 | 北京信诺达泰思特科技股份有限公司 | Aging detection system and method for radio frequency chip |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105319494A (en) * | 2014-11-26 | 2016-02-10 | 北京同方微电子有限公司 | Automatic aging testing device of integrated circuit chip |
| CN107271879A (en) * | 2017-05-31 | 2017-10-20 | 上海华力微电子有限公司 | Semiconductor chip ageing tester and method |
| CN108519548A (en) * | 2018-03-21 | 2018-09-11 | 杭州可靠性仪器厂 | Aging of integrated circuit experimental rig |
| CN108828432A (en) * | 2018-06-08 | 2018-11-16 | 湖州慧能机电科技有限公司 | A kind of high-power chip ageing tester |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001344999A (en) * | 2000-05-31 | 2001-12-14 | Seiko Epson Corp | Semiconductor device |
| JP4889961B2 (en) * | 2005-05-06 | 2012-03-07 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit and burn-in test method thereof |
| CN102721886A (en) * | 2012-06-28 | 2012-10-10 | 惠州市德赛西威汽车电子有限公司 | Aging test device of motormeter |
| CN110716126A (en) * | 2019-10-14 | 2020-01-21 | 珠海亿智电子科技有限公司 | Chip aging test system, method and device |
-
2020
- 2020-12-29 CN CN202011587956.8A patent/CN112816850B/en active Active
- 2020-12-29 CN CN202210320882.4A patent/CN114839505B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105319494A (en) * | 2014-11-26 | 2016-02-10 | 北京同方微电子有限公司 | Automatic aging testing device of integrated circuit chip |
| CN107271879A (en) * | 2017-05-31 | 2017-10-20 | 上海华力微电子有限公司 | Semiconductor chip ageing tester and method |
| CN108519548A (en) * | 2018-03-21 | 2018-09-11 | 杭州可靠性仪器厂 | Aging of integrated circuit experimental rig |
| CN108828432A (en) * | 2018-06-08 | 2018-11-16 | 湖州慧能机电科技有限公司 | A kind of high-power chip ageing tester |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114839505A (en) | 2022-08-02 |
| CN112816850A (en) | 2021-05-18 |
| CN114839505B (en) | 2023-09-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112816850B (en) | Aging test system and method convenient for real-time monitoring and integrated circuit chip | |
| CN101901178A (en) | Computer system on-off test device and method | |
| CN107015891B (en) | Information processing method and test chip | |
| CN112198865B (en) | Testing method, device and system for MCU low-power mode switching | |
| US20120131385A1 (en) | Testing mehtod for unit under test | |
| CN1971528A (en) | Automated computer on-off operation testing device and method | |
| CN103914361B (en) | Detection jig and detection method of computer device | |
| TW201349845A (en) | Testing method and testing apparatus for TV system | |
| CN108168731A (en) | Detection device, method and test tool | |
| CN115184759A (en) | Frequency/temperature characteristic test method and system for identifying excitatory hopping of crystal oscillator | |
| CN112986805B (en) | Intelligent VPX board card testing method and system | |
| JPS63274885A (en) | Method of testing semiconductor integrated circuit during burn-in and circuit substrate | |
| CN115078968B (en) | Chip test circuit, self-test chip and chip test system | |
| TWI399550B (en) | Testing system and method | |
| CN113125938B (en) | Aging test monitoring method and system | |
| CN114964809B (en) | Vehicle instrument testing method and device and storage medium | |
| CN110927477B (en) | Non-intrusive load identification detection method and system | |
| CN104459562A (en) | Startup and shutdown testing device | |
| CN115662488A (en) | SSD reliability test method and system | |
| CN112285550B (en) | Switch power-off detection method and device, computer equipment and readable storage medium | |
| CN114355266A (en) | Health monitoring management system of ATE (automatic test equipment) and control method thereof | |
| JP4156105B2 (en) | IC test equipment | |
| CN117110735A (en) | High-temperature reverse bias aging test method and system | |
| CN111239510A (en) | Self-service test method and test system for EMC of air conditioner | |
| US20020007479A1 (en) | LSI testing apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |