CN112803947B - Method and device for establishing complex clock tree in high-speed analog-to-digital converter - Google Patents
Method and device for establishing complex clock tree in high-speed analog-to-digital converter Download PDFInfo
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Abstract
The invention discloses a method for establishing a complex clock tree in a high-speed analog-to-digital converter, which comprises the following steps: establishing a delay circuit; dividing the output of the delay circuit into a plurality of single-point outputs, wherein the delay time of each single-point output is adjusted through the output vcont of the charge pump, so that a plurality of rising edges and falling edges with different times are obtained; the complex clock tree is implemented by passing the input clock clk in, the output clock clk out, and the rising and falling edges of all single-point output clocks through single-phase clock logic. The invention logically combines 50 percent of output clock obtained by the duty ratio adjusting circuit with clean input clock and different edge time obtained by decomposing the delay circuit to obtain the required correct clock tree, ensures that the obtained clock has small change along with PVT, can meet the control required by the normal working operation of the high-speed ADC and has reliable work.
Description
Technical Field
The present invention relates to a method for establishing a complex clock number, and more particularly, to a method and an apparatus for establishing a complex clock tree in a high-speed analog-to-digital converter.
Background
In a high-speed ADC, some clocks are needed to control the whole operation process of the ADC, and the control clocks are desirably clocks that are not affected by PVT. In the conventional method, an external input clock is usually passed through a duty cycle standby circuit to obtain a 50% output clock, and then a series of logic combination changes are performed with the input clock to obtain a corresponding clock tree, which cannot solve the establishment of a complex clock tree, and the clock tree obtained in this way varies greatly with PVT, so that it is difficult to ensure that under various environmental changes, the obtained clocks do not overlap, and slightly, the obtained clock tree can break the operation process of the whole high-speed ADC, resulting in logic confusion.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a method for establishing a complex clock tree in a high-speed analog-to-digital converter with reliable operation, and provides an apparatus for establishing a complex clock tree in a high-speed analog-to-digital converter.
The technical scheme for solving the problems is as follows: a method for establishing a complex clock tree in a high-speed analog-to-digital converter comprises the following steps:
the method comprises the following steps: establishing a delay circuit;
step two: dividing the output of the delay circuit into a plurality of parts, wherein the delay of each part is output through a single point, the delay time of each single point output is adjusted through the output vcont of the charge pump, and the output of the charge pump is matched and locked with the delay time of the corresponding single point output, so that a plurality of rising edges and falling edges with different times are obtained;
step three; the complex clock tree is implemented by passing the input clock clk in, the output clock clk out, and the rising and falling edges of all single-point output clocks through single-phase clock logic.
In the second step, the delay circuit includes a plurality of first inverters connected in series in sequence, an output end of each first inverter passes through one second inverter and then is used as a single-point output, and the single-point output of the delay circuit includes a, b, c, d, e, f, g, h and i.
The method for establishing the complex clock tree in the high-speed analog-to-digital converter comprises the following specific steps:
3-1) setting 6 clock control lines, wherein phi is a sampling clock control line, clk _ rst is an erasing memory clock control line, phi1e is a sampling process access common mode level clock control line, phi22 is a reference voltage access clock control line, phi2 is a comparison amplification clock control line, and clk _ amp is an access residual error amplification clock control line;
3-2) setting the working timing cycle of the complex clock tree to be 5ns, wherein the phi cycle is 1.6ns, the clk _ rst cycle is 375ps, the phi1e cycle is 2ns, the phi22 cycle is 430ps, the phi2 cycle is 2.5ns, and the clk _ amp cycle is 2.1 ns;
3-3) defining the timing relationship between 6 clock control lines, phi1e falling 60ps before the phi falling edge comes, clk _ rst and phi not overlapping, phi22 and phi not overlapping, phi22 and clk _ amp not overlapping;
3-4) triggering the falling edge of phi1e by using the rising edge of clk _ in, shaping by using a-point output delay waveform of a delay circuit through a two-stage inverter to obtain phi2, and triggering the rising edge of phi1e by using the falling edge of phi 2;
3-5) triggering the rising edge of the clk _ rst by using the falling edge of phi2, and triggering the falling edge of the clk _ rst by using the c point output rising edge of the delay circuit;
3-6) triggering the rising edge of phi by utilizing the falling edge of clk _ rst, and triggering the falling edge of phi through the falling edge of phi1e after the falling edge is delayed by an inverter;
3-7) triggering the phi22 rising edge by using the phi falling edge, and triggering the phi22 falling edge by using the b point output rising edge of the delay circuit;
3-8) using phi22 falling edge to trigger the rising edge of clk _ amp, and outputting the rising edge through a point a of the delay circuit to trigger the falling edge of clk _ amp;
3-9) clock signals are all generated.
A device for establishing a complex clock tree in a high-speed analog-to-digital converter comprises a duty ratio adjusting circuit and a clock tree logic circuit, wherein the duty ratio adjusting circuit comprises a phase error integrator, a delay circuit, a narrow pulse generator and a D trigger, the phase error integrator comprises a phase detector and a charge pump, an original clock clk _ in is connected with the input end of the D trigger and the input end of the phase detector, the output end of the D trigger is connected with the input end of the delay circuit, the output end of the delay circuit generates an output clock clk _ out and is connected with the input end of the narrow pulse generator and the input end of the phase detector, the output end of the narrow pulse generator is connected with the D trigger, and the output end of the phase detector is connected with the delay circuit after passing through the charge pump;
the clock tree logic circuit comprises a sampling clock control circuit used for triggering phi rising edges and falling edges, a memory elimination clock control circuit used for triggering clk _ rst rising edges and falling edges, a sampling process access common mode level clock control circuit used for triggering phi1e rising edges and falling edges, a reference voltage access clock control circuit used for triggering phi22 rising edges and falling edges, a comparison amplification clock control circuit used for triggering phi2 rising edges and falling edges, and an access residual difference amplification clock control circuit used for triggering clk _ amp rising edges and falling edges;
the D flip-flop triggers an input original clock clk _ in to generate an output clock clk _ out, the output pulse width of clk _ out is adjusted by changing a delay circuit delay line, the magnitude of delay is controlled by a delay signal vcont, the vcont is generated by a phase error integrator, in the phase error integrator, a phase detector senses the phase difference between rising edges of clk _ in and clk _ out and generates corresponding up and down signals to drive a charge pump and a low-pass filter, so that control delay signals vcont with different magnitudes are generated to control the output clock clk _ out with the duty ratio of 50%, and delay signals a, b, c, D, e, f, g, h, i and the original clock clk _ in and the output clock clk _ out output from the delay circuit are combined through different logics in a clock tree logic circuit to obtain a required clock tree.
The invention has the beneficial effects that: the invention logically combines 50 percent of output clock obtained by the duty ratio adjusting circuit with clean input clock and different edge time obtained by decomposing the delay circuit to obtain the required correct clock tree, ensures that the obtained clock has small change along with PVT, can meet the control required by the normal working operation of the high-speed ADC and has reliable work.
Drawings
Fig. 1 is a circuit diagram of a duty cycle adjusting circuit according to the present invention.
Fig. 2 is a circuit diagram of the delay circuit of fig. 1.
Fig. 3 is a timing diagram for constructing a clock tree.
Fig. 4 is a circuit diagram of a sampling process access common mode level clock control circuit.
FIG. 5 is a circuit diagram of an erase memory clock control circuit.
FIG. 6 is a graph of simulation results of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings and examples.
As shown in fig. 1, an apparatus for building a complex clock tree in a high-speed analog-to-digital converter includes a duty ratio adjusting circuit and a clock tree logic circuit, where the duty ratio adjusting circuit includes a phase error integrator, a delay circuit delay _ line, a narrow pulse generator pulse _ gen, and a D flip-flop DFF, the phase error integrator includes a phase detector PD and a charge pump CP, an original clock clk _ in is connected to an input end of the D flip-flop and an input end of the phase detector, an output end of the D flip-flop is connected to an input end of the delay circuit, an output end of the delay circuit generates an output clock clk _ out and is connected to an input end of the narrow pulse generator and an input end of the phase detector, an output end of the narrow pulse generator is connected to the D flip-flop, and an output end of the phase detector is connected to the delay circuit after passing through the charge pump;
the clock tree logic circuit comprises a sampling clock control circuit used for triggering phi rising edges and falling edges, a memory elimination clock control circuit used for triggering clk _ rst rising edges and falling edges, a sampling process access common mode level clock control circuit used for triggering phi1e rising edges and falling edges, a reference voltage access clock control circuit used for triggering phi22 rising edges and falling edges, a comparison amplification clock control circuit used for triggering phi2 rising edges and falling edges, and an access residual difference amplification clock control circuit used for triggering clk _ amp rising edges and falling edges;
the D flip-flop triggers an input original clock clk _ in to generate an output clock clk _ out, the output pulse width of the clk _ out is adjusted by changing a delay circuit, the magnitude of the delay is controlled by a delay signal vcont, the vcont is generated by a phase error integrator, in the phase error integrator, a phase detector senses the phase difference between rising edges of clk _ in and clk _ out and generates corresponding upper and lower signals to drive a charge pump and a low-pass filter, so that control delay signals vcont with different magnitudes are generated, the output clock clk _ out with the duty ratio of 50% is controlled, and delay signals a, b, c, D, e, f, g, h, i output from the delay circuit and the original clock clk _ in and the output clock clk _ out are combined through different logics in a clock tree logic circuit to obtain a required clock tree.
The whole working process of the device is established as follows: when an input clock clk _ in enters a D flip-flop, due to the low level of a D terminal, when a rising edge of the clk _ in comes, a point A outputs a low level, clk _ out is obtained through a certain delay, when a falling edge of the clk _ out comes, a narrow pulse generator is triggered to output a narrow pulse, the output end A of the D flip-flop is set to be a high level, the time of the whole high-low level of the point A determines an A pulse, and the output clk _ out is obtained through the delay of the A pulse. The delay time of the delay circuit needs to be determined by a delay circuit for a long time, the delay time of the delay circuit needs to be adjusted by converting the pulse width of an output clock and the phase difference between an original input clock clk _ in into an output voltage vcont through a charge pump, the output clock clk _ out outputs 50% of duty ratio through a repeated superposition adjustment process, and through the series of processes, delay signals a, b, c, d, e, f, g, h, i which are mutually restricted and matched with the delay time and clk _ out which does not change along with PVT are obtained. The required complex clock tree is then implemented by passing the original clock clk in, the output clock clk out and the delay signals a, b, c, d, e, f, g, h, i through simple TSPC logic.
A method for establishing a complex clock tree in a high-speed analog-to-digital converter comprises the following steps:
the method comprises the following steps: a delay circuit is established.
Step two: the output of the delay circuit is divided into a plurality of parts, the delay of each part is output through a single point, the delay time of each single point output is adjusted through the output vcont of the charge pump, the output of the charge pump is matched and locked with the delay time of the corresponding single point output, the delay times are also very matched under the condition of PVT change, and the delay times of all the parts are determined and identical, so that a plurality of rising edges and falling edges at different times are obtained.
As shown in fig. 2, the delay circuit includes a plurality of first inverters connected in series in sequence, an output end of each first inverter passes through one second inverter and then is used as a single-point output, and the single-point output of the delay circuit includes a, b, c, d, e, f, g, h, and i.
Step three; a complex clock tree is implemented by passing the input clock clk in, the output clock clk out, and the rising and falling edges of all single-point output clocks through single-phase clock logic.
The building up of the complex clock tree used in the 14-bit 200M high-speed pipeline adc is achieved below by the clock signals derived above. The clock tree timing relationship to be realized is shown in fig. 3, which is a working timing process of a first stage in a 14-bit 200M high-speed pipeline adc, and the complex clock tree is established by the following steps:
3-1) setting 6 clock control lines, wherein phi is a sampling clock control line, clk _ rst is an erasing memory clock control line, phi1e is a common mode level clock control line accessed in the sampling process, phi22 is a reference voltage access clock control line, phi2 is a comparison amplification clock control line, and clk _ amp is an access residual difference amplification clock control line.
3-2) setting the working timing cycle of the complex clock tree to be 5ns, wherein the phi cycle is 1.6ns, the clk _ rst cycle is 375ps, the phi1e cycle is 2ns, the phi22 cycle is 430ps, the phi2 cycle is 2.5ns, and the clk _ amp cycle is 2.1 ns.
3-3) define the timing relationship between 6 clock control lines, phi1e falls 60ps before the phi falling edge comes, which is important in the overall timing and to ensure that phi1e falling edge is very clean; clk _ rst and phi do not overlap, phi22 and phi do not overlap, and phi22 and clk _ amp do not overlap; it is guaranteed that each clock cannot go wrong in sequence and time.
3-4) from the timing diagram, it can be seen that phi1e falling edge is most important, requiring the cleanest clock to trigger, however, all available trigger clocks are cleanest input clocks clk _ in, so the rising edge of clk _ in is used to trigger the falling edge of phi1 e; through the single-point waveforms of the output delay circuit, the time from the rising edge of an input clock clk _ in to the falling edge of a point a can be obtained, the time required by phi1e can be obtained, and the output delay time of the point a is obtained and just accords with phi2, so that phi2 can be obtained by directly shaping the output delay waveform of the point a through a two-stage inverter, and the falling edge of phi2 can trigger the rising edge of phi1 e;
the sampling process switches in the common mode level clocking circuit as shown in figure 4. In fig. 4, MP2, MP3, MN2, and MN4 constitute a single-phase clock control logic (TSPC), which has a simple logic structure, good stability, and high speed, and when phi2buf is at a high level, the gate of MP2 is turned on at a low level, the drain is at a high level, and the gate of MP3 is turned off at a high level. When phi2buf falling edge comes, MP2 is turned off, MP3 is turned on, and at the moment MP2 is turned off, MP3 is turned on to pull phi1e high, and the same logic is used for triggering phi1e falling edge.
3-5) the rising edge of clk _ rst clock and the rising edge of phi1e start at the same time as observed from the timing diagram, then the falling edge of phi2 can be used to trigger the rising edge of clk _ rst as well, and the c point of the delay circuit is used to output the rising edge to trigger the falling edge of clk _ rst;
the erase memory clock control circuit is shown in FIG. 5. The triggering of the clk _ rst falling edge may be triggered by the output rising edge of the single point c, and the time may be matched to the required clock time by micro-modulating the delay circuit.
3-6) by observing the timing waveforms of FIG. 3, it can be known that phi can be triggered to determine by the clock signals clk _ rst and phi1e, the rising edge of phi is triggered by the falling edge of clk _ rst, and the falling edge of phi is triggered by the falling edge of phi1e after the inverter is delayed; it should be noted here that the falling edge of phi starts to fall after 60ps after phi1e falls, so that the falling edge of phi1e needs to be triggered after the inverter delay.
3-7) the falling edge of phi is used for triggering the rising edge of phi22, and because the pulse width length of phi22 is about 430ps, the falling edge of phi22 is triggered by the rising edge output by the b point of the delay circuit according to the delay time obtained by the delay circuit.
3-8) the rising edge of clk _ amp starts again after the falling edge of phi22, so the rising edge of clk _ amp is triggered by the falling edge of phi22, and the falling edge of clk _ amp is triggered by the rising edge output at point a of the delay circuit.
3-9) clock signals are all generated.
The sampling clock control circuit, the reference voltage access clock control circuit, the comparison amplification clock control circuit and the access residual difference amplification clock control circuit can be realized in a similar mode of accessing the common mode level clock control circuit in the sampling process, and the core point is to determine respective trigger points by utilizing the time from the rising edge of clk _ in to each single-point output and the sequence of time sequence.
The simulation result of the clock tree obtained by the invention is shown in FIG. 6, and the simulation is performed under the environment of the combination of ff, ss and typical process angles and the temperature-404080125 respectively based on the voltage of 1.5V. From the simulation, it can be seen that the most important phi1e falling edge is very clean and has little variation with the process angle, and has already fallen 68ps before the phi falling edge, the rising edges of clk _ rst and phi1e act substantially simultaneously, and the rising edges of clk _ rst and phi do not overlap, and the falling edge of phi, the rising edge of phi22 also has very little variation with the process angle and do not overlap. The Phi2 rising edge has little change with the process angle, Phi2 also starts to pull up after Phi22 pulls up by about 300ps, and clk _ amp also starts to pull up after Phi2 rising edge reaches 380ps, and the falling edge also pulls down before Phi2 falling edge reaches, according to the original design rule. Generally speaking, all clock control signals can meet the timing requirement, so that the establishment of the clock tree can completely meet the control effect of the high-speed ADC under various environments.
From the principle analysis and simulation results, the invention completely overcomes the performance and effect which can not be achieved by the traditional establishment of the clock tree, the clock tree established by the traditional mode can only be suitable for the establishment of the simple clock tree, and the clock tree established by the invention is easy to cause logic confusion and overlap along with the change of PVT (virtual reality) variation, and the regulation space is very limited. The clock tree building method of the invention overcomes the defects, can easily build a complex clock tree, well solves the influence caused by PVT, avoids logic confusion, and ensures that the adjusting space is very large.
Claims (2)
1. A method for establishing a complex clock tree in a high-speed analog-to-digital converter is characterized by comprising the following steps:
the method comprises the following steps: establishing a delay circuit;
step two: dividing the output of the delay circuit into a plurality of parts, wherein the delay of each part is output through a single point, the delay time of each single point is adjusted through the output vcont of the charge pump, and the output of the charge pump is matched and locked with the delay time of the corresponding single point output, so that a plurality of rising edges and falling edges with different times are obtained;
the delay circuit comprises a plurality of first phase inverters which are sequentially connected in series, the output end of each first phase inverter passes through one second phase inverter and then is used as a single-point output, and the single-point output of the delay circuit comprises a, b, c, d, e, f, g, h and i;
step three; implementing a complex clock tree by passing the input clock clk _ in, the output clock clk _ out, and the rising and falling edges of all single-point output clocks through single-phase clock logic;
the third specific process comprises the following steps:
3-1) 6 clock control lines are arranged, wherein phi is a sampling clock control line, clk _ rst is an erasing memory clock control line, phi1e is a sampling process access common mode level clock control line, phi22 is a reference voltage access clock control line, phi2 is a comparison amplification clock control line, and clk _ amp is an access residual difference amplification clock control line;
3-2) setting the working timing cycle of the complex clock tree to be 5ns, wherein the phi cycle is 1.6ns, the clk _ rst cycle is 375ps, the phi1e cycle is 2ns, the phi22 cycle is 430ps, the phi2 cycle is 2.5ns, and the clk _ amp cycle is 2.1 ns;
3-3) defining the timing relationship between 6 clock control lines, phi1e falling 60ps before the phi falling edge comes, clk _ rst and phi not overlapping, phi22 and phi not overlapping, phi22 and clk _ amp not overlapping;
3-4) triggering the falling edge of phi1e by using the rising edge of clk _ in, shaping by using a-point output delay waveform of a delay circuit through a two-stage inverter to obtain phi2, and triggering the rising edge of phi1e by using the falling edge of phi 2;
3-5) triggering the rising edge of the clk _ rst by using the falling edge of phi2, and triggering the falling edge of the clk _ rst by using the c point output rising edge of the delay circuit;
3-6) triggering the rising edge of phi by utilizing the falling edge of clk _ rst, and triggering the falling edge of phi after the falling edge of phi1e is delayed by an inverter;
3-7) triggering the rising edge of phi22 by using the falling edge of phi, and triggering the falling edge of phi22 by using the b point output rising edge of the delay circuit;
3-8) using phi22 falling edge to trigger the rising edge of clk _ amp, and outputting the rising edge through a point a of the delay circuit to trigger the falling edge of clk _ amp;
3-9) clock signals are all generated.
2. An apparatus for building a complex clock tree in a high-speed analog-to-digital converter for implementing the building method of claim 1, characterized in that: the pulse width modulation circuit comprises a duty ratio adjusting circuit and a clock tree logic circuit, wherein the duty ratio adjusting circuit comprises a phase error integrator, a delay circuit, a narrow pulse generator and a D trigger, the phase error integrator comprises a phase detector and a charge pump, an original clock clk _ in is connected with the input end of the D trigger and the input end of the phase detector, the output end of the D trigger is connected with the input end of the delay circuit, the output end of the delay circuit generates an output clock clk _ out and is connected with the input end of the narrow pulse generator and the input end of the phase detector, the output end of the narrow pulse generator is connected with the D trigger, and the output end of the phase detector is connected with the delay circuit after passing through the charge pump;
the clock tree logic circuit comprises a sampling clock control circuit used for triggering phi rising edges and falling edges, a memory elimination clock control circuit used for triggering clk _ rst rising edges and falling edges, a sampling process access common mode level clock control circuit used for triggering phi1e rising edges and falling edges, a reference voltage access clock control circuit used for triggering phi22 rising edges and falling edges, a comparison amplification clock control circuit used for triggering phi2 rising edges and falling edges, and an access residual difference amplification clock control circuit used for triggering clk _ amp rising edges and falling edges; phi is a sampling clock control line, clk _ rst is an erasing memory clock control line, phi1e is a common mode level clock control line accessed in the sampling process, phi22 is a reference voltage access clock control line, phi2 is a comparison amplification clock control line, and clk _ amp is an access residual difference amplification clock control line;
the D flip-flop triggers an input original clock clk _ in to generate an output clock clk _ out, the output pulse width of clk _ out is adjusted by changing a delay circuit delay line, the magnitude of delay is controlled by a delay signal vcont, the vcont is generated by a phase error integrator, in the phase error integrator, a phase detector senses the phase difference between rising edges of clk _ in and clk _ out and generates corresponding up and down signals to drive a charge pump and a low-pass filter, so that control delay signals vcont with different magnitudes are generated to control the output clock clk _ out with the duty ratio of 50%, and delay signals a, b, c, D, e, f, g, h, i and the original clock clk _ in and the output clock clk _ out output from the delay circuit are combined through different logics in a clock tree logic circuit to obtain a required clock tree.
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