CN214042145U

CN214042145U - Temperature sensing unit switch clock circuit capable of eliminating mismatch influence

Info

Publication number: CN214042145U
Application number: CN202021871263.7U
Authority: CN
Inventors: 高垒; 李文昌; 洪婷; 乔立刚; 赵正超
Original assignee: Shandong Huake Semiconductor Research Institute Co ltd
Current assignee: Shandong Huake Semiconductor Research Institute Co ltd
Priority date: 2020-08-31
Filing date: 2020-08-31
Publication date: 2021-08-24
Anticipated expiration: 2030-08-31

Abstract

Eliminate temperature sensing unit switch clock circuit that mismatch influences relates to the integrated circuit technology, the utility model discloses a set of current mirror, current source switching circuit, triode group and the output unit that form side by N current sources, first control unit has N output, is connected with N current mirror input selector's control end one-to-one, triode input selector and triode output selector's control end all are connected to the second control unit, N is for being greater than the integer of 7; the first control unit comprises a trigger level width control module which is used for outputting a square wave signal with pulse width a to each output end of the first control unit; the second control unit comprises a periodic square wave generating circuit with 50% duty ratio; the periodic square wave generation circuit is characterized by comprising a square wave period setting circuit, wherein the square wave period setting circuit is used for setting a period value b of a periodic square wave, and b is a. The utility model discloses reduction mismatch degree that can be very big.

Description

Temperature sensing unit switch clock circuit capable of eliminating mismatch influence

Technical Field

The utility model relates to an integrated circuit technique.

Background

In the temperature sensing circuit generating delta VBE circuit, a DEM technology and a chopping technology can be adopted to eliminate the influence caused by mismatch of a current mirror and mismatch of pnp. As shown in fig. 1. The principle is that the DEM clock CKD <15:0>/CKDN <15:0> and the chopping clock CKC/CKCN are independent from each other or have no specific design relationship (wherein the phase difference between CKD <15:0> and CKDN <15:0> is 180 degrees, and the phase difference between CKC and CKCN is 180 degrees), for example, the clock period of CKD <15:0>/CKDN <15:0> is 16T, and the high level time is T. While the clock period of CKC/CKCN is 2T.

After the DEM technology and the chopping technology are used, although the purposes of reducing the mismatch error of the current mirror and the mismatch error of the PNP can be achieved, if a related clock circuit is unreasonably arranged, the best effect cannot be achieved.

If the chopping clock period is set to be too small, the chopping is too frequent, and adverse effects such as clock feed-through and power consumption increase are brought; if the chopping clock period is set to be too large, only one PNP tube can flow into the DEM starting time of each current mirror, and if the PNP tube is seriously mismatched, the final chopping effect is greatly reduced.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that a temperature sensing circuit and temperature sensing circuit control method of the mismatch of elimination galvanometer mirror and PNP pipe that can be better is provided.

The utility model provides a technical scheme that technical problem adopted is, eliminate temperature sensing unit switch clock circuit that mismatch influence, include by the current mirror group, current source switching circuit, triode group and the output unit that N current sources formed side by side, current source switching circuit includes N current mirror input selector switch and two triode input selector switches that parallel, and every current source is connected to the current source input selector switch who corresponds with it; the two current source output selection switches are in one-to-one correspondence connection with two triodes in the triode group, and are also connected with an output unit, wherein the output unit comprises two triode output selection switches; the first control unit is provided with N output ends which are correspondingly connected with the control ends of the N current mirror input selection switches one by one, the control ends of the triode input selection switch and the triode output selection switch are both connected to the second control unit, and N is an integer greater than 7;

the first control unit comprises a trigger level width control module which is used for outputting a square wave signal with pulse width a to each output end of the first control unit;

the second control unit comprises a periodic square wave generating circuit with 50% duty ratio;

the periodic square wave generation circuit is characterized by comprising a square wave period setting circuit, wherein the square wave period setting circuit is used for setting a period value b of a periodic square wave, and b is a.

The beneficial effects of the utility model are that, when current mirror or temperature sensing triode produce the mismatch because technology manufacturing reason, can be through above-mentioned circuit structure and control method, very big reduction mismatch degree.

Drawings

Fig. 1 is a schematic diagram of a temperature sensing circuit Δ VBE.

Fig. 2 is a schematic diagram of a temperature sensing circuit Δ VBE for increasing the mismatch amount.

Fig. 3 is a comparison diagram of the switching control pulse of the present invention.

Fig. 4 is a clock generation circuit diagram.

Fig. 5 is a waveform diagram of simulation 1.

Fig. 6 is a waveform diagram of simulation 2.

Fig. 7 is a waveform diagram of simulation 3.

Fig. 8 is a circuit diagram of a sampling circuit of an ADC.

Detailed Description

Referring to fig. 1 and 3, taking 16 sets of current mirrors as an example, 1 current mirror is sequentially extracted as an IC, the other 15 current mirrors are extracted as 15 × IC, mismatch errors of the current mirrors are eliminated, and two temperature sensing triodes QL and QR are switched by an alternate clock.

The circuit of the utility model comprises a current mirror group formed by N current sources in parallel, a current source switching circuit, a triode group and an output unit, wherein the current source switching circuit comprises N current mirror input selector switches in parallel and two triode input selector switches, and each current source is connected to the current source input selector switch corresponding to the current source input selector switch; the two triode input selection switches are in one-to-one correspondence connection with two triodes in the triode group, and are also connected with an output unit, wherein the output unit comprises two triode output selection switches; the first control unit is provided with N output ends which are correspondingly connected with the control ends of the N current mirror input selection switches one by one, and output signals of the first control unit are CKD and CKDN; the control ends of the triode input selection switch and the triode output selection switch are connected to a second control unit, output signals of the second control unit are CKC and CKCN, and N is an integer greater than 7;

the periodic square wave generating circuit comprises a square wave period setting circuit for setting a period value b of the periodic square wave, wherein b is a.

The square wave period setting circuit can adopt any one of the following two modes:

1) the square wave period setting circuit comprises a pulse width detection unit and a square wave period control unit connected with the pulse width detection unit, wherein the pulse width detection unit is connected with each output end of the first control unit so as to detect the output pulse width of the first control unit, and the square wave period control unit controls the length of a square wave period;

2) the square wave period setting circuit is a square wave period control circuit, and a period length corresponding to the output pulse width of the first control unit is fixed.

The utility model discloses in, CKD CKDN and CKC CKCN all adopt OSC as the clock source, and the OSC cycle is T, behind 2 frequency divisions, and the clock for sampling circuit is 2T, and each way output waveform of sampling circuit, the control signal that also is the current source input selector switch is the CKD of fig. 1 and fig. 2.

CKDN is the inverse of CKD and CKCN is the inverse of CKC.

According to the later stage ADC structure, in each large sampling period, there should be 15 Δ VBE + VBE, which is 16 sampling + holding periods, where Δ VBE period of each sampling is T, and holding is T, and then each large sampling period time is: 16 × (T + T) ═ 32T.

When one DEM conversion is completed in 32T and the designed DEM has 16 paths, each high level time of the DEM is 32T/16-2T.

And the PNP chopping clock has a period of 2T, so as to ensure that each DEM current flows into the PNP tubes on the left side and the right side, and the PNP chopping clock does not exceed the high-level time of the DEM.

Therefore, the key point of the present invention is to set the DEM clock high level time length to be 2T, and set the chopping clock period (CKC/CKCN) to be 2T, the two time lengths are equal, and the triggering edge (e.g. rising edge) of CKD and the rising edge of CKC occur simultaneously.

In addition, the period of the chopping clock CKC/CKCN is set to be 2T, and the chopping clock can be further matched with the sampling clock of the ADC sampling circuit, so that the influence caused by pnp mismatch is reduced. As shown in fig. 8, Δ VBE is the output voltage of fig. 2, CKE/CKEN is a clock signal with a period of 2T and a duty cycle of 50%, Cs1/Cs2 is a sampling capacitor, CI1/CI2 is an integrating capacitor, VCM is a common-mode input voltage, and the core is a differential input differential output amplifier.

Suppose QL in fig. 2 is connected in series with a parasitic resistance, which brings about a voltage of Δ Vos. In the first 50% of the first cycle, the Δ VBE _ p output voltage is Δ VBE _ p + Δ Vos, the Δ VBE _ m output voltage is Δ VBE _ m, the charge sampled at Cs1 is (VCM- Δ VBE _ p- Δ Vos) Cs1, and the charge sampled at Cs2 is (VCM- Δ VBE _ m) Cs 2. At the later 50% of the first cycle, CKC/CKCN switches, and the mismatch voltage Δ Vos of QL is switched to Δ VBE _ m output. The Δ VBE _ p output voltage is Δ VBE _ p, and the Δ VBE _ m output voltage is Δ VBE _ m + Δ Vos. Simultaneously, the clock of CKE/CKEN is switched, the charge sampled at Cs1 is (VCM-delta VBE _ p) Cs1, and the charge sampled at Cs2 is (VCM-delta VBE _ m-delta Vos) Cs 2.

Thus, throughout the cycle, Cs1 samples the charge as:

q1 ═ Cs1+ (VCM- Δ VBE _ p) · Cs1 ═ Cs1 (2VCM-2 Δ VBE _ p- Δ Vos); cs2 samples the charge as: q2 ═ Cs2+ (VCM- Δ VBE _ m- Δ Vos) · Cs2 ═ Cs2 (2VCM-2VBE _ m- Δ Vos).

By design Cs 1-Cs 2, the differential input charge is: Q2-Q1 ═ (2 Δ VBE _ p-2VBE _ m) Cs1

From the final expression, it can be seen that when the chopping clock is set to have the same period as the sampling clock of 2T, the PNP mismatch can be eliminated.

FIG. 4 is a schematic diagram of a circuit for generating a DEM clock CKD <15:0>/CKDN <15:0> and a Chopping clock CKC/CKCN, wherein the period of the input clock CLK is 2T, 16D flip-flops are passed, and the final DEM clock is a waveform with a period of 32T and a high level of 2T, and the high level is sequentially transmitted from CKD <0> to CKD <15>, and then the cycle is performed.

The specific principle is as follows: when the first CLK clock arrives, CKD <15:0> -CKDN <15:0> -0, the RS flip-flop outputs Q-1, when the rising edge of the first CLK arrives, CKD <0> -1, CKDN <0> -0. CKDN <15> immediately becomes 1, causing the RS flip-flop output Q to flip to 0.

After the rising edge of the second CLK clock arrives, the output CKD <1> -1 and CKDN <1> -0 of the second stage D flip-flop, and the input of the first stage D flip-flop is changed to 0, so the output CKD <0> -0 and CKDN <0> -1, that is, CKD <0> maintains a high level for one period of 2T.

After the rising edge of the third CLK clock arrives, similarly, the output CKD <2> of the third stage D flip-flop is 1, CKDN <2> is 0, and the input of the second stage D flip-flop is changed to 0, so the output CKD <1> is 0, CKDN <1> is 1, and CKD <1> maintains a high level for one period of 2T.

Until the rising edge of the 16 th CLK clock comes, the 16 th D flip-flop outputs CKD <15> is 1 and CKDN <15> is 0, so that the RS flip-flop outputs Q is 1.

The situation that the rising edge of the 17 th CLK clock comes and the rising edge of the 1 st CLK clock comes is repeated, so far, the circuit realizes the shift register function with the cycle of 16CLK (16X 2T) 32T and the high level of 1CLK (2T). The cycle of the Chopping clock CKC/CKCN is the same as the cycle of CLK, and the cycle is 2T.

Fig. 3 is a schematic diagram of the chopping clock and DEM clock of Δ VBE, it can be seen that the high level of the DEM clock CKD is 2T, when CKD is high level, the current sources of sample and hold are unchanged and both come from the same current source, and at the same time, the chopping clock of pnp is switched, so as to further eliminate pnp mismatch.

Simulation verification:

the reason for the mismatch between the current mirror and the PNP transistor is that there is uncertainty in every process step in the manufacturing of the integrated circuit, resulting in limited mismatch for nominally identical devices. To verify whether the mismatch suppression function is effective or not through simulation, the mismatch amount needs to be artificially increased for comparison simulation. The mismatch amount setting is shown in fig. 2:

all I1 and I2 are deviated to 125% of the standard value, and the rest I3-I16 are still standard currents; the parasitic resistance R _ QL of the PNP tube QL is increased to 27 Ω.

First, the determination criterion is that the simulated mismatch amount is 0, i.e., I1-I2- … -I16 are the same. When R _ QL is equal to 0, the CKD period is 16T, the high levels are sequentially 2T, and the CKC/CKCN period is 2T, which is denoted as simulation 1, see fig. 5.

Next, the simulation mismatch amount is shown in fig. 6, and the clock period is not changed, i.e. CKD period is 16T, high level is 2T in sequence, and CKC/CKCN period is 2T, which is marked as simulation 2.

Finally, the simulation mismatch amount is shown in fig. 7, and the CKC period changes, that is, the CKD period is 16T, the high levels are sequentially 2T, and the CKC/CKCN period is 4T, which is marked as simulation 3.

The glitch in the figure is due to the clock switch, and the DC amount needs to be taken into account. Fig. 6 shows the two-terminal output waveform of simulation 2. Fig. 7 is a graph showing the output waveform of simulation 3. The high or low of the waveform is difficult to be visually seen. Therefore, a calculator is used for taking an average value of a period of time, and the difference value of the two values is observed for judgment.

From the above table, it can be seen that the final output of emulation 2 is closer to emulation 1, and the difference of emulation 2 and emulation 3 is just in the cycle setting of CKC, and emulation 2 does the utility model discloses the cycle number that sets up, and emulation 3 is other circumstances, can prove from this the utility model's advantage.

The specification and the drawings of the present invention clearly illustrate the necessary technical content, and the ordinary skilled person can implement the present invention according to the specification, so that the detailed description of the specific circuit structure is omitted.

Claims

1. The temperature sensing unit switch clock circuit for eliminating mismatch influence comprises a current mirror group formed by N current sources in parallel, a current source switching circuit, a triode group and an output unit, wherein the current source switching circuit comprises N current mirror input selection switches in parallel and two triode input selection switches, and each current source is connected to the current source input selection switch corresponding to the current source input selection switch; the two triode input selection switches are in one-to-one correspondence connection with two triodes in the triode group, and are also connected with an output unit, wherein the output unit comprises two triode output selection switches; the first control unit is provided with N output ends which are correspondingly connected with the control ends of the N current mirror input selection switches one by one, the control ends of the triode input selection switch and the triode output selection switch are both connected to the second control unit, and N is an integer greater than 7;

2. The temperature sensing unit switch clock circuit for eliminating mismatch influence according to claim 1, wherein the square wave period setting circuit comprises a pulse width detection unit and a square wave period control unit connected thereto, the pulse width detection unit is connected to the first control unit for detecting the output pulse width of the first control unit, and the square wave period control unit controls the length of the square wave period according to the width.