CN101102112A

CN101102112A - Clock control method of high-speed pipe line A/D converter and its lock storage clock generator

Info

Publication number: CN101102112A
Application number: CNA200610028617XA
Authority: CN
Inventors: 金信煦; 张永寿
Original assignee: Shanghai LG Electronics Co Ltd
Current assignee: Shanghai LG Electronics Co Ltd
Priority date: 2006-07-05
Filing date: 2006-07-05
Publication date: 2008-01-09

Abstract

The invention is concerned with the clock controlling method of the high speed tube line A/D converter and the lock up clock creator. The method includes: Inputting the analog signal and enlarging it in the preamplifier; Turning on the flip-latch by using the additional clock; Keying the digital code into the MDAC through the special clock excesses the delay clock; enlarging the signal difference of the MDAC signal and the input analog signal formerly. The lock up clock creator uses the clock signal of the preamplifier and the output signal is obtained by making the clock signal passes through the falling edge as the each input signals of the NAND gate, and it controls the clock that provides the high speed tube line of the lock-up clock. The invention can insure the plenary of the clock time spare within the high operating speed tube line A/D converter.

Description

The clock control method of high speed pipeline A/D converter and latch clock maker thereof

Technical field

The clock control that the present invention relates to the clock control method of high speed pipeline A/D converter and pipeline A/D converter is with latching (latch) clock generator { Timing Controlling Method at High-SpeedPipel ined A/D Converters and Latch Clock Generator for High-Speedpipelined A/D Converters}.In detail, the present invention relates to the latch clock maker of following clock control method and use thereof: in the pipeline A/D converter that runs up, can guarantee sufficient clock vacant (margin), make run up very useful, and, can prevent the unnecessary power consumption of simulated assembly etc., realize the low-power running of pipeline A/D converter.

Background technology

Recently, CD (Compact Disk) and DVD optical disc storage and the develop rapidlys of playback equipment production technology such as (Digital Versatile Disk), and also in the high speed information treatment facility, it is diversified that the speed type of A/D converter also becomes.For high-speed a/d converter, though the A/D converter of full flicker (Full Flash) form is arranged, but its video picture degree (Resolution) is restricted, and structurally will consume a large amount of electric weight, so be difficult to reach the high video picture degree of the low-power effect under the state of running up.Therefore, pipeline (Pipeline) A/D converter that can realize high video picture degree and high speed effect simultaneously just is used to a lot of applications.Even so, still for the pipeline A/D converter, when embodying the high speed effect, in the clock of hope, must handle simulation (Analog) signal, so must consume big volume and electricity, clock (Timing) also is restricted, so bring a lot of difficulties for embodiment high speed effect.

The pipeline A/D converter of existing representative configuration as shown in Figure 1.Comprise SHA (sample-and-hold: sampling and hold amplifier) 11 and the multistage change-over circuit that is in series 12 that is electrically connected with the output of SHA, and the numeric error correction logic circuit (Digital Error Correction Logic, DCL) 13 that are electrically connected with the output of multistage change-over circuit 12.

The analog signal of each end input is the input signal of m-position (m-bit) flicker A/D converter and multiplication analog converter (hereinafter to be referred as MDAC:Multiplying Digital to Analog Converter).

Fig. 2 is the structural representation that constitutes each change-over circuit of original pipeline A/D converter.Each change-over circuit 12 comprises a flicker A/D converter 121 and a MDAC121.Flicker A/D converter 121 is made of preamplifier 1211, latch 1212 and encoder 1213 (Encoder).MDAC122 comprises DAC1221 and amplifier 1222.The digital coding (Digital Code) of flicker A/D converter output is transferred to MDAC, makes reference voltage and uses, and MDAC amplifies analog signal and the reference voltage poor (Residue) imported, and is transferred to next stage.The clock flow process that sort signal flows as shown in Figure 3.

The clock that is used to drive the pipeline A/D converter uses the clock signal QO and the QE of non-overlapped two phase clock (Non-OverlappingTwo-Phase Clock) type.As mentioned above, MDAC receives the coding of flicker A/D converter input, and amplifies.Therefore, before MDAC began to amplify, the flicker A/D converter must have power output.Simultaneously, the power output when MDAC amplifies must join in the Tw, can obtain needed video picture degree.Existing A/D converter utilizes the trailing edge (FallingEdge) of QE clock, makes the latch clock of comparator, simultaneously, during Δ T12, digital coding is imported in the MDAC.Simultaneously, according to the difference of analogue data, MDAC must handle analog signal in Tw.Simultaneously, if ADC slowly runs up, the cycle of clock shortens, and thus, Δ T12 is also along with shortening.From the rising edge (Rising Edge) of latch clock, make the latch entry into service that constitutes the flicker A/D converter, the digitally coded output clock Δ TLD in the input MDAC is vacant.In the A/D converter of low-speed running, because Δ T12＞Δ TLD, so to equal Tw just passable for the clock that is provided with of MDAC.But, when running up, just satisfy Δ T12＜Δ TLD, after MDAC begins to amplify because begin receiving digitally encoded, so before obtaining needed voltage, the clock that is provided with of MDAC is limited in below the Tw.Therefore, at a high speed output is set, institute is so that need more power consumption, thereby causes the unnecessary increase and the waste of electric weight.

Summary of the invention

The present invention is the clock control method and the latch clock maker thereof of a kind of high speed pipeline A/D converter of proposing in order to address the above problem, the clock control of pipeline A/D converter of using the clock control method of this high speed pipeline A/D converter and can carrying out clock control with the latch clock maker in the pipeline A/D converter that runs up, can guarantee that sufficient clock is vacant, not only make to run up very usefully, and can prevent the unnecessary power consumption of simulated assembly etc.

To achieve these goals, the clock control method of high speed pipeline A/D converter of the present invention has the feature that comprises following four steps: input analog signal, and the step of amplifying in preamplifier; Utilize additional clock, with the step of latch unlatching; After surpassing the specific clock of delayed clock (TLD), digital coding is imported the step of MDAC; The step that signal difference between the analog signal of the signal of input MDAC and original input is amplified.

In the present invention, preferably allow latch open, the clock signal (QE) that the control preamplifier is amplified and make clock signal pass through output signal that trailing edge (delay-chain) obtained input signal as NAND gate (NANDgate), and the output signal that is obtained controlled as latch signal, at this moment, can comprise the odd number converter circuit in the trailing edge.

Simultaneously, any one input of trailing edge all comprises the NAND gate that electricity connects among the present invention.The clock signal (QE) that the control preamplifier is amplified and make clock signal pass through output signal that trailing edge obtains each input signal as NAND gate provides the clock control latch clock maker of the high speed pipeline of generation latch clock.At this moment, comprise the odd number converter circuit in the trailing edge.

As mentioned above, the present invention utilizes additional latch clock, from the flicker A/D converter output is arranged, and begins to amplify by MADC, can produce the vacant time (Timing Margin).At this moment, though exist many more vacant clocks good more, also should consider the clock that analog input signal is amplified by preamplifier, so be difficult to make it very big.Utilize and regulate vacant time method, if trailing edge uses converter circuit, just can regulate the number of transducer.

If replacement (reset) is not relatively good for the preamplifier of Shi Yonging in the present invention.If replacement is arranged, shiver just bring for the analog signal of input MADC.Simultaneously, must guarantee bandwidth that high speed signal is amplified.

In sum, of the present invention is a very valuable invention, and its effect is: in the pipeline A/D converter that utilizes additional clock to run up, can guarantee that sufficient clock is vacant, not only make to run up very usefully, and can prevent the unnecessary power consumption of simulated assembly etc.

Description of drawings

Concrete characteristic performance of the present invention is further described by following embodiment and accompanying drawing thereof.

Fig. 1 is the formation schematic diagram of original common pipeline A/D converter;

Fig. 2 is each member (stage) structural representation that constitutes original pipeline A/D converter;

Fig. 3 is each the member clock flow chart that constitutes original pipeline A/D converter;

Fig. 4 is each the member clock flow chart that constitutes pipeline A/D converter of the present invention;

Fig. 5 is the circuit diagram of latch clock maker of the present invention.

Fig. 6 constitutes the concrete clock flow chart of each member of pipeline A/D converter of the present invention.

Embodiment

Desirable embodiment to devices and methods therefor of the present invention is elaborated with reference to the accompanying drawings.

Fig. 4 is a clock control method flow chart of the present invention.Here, QL utilizes the circuit of Fig. 5 latch clock maker 5, can generate QE and input.Please cooperate referring to Fig. 5, Fig. 5 is the circuit diagram of latch clock maker of the present invention.The clock control of a kind of high speed pipeline of the present invention latch clock maker, any one input of its trailing edge all comprises the NAND gate T that electricity connects, clock signal (QE) that the control preamplifier is amplified and above-mentioned clock signal are by signal that trailing edge obtained each input signal as NAND gate T, and the generation latch clock.At this moment, comprise the odd number converter circuit in the trailing edge.

Utilize the mode of Fig. 4, in the timing topology of the shown common pipeline A/D converter of Fig. 3, during the latch operation, can know that just the COMP interval has increased.This time that means that just latch brings into operation when the MDAC supplied with digital signal is elongated.Like this, before MDAC begins to amplify, because the digital coding abundance, so can guarantee normal operation.Among the figure: RESET represents " replacement "; COMP represents " comparison "; SAMPLE represents " sampling "; AMPLIF represents " amplitude ".

Clock control signal flow process of the present invention as shown in Figure 6.If utilize QE input analog signal,, open (Turn-on) at the rising edge latch of QL and begin relatively to latch 62 just preamplifier begins to amplify 61.Thus, after delayed clock TLD 63, digital coding is imported into MDAC.Therefore, MDAC just begins to amplify 64 at the rising edge of QO.Here, output signal is arranged,, have sufficient vacant clock (65 or clock vacant) by begin amplification to MDAC from the flicker A/D converter.Though exist many more vacant clocks good more, also should consider the clock that analog input signal is amplified by preamplifier, so be not too greatly then relatively good.

The clock control method of desirable embodiment of the present invention is very useful for the pipeline A/D converter of run up (200MHz is above more satisfactory).For the transducer of low-speed running, there is not the too big worry of trailing edge yet.

As mentioned above, desirable embodiment of the present invention only is for the illustration purpose, is not in order to limit the present invention.Any those skilled in the art without departing from the spirit and scope of the present invention, can do the change or the replacement of various equivalences, so protection scope of the present invention are as the criterion with the scope that appending claims was defined.

Claims

1, a kind of clock control method of A/D converter of high speed pipeline is characterized in that, comprises following four steps: input analog signal, and the step of amplifying in preamplifier; Utilize additional clock, with the step of latch unlatching; After surpassing the specific clock of delayed clock, digital coding is imported the step of multiplication analog-converted; The step that signal difference between the analog signal of the signal of input multiplication analog-converted and original input is amplified.

2, clock control method as claimed in claim 1, it is characterized in that: allow latch open, the clock signal that the control preamplifier is amplified and make clock signal pass through output signal that trailing edge obtains input signal as NAND gate, and the output signal that is obtained is controlled as latch signal.

3, clock control method as claimed in claim 2 is characterized in that: can comprise the odd number converter circuit in the trailing edge.

4, clock control method as claimed in claim 1 is characterized in that: employed preamplifier is not reset.

5, a kind of clock control of high speed pipeline latch clock maker, it is characterized in that: any one input of trailing edge all comprises the NAND gate that electricity connects, clock signal that the control preamplifier is amplified and above-mentioned clock signal be by signal that trailing edge obtained each input signal as NAND gate, and generate latch clock.

6, latch clock maker as claimed in claim 5, it is characterized in that: trailing edge comprises the odd number converter circuit.