CN112803373A - Power semiconductor device protection circuit, control method, storage medium, and apparatus - Google Patents

Power semiconductor device protection circuit, control method, storage medium, and apparatus Download PDF

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Publication number
CN112803373A
CN112803373A CN202011474538.8A CN202011474538A CN112803373A CN 112803373 A CN112803373 A CN 112803373A CN 202011474538 A CN202011474538 A CN 202011474538A CN 112803373 A CN112803373 A CN 112803373A
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semiconductor device
power semiconductor
module
circuit
turn
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CN112803373B (en
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曾宏
潘学军
刘敏安
陈彦
陈芳林
陈勇民
邹平
沈飞淞
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Zhuzhou CRRC Times Semiconductor Co Ltd
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Zhuzhou CRRC Times Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
    • H02H7/205—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment for controlled semi-conductors which are not included in a specific circuit arrangement

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Protection Of Static Devices (AREA)
  • Power Conversion In General (AREA)

Abstract

The invention discloses a power semiconductor device protection circuit, a control method, a storage medium and equipment. The control module is configured to respond to an instruction for indicating the power semiconductor device to be short-circuited and control the action of the turn-off module to turn off the turn-off circuit, so that the device on the turn-off circuit can be still protected after the power semiconductor device fails or a gate cathode is short-circuited due to external reasons; in addition, the protection module is controlled to act to switch on the protection circuit, so that the gate cathode short circuit is ensured, the pressure bearing capacity and the boosting rate of the power semiconductor device are effectively improved, the protection circuit can be switched on rapidly under the condition that the gate cathode short circuit is caused by external factors, the safety of the whole power semiconductor drive switching-off circuit is protected, and meanwhile, the applicability, the reliability and the repeated applicability of the power semiconductor device are improved.

Description

Power semiconductor device protection circuit, control method, storage medium, and apparatus
Technical Field
The present invention relates to the field of electronic circuit technologies, and in particular, to a power semiconductor device protection circuit, a control method, a storage medium, and a device.
Background
In the prior art, the on-off control of a thyristor is implemented by a gate driving unit matched with the thyristor, for example, the Integrated Gate Commutated Thyristor (IGCT) includes an anode (a), a gate (G) and a cathode (K), when the IGCT is turned off, a cathode current is commutated to the gate and hard turn-off is implemented by a turn-off circuit connected to the gate, as shown in fig. 1, fig. 1 shows a gate turn-off current path diagram of the IGCT, as can be seen from fig. 1, when hard turn-off is implemented, the cathode current completely passes through the turn-off circuit, and therefore, the turn-off circuit needs a plurality of devices connected in parallel, and can be formed by connecting a plurality of turn-off MOSFETs in parallel with a plurality of capacitors.
In order to realize the frequency hard turn-off of the IGCT, the capacity of a capacitor stack of the turn-off circuit can reach dozens of millifarads (mF), when the GCT device fails to be short-circuited or GK short-circuit is caused by external reasons, because the turn-off MOSFET stack is turned on when the IGCT is turned off, a turn-off switch tube signal still exists, and the turn-off capacitor stack can be short-circuited, the short-circuited energy of the capacitor stack can completely pass through the turn-off MOSFET, so that the MOSFET has a risk of failure, and the safety of the whole thyristor driving turn-off circuit is affected, as shown in fig. 2, fig. 2 shows a short-circuit current path diagram when the.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: how to quickly realize the protection of the whole gate drive turn-off circuit under the condition of short circuit of a power semiconductor device gate cathode.
To solve the above technical problems, the present invention provides a power semiconductor device protection circuit, a control method, a storage medium, and an apparatus.
In a first aspect of the present invention, there is provided a power semiconductor device protection circuit comprising: the device comprises a turn-off module, a protection module and a control module;
the control module is connected with the off-terminal module and the protection module, and is configured to control the action of the off-module to disconnect an off-circuit and control the action of the protection module to connect a protection circuit in response to a power semiconductor device short-circuit instruction;
the turn-off module is connected between a gate and a cathode of the power semiconductor device and is configured to open the turn-off circuit in response to a control instruction of the control module;
the protection module is connected between the gate and the cathode of the power semiconductor device, and the protection module is configured to turn on the protection circuit in response to a control command of the control module.
Optionally, the protection module includes:
the first end of the first resistor is connected with the control module;
the grid electrode of the first MOS stack is connected with the second end of the first resistor, the drain electrode of the first MOS stack is connected with the cathode, and the source electrode of the first MOS stack is grounded;
the first end of the second resistor is connected with the control module;
and the grid electrode of the second MOS stack is connected with the second end of the second resistor, the drain electrode of the second MOS stack is connected with the gate electrode, and the source electrode of the second MOS stack is grounded.
Optionally, the shutdown module includes:
a third MOS stack and a capacitor;
the grid electrode of the third MOS stack is connected with the control module, the drain electrode of the third MOS stack is connected with the gate electrode, and the source electrode of the third MOS stack is grounded;
the first end of the capacitor is connected with the cathode, and the second end of the capacitor is grounded.
Optionally, the power semiconductor device protection circuit further includes:
a power module configured to provide a voltage to the capacitance;
a detection module configured to detect voltage signals of the power supply module, the third MOS stack, and the capacitor, respectively, and send a detection signal to the control module based on the voltage signals, so that the control module determines whether the power semiconductor device is short-circuited based on the detection signal.
Optionally, the detection module includes:
the positive input end of the first comparator circuit is connected with the input end of the power supply module, the negative input end of the first comparator circuit is connected with a first reference voltage, the output end of the first comparator circuit is connected with the control module, and when the voltage of the input end of the power supply module is smaller than the first reference voltage, the first comparator circuit outputs a power-down signal;
a positive input end of the second comparator circuit is connected to the first end of the capacitor, a negative input end of the second comparator circuit is connected to a second reference voltage, an output end of the second comparator circuit is connected to the control module, and when the voltage at the first end of the capacitor is smaller than the second reference voltage, the second comparator circuit outputs a voltage abnormal signal;
and a positive input end of the third comparator circuit is connected with the gate of the third MOS stack, a negative input end of the third comparator circuit is connected with a third reference voltage, an output end of the third comparator circuit is connected with the control module, and when the voltage of the input end of the gate is greater than the third reference voltage, the third comparator circuit outputs a high-level signal to indicate that the input end of the gate has a voltage signal.
Optionally, the power semiconductor device includes: an integrated gate commutated thyristor, an emitter turn-off thyristor, a gate commutated thyristor or a gate turn-off thyristor.
In a second aspect of the present invention, there is provided a control method for a power semiconductor device protection circuit, the method being implemented based on the power semiconductor device protection circuit as described above, and including:
and controlling the action of the turn-off module to turn off the turn-off circuit and controlling the action of the protection module to turn on the protection circuit in response to the instruction of the power semiconductor device short circuit.
Optionally, before the controlling the shutdown module to act to turn off the shutdown circuit and the controlling the protection module to act to turn on the protection circuit in response to the instruction of the power semiconductor device short circuit, the method further includes:
receiving detection signals of the power module, the third MOS stack and the capacitor;
judging whether the power semiconductor device is short-circuited or not based on the detection signal;
when the power semiconductor device is in a static off state and a power-down signal of the power module and a voltage abnormal signal of the capacitor are received, judging that the power semiconductor device is in a short circuit; alternatively, the first and second electrodes may be,
and when a high-level signal of the third MOS stack is received, judging that the power semiconductor device is short-circuited.
Optionally, before the controlling the shutdown module to act to turn off the shutdown circuit and the controlling the protection module to act to turn on the protection circuit in response to the instruction of the power semiconductor device short circuit, the method further includes:
receiving detection signals of the power module, the third MOS stack and the capacitor;
judging whether the power semiconductor device is short-circuited or not based on the detection signal;
when the power semiconductor device is in a dynamic turn-off state and a power-down signal of the power module and a voltage abnormal signal of the capacitor are received, judging that the power semiconductor device is in a short circuit; alternatively, the first and second electrodes may be,
and when a high level signal of the third MOS stack is received and the duration of the high level signal is longer than a preset duration, judging that the power semiconductor device is short-circuited.
In a third aspect of the present invention, there is provided a storage medium comprising a computer program stored thereon, the computer program, when executed by a processor, being capable of implementing the control method of the power semiconductor device protection circuit as described above.
In a fourth aspect of the invention, there is provided an apparatus comprising: a memory having stored thereon a computer program which, when executed by the controller, is capable of implementing the method of controlling a power semiconductor device protection circuit as described above.
Compared with the prior art, one or more embodiments in the above scheme can have the following advantages or beneficial effects:
the power semiconductor device protection circuit, the control method, the storage medium and the equipment to which the invention is applied comprise a turn-off module, a protection module and a control module. The control module is configured to respond to an instruction for indicating the power semiconductor device to be short-circuited and control the action of the turn-off module to turn off the turn-off circuit, so that the MOS device on the turn-off circuit can be still protected after GCT fails or GK short circuit is caused by external reasons; in addition, the protection module is controlled to act to switch on the protection circuit, so that the GK short circuit is ensured, the pressure bearing capacity and the boosting rate of the power semiconductor device are effectively improved, the protection circuit can be switched on quickly under the condition that the GK short circuit is caused by external factors, the safety of the whole power semiconductor drive switching-off circuit such as the GCT device and the third MOS stack can be protected, and meanwhile, the applicability, the reliability and the repeated applicability of the power semiconductor device are improved.
Drawings
The scope of the present disclosure may be better understood by reading the following detailed description of exemplary embodiments in conjunction with the accompanying drawings. Wherein the included drawings are:
FIG. 1 shows an IGCT gate-off current path diagram;
FIG. 2 shows a short circuit current path diagram when GK is shorted;
fig. 3 is a schematic structural diagram illustrating a protection circuit of a power semiconductor device according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a power semiconductor device protection circuit provided by an embodiment of the invention;
fig. 5 is a schematic structural diagram of a protection circuit of a power semiconductor device according to another embodiment of the present invention;
fig. 6 is a schematic diagram of a power semiconductor device protection circuit according to another embodiment of the present invention;
fig. 7 is a schematic diagram of a power semiconductor device protection circuit according to another embodiment of the present invention;
fig. 8 is a schematic flow chart illustrating a control method of a protection circuit of a power semiconductor device according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of an apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the following will describe in detail an implementation method of the present invention with reference to the accompanying drawings and embodiments, so that how to apply technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented.
In the prior art, the on-off control of a thyristor is implemented by a gate driving unit matched with the thyristor, for example, the Integrated Gate Commutated Thyristor (IGCT) includes an anode (a), a gate (G) and a cathode (K), when the IGCT is turned off, a cathode current is commutated to the gate and hard turn-off is implemented by a turn-off circuit connected to the gate, as shown in fig. 1, fig. 1 shows a gate turn-off current path diagram of the IGCT, as can be seen from fig. 1, when hard turn-off is implemented, the cathode current completely passes through the turn-off circuit, and therefore, the turn-off circuit needs a plurality of devices connected in parallel, and can be formed by connecting a plurality of turn-off MOSFETs in parallel with a plurality of capacitors.
In order to realize the frequency hard turn-off of the IGCT, the capacity of a capacitor stack of the turn-off circuit can reach dozens of millifarads (mF), when the GCT device fails to be short-circuited or GK short-circuit is caused by external reasons, because the turn-off MOSFET stack is turned on when the IGCT is turned off, a turn-off switch tube signal still exists, and the turn-off capacitor stack can be short-circuited, the short-circuited energy of the capacitor stack can completely pass through the turn-off MOSFET, so that the MOSFET has a risk of failure, and the safety of the whole thyristor driving turn-off circuit is affected, as shown in fig. 2, fig. 2 shows a short-circuit current path diagram when the.
In view of the above, the present application provides a power semiconductor device protection circuit, a control method, a storage medium, and an apparatus, which include a shutdown module 10, a protection module 11, and a control module 12. The control module 12 is configured to control the shutdown module 10 to act to disconnect the shutdown circuit in response to an instruction for indicating a short circuit of the power semiconductor device, so that the MOS device on the shutdown circuit can still be protected after GCT failure or GK short circuit caused by an external reason; in addition, the protection module 11 is also controlled to operate to switch on the protection circuit, so that the GK short circuit is ensured, the pressure bearing capacity and the boosting rate of the power semiconductor device are effectively improved, the protection circuit can be switched on quickly under the condition that the GK short circuit is caused by external factors, the safety of the whole power semiconductor drive switching-off circuit such as the GCT device and the third MOS stack can be protected, and meanwhile, the applicability, the reliability and the repeated applicability of the power semiconductor device are improved.
Example one
Referring to fig. 3, fig. 3 is a schematic structural diagram illustrating a power semiconductor device protection circuit according to an embodiment of the present invention, which includes: a shutdown module 10, a protection module 11 and a control module 12,
the control module 12 is connected with the turn-off module 10 and the protection module 11, and the control module 12 is configured to control the turn-off module 10 to act to turn off the turn-off circuit and control the protection module 11 to act to turn on the protection circuit in response to the instruction of the power semiconductor device short circuit;
the turn-off module 10 is connected between the gate and the cathode of the power semiconductor device, and the turn-off module 10 is configured to open the turn-off circuit in response to a control instruction of the control module 12;
the protection module 11 is connected between the gate and the cathode of the power semiconductor device, and the protection module 11 is configured to turn on the protection circuit in response to a control instruction of the control module 12.
In the embodiment of the present invention, the power semiconductor device may be an integrated gate commutated thyristor, an emitter turn-off thyristor, a gate commutated thyristor, or a gate turn-off thyristor, and in the present application, an Integrated Gate Commutated Thyristor (IGCT) is taken as an example for description, the IGCT is a device in which a gate driving circuit and a gate commutated thyristor GCT are integrated into a whole, the gate driving circuit may be divided into an on circuit and an off circuit, wherein the on circuit may adopt a conventional configuration in the prior art, the off circuit belongs to the turn-off module 10, and as an example, the off circuit may be composed of an NMOS stack and a capacitor; as another example, the shutdown circuit may also be comprised of a PMOS stack and a capacitor. In the following description, a turn-off circuit composed of an NMOS stack and a capacitor will be described as an example.
The protection module 11 includes a first resistor, a first MOS stack, a second resistor, and a second MOS stack, where the first MOS stack and the second MOS stack may be simultaneously selected as an NMOS stack or a PMOS stack, and in the embodiment of the present invention, the NMOS stack is taken as an example for description, specifically refer to fig. 4, where fig. 4 illustrates a schematic diagram of a protection circuit of a power semiconductor device provided in the embodiment of the present invention, and MGND represents an output terminal of the protection circuit and is a relative ground point of an input terminal of the protection module 11.
Wherein, the protection module 11 may include:
a first resistor R1First resistance R1Is connected to the control module 12;
first NMOS Stack Q1First NMOS stack Q1Gate g and first resistor R1Is connected to the second terminal of the first NMOS stack Q1Is connected to the cathode K, a first NMOS stack Q1The source s of (a) is grounded;
a second resistor R2A second resistance R2First terminal and control module12, connecting;
second NMOS Stack Q2Second NMOS stack Q2Gate g and second resistor R2Second terminal of the second NMOS stack Q2Is connected with the gate G, and a second NMOS stack Q2Is grounded.
The shutdown module 10 may comprise a third NMOS stack Q3And a capacitor C, wherein the third NMOS stack Q3Is connected to the control module 12, a third NMOS stack Q3Is connected with the gate G, and a third NMOS stack Q3Is grounded.
As another example, referring to fig. 5, fig. 5 is a schematic structural diagram of a power semiconductor device protection circuit provided in an embodiment of the present invention, where the power semiconductor device protection circuit may further include:
a power supply module 13, the power supply module 13 being configured to supply a voltage to the capacitor C;
a detection module 14, the detection module 14 being configured to detect the voltage module 13 and the third NMOS stack Q respectively3And the voltage signal of the capacitor C, and sends a detection signal to the control module 12 based on the voltage signal, so that the control module 12 determines whether the power semiconductor device is short-circuited based on the detection signal.
As an example, referring to fig. 6, fig. 6 shows a schematic diagram of a power semiconductor device protection circuit according to another embodiment of the present invention, wherein the detection module 14 may include:
a first comparator circuit 141, a positive input terminal of the first comparator circuit 141 is connected to the input terminal of the power module 13, and a negative input terminal of the first comparator circuit 141 is connected to the first reference voltage Vref1The output terminal of the first comparator circuit 141 is connected to the control module 12, and the voltage at the input terminal of the power module 13 is lower than the first reference voltage Vref1When, the first comparator circuit 141 outputs a power down signal;
a second comparator circuit 142, a positive input terminal of the second comparator circuit 142 is connected to the first terminal of the capacitor C, and a negative input terminal of the second comparator circuit 142 is connected to a second reference voltage Vref2The output of the second comparator circuit 142 is electrically connected to the control module 12The voltage of the first end of the capacitor C is less than the second reference voltage Vref2Meanwhile, the second comparator circuit 142 outputs a voltage abnormality signal;
a third comparator circuit 143, a positive input terminal of the third comparator circuit 143 being connected to the third NMOS stack Q3A negative input terminal of the third comparator circuit 143 is connected to a third reference voltage Vref3The output terminal of the third comparator circuit 143 is connected to the control module 12, and the voltage at the input terminal of the gate g is greater than the third reference voltage Vref3The third comparator circuit 143 outputs a high signal indicating that the input terminal of the gate g has a voltage signal.
The turn-off state of the GCT can be divided into static turn-off and dynamic turn-off, the dynamic turn-off is the process of switching the GCT from the turn-on state to the static turn-off, the duration of the dynamic turn-off is very short, usually microsecond, and the preset duration T of the normal dynamic turn-off can be set based on the dynamic turn-off.
Referring to fig. 1, when the GCT is normally turned off, current flows from the source s to the drain d of the NMOS stack, no current flows after the GCT is turned off, and the gate G is grounded; as shown in fig. 2, when the GK of the GCT is short-circuited, the current flows from the drain d to the source s of the NMOS stack, and thus it can be seen that the gate G voltages to the ground are different in different states, and the gate G voltage is raised when the GK of the GCT is short-circuited; in addition, when the GK of the GCT is short-circuited and the power supply voltage is powered down, the voltage of the first end of the capacitor C also drops, so that the detection module 14 can be used for respectively detecting the power supply module 13 and the third NMOS stack Q3And the voltage signal of the capacitor C, and sends a detection signal to the control module 12 based on the voltage signal, so that the control module 12 determines whether the power semiconductor device is short-circuited based on the detection signal.
As an example, the control module 12 is further configured to: when the power semiconductor device is in static turn-off, judging whether the power semiconductor device is in short circuit or not based on the detection signal;
when the control module 12 receives the detection signals of the power-down signal and the voltage abnormal signal, the control module 12 judges that the power semiconductor device is short-circuited; alternatively, the first and second electrodes may be,
when the control module 12 receives the detection signal of the high level signal, the control module 12 determines that the power semiconductor device is short-circuited.
As another example, the control module 12 is further configured to: when the power semiconductor device is in a dynamic turn-off state, judging whether the power semiconductor device is short-circuited or not based on the detection signal;
when the control module 12 receives the detection signals of the power-down signal and the voltage abnormal signal, the control module 12 judges that the power semiconductor device is short-circuited; alternatively, the first and second electrodes may be,
when the control module 12 receives the detection signal of the high level signal and the duration of the high level signal is longer than the preset duration, the control module 12 determines that the power semiconductor device is short-circuited.
As another example, referring to fig. 7, fig. 7 shows a schematic diagram of a power semiconductor device protection circuit provided by another embodiment of the present invention, and the power semiconductor device protection circuit differs from the power semiconductor device protection circuit shown in fig. 6 mainly in that a switching element 15 is further provided, the switching element 15 is connected between a gate and a cathode of the power semiconductor device, and as a specific example, the switching element 15 may be a relay K, JFET or a MOSFET. Taking the relay K as the power semiconductor device protection circuit of the switch element 15 as an example, when the power semiconductor device is powered on, the control module 12 controls the relay K to be closed, and then controls the relay K to be disconnected after the power semiconductor device is powered on; when the power semiconductor device is powered off, the control module 12 controls the relay K to be closed, so that the gate pole and the cathode of the power semiconductor device are short-circuited, and the power semiconductor device is prevented from being damaged due to overhigh withstand voltage or overlarge voltage change rate of the anode and cathode devices. It should be noted that, because the protection circuit 12 has a faster turn-off speed relative to the relay K, when receiving an instruction for indicating a short circuit of the power semiconductor device, the protection circuit 12 can preferentially implement a short circuit between the gate and the cathode of the power semiconductor device, so as to perform circuit protection more quickly and effectively.
The protection circuit for the power semiconductor device provided by the embodiment of the invention comprises a shutdown module 10, a protection module 11 and a control module 12. The control module 12 is configured to control the shutdown module 10 to act to disconnect the shutdown circuit in response to an instruction for indicating a short circuit of the power semiconductor device, so that the MOS device on the shutdown circuit can still be protected after GCT failure or GK short circuit caused by an external reason; in addition, the protection module 11 is also controlled to operate to switch on the protection circuit, so as to realize a GK short circuit, effectively improve the pressure bearing capacity and the boosting rate of the power semiconductor device, ensure the safety of the protection circuit which can be quickly switched on and protecting the whole power semiconductor drive switching-off circuit such as the GCT device and the third MOS stack under the condition that the GK short circuit is caused by external factors, and simultaneously improve the applicability, reliability and repeated applicability of the power semiconductor device.
The above is a power semiconductor device protection circuit provided in the embodiments of the present invention, and accordingly, the present invention also provides a control method of a power semiconductor device protection circuit, which is specifically described in the second embodiment.
Example two
Referring to fig. 8, fig. 8 is a schematic flow chart illustrating a control method of a power semiconductor device protection circuit according to an embodiment of the present invention, where the method is implemented based on the power semiconductor device protection circuit in the first embodiment, and includes:
step S801: and controlling the action of the turn-off module to turn off the turn-off circuit and controlling the action of the protection circuit to turn on the protection circuit in response to the instruction of the power semiconductor device short circuit.
As shown in fig. 6, the power semiconductor device may be an IGCT device, and the turn-off module 10 may include a third NMOS stack Q3And a capacitor C, wherein the third NMOS stack Q3Is connected to the control module 12, a third NMOS stack Q3Is connected with the gate G, and a third NMOS stack Q3Is grounded.
The protection module may include:
a first resistor R1First resistance R1Is connected to the control module 12;
first NMOS Stack Q1First NMOS stack Q1Gate g and first resistor R1Is connected to the second terminal of the first NMOS stack Q1Is connected to the cathode K, a first NMOS stack Q1The source s of (a) is grounded;
a second resistor R2A second resistance R2Is connected to the control module 12;
second NMOS Stack Q2Second NMOS stack Q2Gate g and second resistor R2Second terminal of the second NMOS stack Q2Is connected with the gate G, and a second NMOS stack Q2Is grounded.
In the embodiment of the present invention, before performing step S801, it may further be determined that the GCT is normally turned off, turned on, or abnormally turned off, that is, it is determined whether the GCT is short-circuited, and as an example, before performing step S801, the method may further include:
receiving detection signals of the power module, the third MOS stack and the capacitor;
judging whether the power semiconductor device is short-circuited based on the detection signal;
when the power semiconductor device is in a static off state and a power failure signal of a power module and a voltage abnormal signal of a capacitor are received, judging that the power semiconductor device is in a short circuit; alternatively, the first and second electrodes may be,
and when a high-level signal of the third MOS stack is received, judging that the power semiconductor device is short-circuited.
As another example, before performing step S801, the method may further include:
receiving detection signals of the power module, the third MOS stack and the capacitor;
judging whether the power semiconductor device is short-circuited based on the detection signal;
when the power semiconductor device is in a dynamic turn-off state and a power failure signal of a power module and a voltage abnormal signal of a capacitor are received, judging that the power semiconductor device is in a short circuit; alternatively, the first and second electrodes may be,
and when the high-level signal of the third MOS stack is received and the duration of the high-level signal is longer than the preset duration, judging that the power semiconductor device is short-circuited.
As a specific example, canThe first comparator 142 is used to detect the input terminal of the power module 13, and VIN _ DROP represents the power-down signal of the input terminal; detecting the voltage at the first end of the capacitor C by using a second comparator circuit 142, wherein VK _ OK represents a voltage normal signal at the first end, and VK _ ERROR represents a voltage abnormal signal at the first end; detecting third NMOS Stack Q Using third comparator 1433When the output of the third comparator 143 is at a low level, VMOS _ ON represents that the input terminal of the gate g has no voltage signal, and VMOS _ OFF represents that the input terminal of the gate g has a voltage signal.
When the GCT is in static off: VK _ OK and VMOS _ ON are received and a transition to the third NMOS stack Q is detected3Outputting a hard shutdown signal HOFF, outputting no control instruction to the protection module 11, and judging that the GCT is in a normal shutdown state; receiving VMOS _ OFF, judging GK short circuit, GCT abnormal shut-OFF state, outputting hard shut-OFF signal HOFF to control third NMOS stack Q3The gate voltage of the first NMOS stack Q is controlled to turn off the turn-off circuit and simultaneously output a control command to the protection module 11 to turn on the first NMOS stack Q1And a second NMOS stack Q2The safety of the whole circuit can be still protected under the condition of GK short circuit caused by non-device failure; in addition, when VK _ ERROR and VIN _ DROP signals are received, GK short circuit is judged, GCT is in an abnormal turn-off state, and at the moment, a hard turn-off signal HOFF is output to control the third NMOS stack Q3The gate voltage of the first NMOS stack Q is controlled to turn off the turn-off circuit and simultaneously output a control command to the protection module 11 to turn on the first NMOS stack Q1And a second NMOS stack Q2And the safety of the whole circuit can be still protected under the condition of GK short circuit caused by non-device failure.
When GCT is on: receiving VK _ OK and VMOS _ OFF, detecting no hard OFF signal HOFF, outputting no control instruction to the protection module 11, and judging that the GCT is normally switched on; if the GK is shorted during the turn-on process, the detection signal will persist and not be processed.
When the GCT is in dynamic shutdown: VK _ OK and VMOS _ OFF are received, VMOS _ OFF is maintained for a period of time and then VMOS _ ON is received, and a third switch is detectedNMOS stack Q3Outputting a hard shutdown signal HOFF, outputting no control instruction to the protection module 11, and judging that the GCT is normally shut down; when the duration time of the VMOS _ OFF exceeds the normal turn-OFF time, namely the preset duration T, the GK short circuit is judged, abnormal turn-OFF occurs, and at the moment, a hard turn-OFF signal HOFF is output to control the third NMOS stack Q3The gate voltage of the first NMOS stack Q is controlled to turn off the turn-off circuit and simultaneously output a control command to the protection module 11 to turn on the first NMOS stack Q1And a second NMOS stack Q2The safety of the whole circuit can be still protected under the condition of GK short circuit caused by non-device failure; in addition, when VK _ ERROR and VIN _ DROP signals are received, GK short circuit is judged, GCT is in an abnormal turn-off state, and at the moment, a hard turn-off signal HOFF is output to control the third NMOS stack Q3The gate voltage of the first NMOS stack Q is controlled to turn off the turn-off circuit and simultaneously output a control command to the protection module 11 to turn on the first NMOS stack Q1And a second NMOS stack Q2And the safety of the whole circuit can be still protected under the condition of GK short circuit caused by non-device failure.
The method for controlling the power semiconductor device protection circuit provided by the embodiment of the invention is implemented based on the power semiconductor device protection circuit described in the first embodiment, and controls the shutdown module 10 to act to disconnect the shutdown circuit in response to the instruction for indicating the power semiconductor device short circuit, so that the MOS device on the shutdown circuit can be still protected after GCT fails or GK short circuit is caused by external reasons; meanwhile, the protection module 11 is controlled to act to switch on the protection circuit, so that the GK short circuit is ensured, the bearing capacity and the boosting rate of the power semiconductor device are effectively improved, the safety of the protection circuit, the GCT device, the third MOS stack and other whole power semiconductor drive switching-off circuits can be rapidly switched on under the condition that the GK short circuit is caused by external factors is ensured, and the applicability, the reliability and the repeated applicability of the power semiconductor device are improved.
In another aspect of the present application, a storage medium is provided, and a computer program is stored on the storage medium, and when being executed by a processor, the computer program can implement the control method of the power semiconductor device protection circuit according to the second embodiment.
In another aspect of the present application, there is provided an apparatus, which is shown in fig. 9, and fig. 9 is a schematic structural diagram of an apparatus provided in an embodiment of the present invention, and includes:
a memory 91 and a controller 92, wherein the memory 91 stores a computer program, and the computer program can realize the control method of the power semiconductor device protection circuit according to the second embodiment when the computer program is executed by the controller 92.
The processes, functions, methods, and/or software described above may be recorded, stored, or fixed in one or more computer-readable storage media that include program instructions to be implemented by a computer to cause a processor to execute the program instructions. The storage media may also include program instructions, data files, data structures, etc., alone or in combination. Storage media or program instructions may be specially designed and understood by those skilled in the computer software arts, and storage media or instructions may be known and available to those skilled in the computer software arts. Examples of computer-readable storage media include: magnetic media such as hard disks, floppy disks, and magnetic tape; optical media, such as CDROM disks and DVDs; magneto-optical media, e.g., optical disks; and hardware devices specifically configured to store and execute program instructions, such as Read Only Memory (ROM), Random Access Memory (RAM), flash memory, and the like. Examples of program instructions include both machine code, such as produced by a compiler, and files containing higher level code that may be executed by the computer using an interpreter. The described hardware devices may be configured to act as one or more software modules to perform the operations and methods described above, and vice versa. In addition, computer readable storage media may be distributed over network coupled computer systems and may store and execute computer readable code or program instructions in a distributed fashion.
It should be noted that the device may include one or more controllers and a memory, and the controllers and the memory may be connected by a bus or other means. The memory, which is a non-volatile computer-readable storage medium, may be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The controller executes various functional applications and data processing of the device by running the nonvolatile software programs, instructions, and modules stored in the memory, that is, implements the control method of the power semiconductor device protection circuit as described above.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (11)

1. A power semiconductor device protection circuit, comprising: the device comprises a turn-off module, a protection module and a control module;
the control module is connected with the off-terminal module and the protection module, and is configured to control the action of the off-module to disconnect an off-circuit and control the action of the protection module to connect a protection circuit in response to a power semiconductor device short-circuit instruction;
the turn-off module is connected between a gate and a cathode of the power semiconductor device and is configured to open the turn-off circuit in response to a control instruction of the control module;
the protection module is connected between the gate and the cathode of the power semiconductor device, and the protection module is configured to turn on the protection circuit in response to a control command of the control module.
2. The power semiconductor device protection circuit according to claim 1, wherein the protection module comprises:
the first end of the first resistor is connected with the control module;
the grid electrode of the first MOS stack is connected with the second end of the first resistor, the drain electrode of the first MOS stack is connected with the cathode, and the source electrode of the first MOS stack is grounded;
the first end of the second resistor is connected with the control module;
and the grid electrode of the second MOS stack is connected with the second end of the second resistor, the drain electrode of the second MOS stack is connected with the gate electrode, and the source electrode of the second MOS stack is grounded.
3. The power semiconductor device protection circuit according to claim 1 or 2, wherein the shutdown module comprises:
a third MOS stack and a capacitor;
the grid electrode of the third MOS stack is connected with the control module, the drain electrode of the third MOS stack is connected with the gate electrode, and the source electrode of the third MOS stack is grounded;
the first end of the capacitor is connected with the cathode, and the second end of the capacitor is grounded.
4. The power semiconductor device protection circuit according to claim 3, further comprising:
a power module configured to provide a voltage to the capacitance;
a detection module configured to detect voltage signals of the power supply module, the third MOS stack, and the capacitor, respectively, and send a detection signal to the control module based on the voltage signals, so that the control module determines whether the power semiconductor device is short-circuited based on the detection signal.
5. The power semiconductor device protection circuit of claim 4, wherein the detection module comprises:
the positive input end of the first comparator circuit is connected with the input end of the power supply module, the negative input end of the first comparator circuit is connected with a first reference voltage, the output end of the first comparator circuit is connected with the control module, and when the voltage of the input end of the power supply module is smaller than the first reference voltage, the first comparator circuit outputs a power-down signal;
a positive input end of the second comparator circuit is connected to the first end of the capacitor, a negative input end of the second comparator circuit is connected to a second reference voltage, an output end of the second comparator circuit is connected to the control module, and when the voltage at the first end of the capacitor is smaller than the second reference voltage, the second comparator circuit outputs a voltage abnormal signal;
and a positive input end of the third comparator circuit is connected with the gate of the third MOS stack, a negative input end of the third comparator circuit is connected with a third reference voltage, an output end of the third comparator circuit is connected with the control module, and when the voltage of the input end of the gate is greater than the third reference voltage, the third comparator circuit outputs a high-level signal to indicate that the input end of the gate has a voltage signal.
6. The power semiconductor device protection circuit according to claim 1, wherein the power semiconductor device comprises: an integrated gate commutated thyristor, an emitter turn-off thyristor, a gate commutated thyristor or a gate turn-off thyristor.
7. A control method of a power semiconductor device protection circuit, the method being implemented based on the power semiconductor device protection circuit according to any one of claims 1 to 6, comprising:
and controlling the action of the turn-off module to turn off the turn-off circuit and controlling the action of the protection module to turn on the protection circuit in response to the instruction of the power semiconductor device short circuit.
8. The method of claim 7, wherein prior to said controlling a shutdown module action to turn off a shutdown circuit and controlling a protection module action to turn on a protection circuit in response to the instruction to short circuit the power semiconductor device, the method further comprises:
receiving detection signals of the power module, the third MOS stack and the capacitor;
judging whether the power semiconductor device is short-circuited or not based on the detection signal;
when the power semiconductor device is in a static off state and a power-down signal of the power module and a voltage abnormal signal of the capacitor are received, judging that the power semiconductor device is in a short circuit; alternatively, the first and second electrodes may be,
and when a high-level signal of the third MOS stack is received, judging that the power semiconductor device is short-circuited.
9. The method of claim 7, wherein prior to said controlling a shutdown module action to turn off a shutdown circuit and controlling a protection module action to turn on a protection circuit in response to the instruction to short circuit the power semiconductor device, the method further comprises:
receiving detection signals of the power module, the third MOS stack and the capacitor;
judging whether the power semiconductor device is short-circuited or not based on the detection signal;
when the power semiconductor device is in a dynamic turn-off state and a power-down signal of the power module and a voltage abnormal signal of the capacitor are received, judging that the power semiconductor device is in a short circuit; alternatively, the first and second electrodes may be,
and when a high level signal of the third MOS stack is received and the duration of the high level signal is longer than a preset duration, judging that the power semiconductor device is short-circuited.
10. A storage medium having stored thereon a computer program which, when executed by a processor, is capable of implementing a method of controlling a power semiconductor device protection circuit according to any one of claims 7 to 9.
11. An apparatus, comprising: a memory having stored thereon a computer program which, when executed by the controller, is capable of implementing a method of controlling a power semiconductor device protection circuit as claimed in any one of claims 7 to 9.
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