CN112803373B - Power semiconductor device protection circuit, control method, storage medium, and apparatus - Google Patents
Power semiconductor device protection circuit, control method, storage medium, and apparatus Download PDFInfo
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- CN112803373B CN112803373B CN202011474538.8A CN202011474538A CN112803373B CN 112803373 B CN112803373 B CN 112803373B CN 202011474538 A CN202011474538 A CN 202011474538A CN 112803373 B CN112803373 B CN 112803373B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
- H02H7/205—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment for controlled semi-conductors which are not included in a specific circuit arrangement
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Abstract
The invention discloses a power semiconductor device protection circuit, a control method, a storage medium and equipment. The control module is configured to control the turn-off module to act to turn off the turn-off circuit in response to an instruction for indicating the short circuit of the power semiconductor device, so that the power semiconductor device can still be protected from being turned off after the power semiconductor device fails or a gate cathode is short-circuited due to external reasons; in addition, the protection module is controlled to act to switch on the protection circuit, so that the door cathode short circuit is ensured to be realized, the pressure bearing capacity and the pressure increasing rate of the power semiconductor device are effectively improved, the protection circuit can be quickly switched on under the condition that the door cathode short circuit is caused by external factors, the safety of the whole power semiconductor drive turn-off circuit is protected, and meanwhile, the applicability, the reliability and the repeated application of the power semiconductor device are improved.
Description
Technical Field
The present invention relates to the field of electronic circuits, and in particular, to a power semiconductor device protection circuit, a control method, a storage medium, and an apparatus.
Background
In the prior art, the switching control of the thyristor is realized by a matched gate driving unit, taking the switching control of an Integrated Gate Commutated Thyristor (IGCT) as an example, the IGCT comprises an anode (a), a gate (G) and a cathode (K), when the IGCT is turned off, the cathode current is commutated to the gate and is turned off hard by a turn-off circuit connected with the gate, as shown in fig. 1, fig. 1 shows a turn-off current path diagram of the gate of the IGCT, and as can be seen in fig. 1, the cathode current is all turned on by the turn-off circuit when the hard turn-off is realized, therefore, the turn-off circuit needs multiple devices to be connected in parallel, and a plurality of turn-off MOSFETs and a plurality of capacitors can be connected in parallel.
In order to realize the frequency hard turn-off of the IGCT, the capacity of the capacitor stack of the turn-off circuit can reach several tens millifarads (mF), when the GCT device fails to be short-circuited or the GK is short-circuited due to external reasons, the turn-off MOSFET stack is turned on when the IGCT is turned off, and still turn-off the switching tube signal, the turn-off capacitor stack can be short-circuited, so that the energy of the short circuit of the capacitor stack can completely pass through the turn-off MOSFET, thereby causing the MOSFET to fail and affecting the safety of the whole thyristor drive turn-off circuit, as shown in fig. 2, fig. 2 shows a short circuit current path diagram when the GK is short-circuited.
Disclosure of Invention
The invention aims to solve the technical problems that: how to quickly realize the protection of the whole gate drive turn-off circuit under the condition of the gate cathode short circuit of the power semiconductor device.
In order to solve the technical problems, the invention provides a power semiconductor device protection circuit, a control method, a storage medium and equipment.
In a first aspect of the present invention, there is provided a power semiconductor device protection circuit comprising: the system comprises a shut-down module, a protection module and a control module;
The control module is connected with the gateway module and the protection module, and is configured to respond to an instruction of short circuit of the power semiconductor device to control the action of the shutdown module to disconnect the shutdown circuit and control the action of the protection module to connect the protection circuit;
The turn-off module is connected between a gate and a cathode of the power semiconductor device, and is configured to disconnect the turn-off circuit in response to a control instruction of the control module;
the protection module is connected between a gate and a cathode of the power semiconductor device, and is configured to turn on the protection circuit in response to a control instruction of the control module.
Optionally, the protection module includes:
the first end of the first resistor is connected with the control module;
The grid electrode of the first MOS stack is connected with the second end of the first resistor, the drain electrode of the first MOS stack is connected with the cathode, and the source electrode of the first MOS stack is grounded;
The first end of the second resistor is connected with the control module;
and the grid electrode of the second MOS stack is connected with the second end of the second resistor, the drain electrode of the second MOS stack is connected with the gate electrode, and the source electrode of the second MOS stack is grounded.
Optionally, the shutdown module includes:
a third MOS stack and a capacitor;
The grid electrode of the third MOS stack is connected with the control module, the drain electrode of the third MOS stack is connected with the gate electrode, and the source electrode of the third MOS stack is grounded;
the first end of the capacitor is connected with the cathode, and the second end of the capacitor is grounded.
Optionally, the power semiconductor device protection circuit further includes:
a power module configured to provide a voltage to the capacitor;
The detection module is configured to detect voltage signals of the power supply module, the third MOS stack and the capacitor respectively, and send detection signals to the control module based on the voltage signals, so that the control module judges whether the power semiconductor device is short-circuited based on the detection signals.
Optionally, the detection module includes:
the positive input end of the first comparator circuit is connected with the input end of the power supply module, the negative input end of the first comparator circuit is connected with a first reference voltage, the output end of the first comparator circuit is connected with the control module, and when the voltage of the input end of the power supply module is smaller than the first reference voltage, the first comparator circuit outputs a power-off signal;
the positive input end of the second comparator circuit is connected with the first end of the capacitor, the negative input end of the second comparator circuit is connected with a second reference voltage, the output end of the second comparator circuit is connected with the control module, and when the voltage of the first end of the capacitor is smaller than the second reference voltage, the second comparator circuit outputs a voltage abnormality signal;
And the positive input end of the third comparator circuit is connected with the grid electrode of the third MOS stack, the negative input end of the third comparator circuit is connected with a third reference voltage, the output end of the third comparator circuit is connected with the control module, and when the voltage of the input end of the grid electrode is larger than the third reference voltage, the third comparator circuit outputs a high-level signal for indicating that the input end of the grid electrode has a voltage signal.
Optionally, the power semiconductor device includes: the gate commutating thyristor, the emitter turn-off thyristor, the gate commutating thyristor and the gate turn-off thyristor are integrated.
In a second aspect of the present invention, there is provided a control method of a power semiconductor device protection circuit, the method being implemented based on the power semiconductor device protection circuit as described above, comprising:
the turn-off module is controlled to act to turn off the turn-off circuit and the protection module is controlled to act to turn on the protection circuit in response to an instruction of a short circuit of the power semiconductor device.
Optionally, before the controlling the shutdown module to act to open the shutdown circuit and the controlling the protection module to act to close the protection circuit in response to the instruction of the short circuit of the power semiconductor device, the method further includes:
receiving detection signals of the power supply module, the third MOS stack and the capacitor;
judging whether the power semiconductor device is short-circuited or not based on the detection signal;
When the power semiconductor device is in a static off state, judging that the power semiconductor device is short-circuited when a power-down signal of the power module and a voltage abnormality signal of the capacitor are received; or alternatively
And when the high-level signal of the third MOS stack is received, judging that the power semiconductor device is short-circuited.
Optionally, before the controlling the shutdown module to act to open the shutdown circuit and the controlling the protection module to act to close the protection circuit in response to the instruction of the short circuit of the power semiconductor device, the method further includes:
receiving detection signals of the power supply module, the third MOS stack and the capacitor;
judging whether the power semiconductor device is short-circuited or not based on the detection signal;
when the power semiconductor device is in a dynamic off state, judging that the power semiconductor device is short-circuited when a power-down signal of the power module and a voltage abnormality signal of the capacitor are received; or alternatively
And judging that the power semiconductor device is short-circuited when the high-level signal of the third MOS stack is received and the duration time of the high-level signal is longer than a preset duration time.
In a third aspect of the present invention, there is provided a storage medium having stored thereon a computer program which, when executed by a processor, is capable of implementing the control method of the power semiconductor device protection circuit as described above.
In a fourth aspect of the invention, there is provided an apparatus comprising: a memory and a controller, the memory having stored thereon a computer program which, when executed by the controller, enables the control method of the power semiconductor device protection circuit as described above to be implemented.
One or more embodiments of the above-described solution may have the following advantages or benefits compared to the prior art:
The power semiconductor device protection circuit, the control method, the storage medium and the equipment applying the invention comprise a turn-off module, a protection module and a control module. The control module is configured to control the turn-off module to act to turn off the turn-off circuit in response to an instruction for indicating the short circuit of the power semiconductor device, so that after the GCT fails or the GK is short-circuited due to external reasons, the MOS device on the turn-off circuit can be still protected; in addition, the protection module is controlled to act to switch on the protection circuit, so that GK short circuit is guaranteed to be realized, the pressure bearing capacity and the pressure increasing rate of the power semiconductor device are effectively improved, the safety of the whole power semiconductor drive switch-off circuit such as the protection circuit, the GCT device and the third MOS stack can be rapidly switched on under the condition that the GK short circuit is caused by external factors, and meanwhile, the applicability, the reliability and the repeated applicability of the power semiconductor device are improved.
Drawings
The scope of the present disclosure may be better understood by reading the following detailed description of exemplary embodiments in conjunction with the accompanying drawings. The drawings included herein are:
FIG. 1 shows an IGCT gate turn-off current path diagram;
FIG. 2 shows a short circuit current path diagram when GK is shorted;
Fig. 3 is a schematic structural diagram of a protection circuit for a power semiconductor device according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a power semiconductor device protection circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram showing a structure of a power semiconductor device protection circuit according to another embodiment of the present invention;
fig. 6 is a schematic diagram of a power semiconductor device protection circuit according to another embodiment of the present invention;
fig. 7 is a schematic diagram of a power semiconductor device protection circuit according to another embodiment of the present invention;
fig. 8 is a schematic flow chart of a control method of a power semiconductor device protection circuit according to an embodiment of the present invention;
Fig. 9 shows a schematic diagram of an apparatus structure according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following detailed description of the implementation method of the present invention will be given with reference to the accompanying drawings and examples, by which the technical means are applied to solve the technical problems, and the implementation process for achieving the technical effects can be fully understood and implemented accordingly.
In the prior art, the switching control of the thyristor is realized by a matched gate driving unit, taking the switching control of an Integrated Gate Commutated Thyristor (IGCT) as an example, the IGCT comprises an anode (a), a gate (G) and a cathode (K), when the IGCT is turned off, the cathode current is commutated to the gate and is turned off hard by a turn-off circuit connected with the gate, as shown in fig. 1, fig. 1 shows a turn-off current path diagram of the gate of the IGCT, and as can be seen in fig. 1, the cathode current is all turned on by the turn-off circuit when the hard turn-off is realized, therefore, the turn-off circuit needs multiple devices to be connected in parallel, and a plurality of turn-off MOSFETs and a plurality of capacitors can be connected in parallel.
In order to realize the frequency hard turn-off of the IGCT, the capacity of the capacitor stack of the turn-off circuit can reach several tens millifarads (mF), when the GCT device fails to be short-circuited or the GK is short-circuited due to external reasons, the turn-off MOSFET stack is turned on when the IGCT is turned off, and still turn-off the switching tube signal, the turn-off capacitor stack can be short-circuited, so that the energy of the short circuit of the capacitor stack can completely pass through the turn-off MOSFET, thereby causing the MOSFET to fail and affecting the safety of the whole thyristor drive turn-off circuit, as shown in fig. 2, fig. 2 shows a short circuit current path diagram when the GK is short-circuited.
In view of this, the present application provides a power semiconductor device protection circuit, a control method, a storage medium, and an apparatus, which includes a shutdown module 10, a protection module 11, and a control module 12. Wherein, the control module 12 is configured to control the turn-off module 10 to act to turn off the turn-off circuit in response to an instruction for indicating a short circuit of the power semiconductor device, so that after the GCT fails or the external cause causes the GK to short circuit, the MOS device on the turn-off circuit can still be protected; in addition, the protection module 11 is controlled to act to turn on the protection circuit, so as to ensure that the GK short circuit is realized, effectively improve the pressure bearing capacity and the pressure increasing rate of the power semiconductor device, and can quickly turn on the protection circuit, protect the safety of the whole power semiconductor drive turn-off circuit such as the GCT device, the third MOS stack and the like under the condition that the GK short circuit is caused by external factors, and simultaneously improve the applicability, the reliability and the repeated applicability of the power semiconductor device.
Example 1
Referring to fig. 3, fig. 3 shows a schematic structural diagram of a power semiconductor device protection circuit according to an embodiment of the present invention, which includes: a shut down module 10, a protection module 11 and a control module 12,
Wherein, the control module 12 is connected with the turn-off module 10 and the protection module 11, and the control module 12 is configured to respond to the instruction of short circuit of the power semiconductor device to control the turn-off module 10 to act to turn off the turn-off circuit and control the protection module 11 to act to turn on the protection circuit;
the turn-off module 10 is connected between the gate and the cathode of the power semiconductor device, the turn-off module 10 being configured to open the turn-off circuit in response to a control instruction of the control module 12;
The protection module 11 is connected between the gate and the cathode of the power semiconductor device, and the protection module 11 is configured to turn on a protection circuit in response to a control instruction of the control module 12.
In the embodiment of the present application, the power semiconductor device may be an integrated gate commutated thyristor, an emitter turn-off thyristor, a gate commutated thyristor or a gate turn-off thyristor, and in the present application, an Integrated Gate Commutated Thyristor (IGCT) will be described as an example, where the IGCT is a device formed by integrating a gate driving circuit and a gate commutated thyristor GCT into one unit, and the gate driving circuit may be further divided into an on circuit and an off circuit, where the on circuit may be conventionally provided in the prior art, the off circuit belongs to the off module 10, and the off circuit may be formed by using an NMOS stack and a capacitor as an example; as another example, the shutdown circuit may also be formed using a PMOS stack and a capacitor. In the following description, a shutdown circuit composed of an NMOS stack and a capacitor will be described as an example.
The protection module 11 includes a first resistor, a first MOS stack, a second resistor, and a second MOS stack, where the first MOS stack and the second MOS stack may be selected as an NMOS stack or a PMOS stack at the same time, in this embodiment of the present invention, an NMOS stack will be described as an example, referring to fig. 4 specifically, fig. 4 shows a schematic diagram of a power semiconductor device protection circuit provided in this embodiment of the present invention, and MGND represents an output end of the protection circuit and is a relative grounding point of an input end of the protection module 11.
The protection module 11 may include:
The first end of the first resistor R 1 and the first end of the first resistor R 1 are connected with the control module 12;
The grid g of the first NMOS stack Q 1 is connected with the second end of the first resistor R 1, the drain d of the first NMOS stack Q 1 is connected with the cathode K, and the source s of the first NMOS stack Q 1 is grounded;
The first end of the second resistor R 2 and the second resistor R 2 are connected with the control module 12;
And a gate G of the second NMOS stack Q 2, a drain d of the second NMOS stack Q 2 and the gate G of the second NMOS stack Q 2 are connected to the second end of the second resistor R 2, and a source s of the second NMOS stack Q 2 is grounded.
The shutdown module 10 may include a third NMOS stack Q 3 and a capacitor C, where a gate G of the third NMOS stack Q 3 is connected to the control module 12, a drain d of the third NMOS stack Q 3 is connected to the gate G, and a source s of the third NMOS stack Q 3 is grounded.
As another example, referring to fig. 5, fig. 5 shows a schematic structural diagram of a power semiconductor device protection circuit provided by an embodiment of the present invention, where the power semiconductor device protection circuit may further include:
A power supply module 13, the power supply module 13 configured to supply a voltage to the capacitor C;
the detection module 14, the detection module 14 is configured to detect voltage signals of the voltage module 13, the third NMOS stack Q 3 and the capacitor C, respectively, and send detection signals to the control module 12 based on the voltage signals, so that the control module 12 determines whether the power semiconductor device is shorted based on the detection signals.
As an example, referring to fig. 6, fig. 6 is a schematic diagram of a power semiconductor device protection circuit according to another embodiment of the present invention, where the detection module 14 may include:
The positive input end of the first comparator circuit 141 is connected with the input end of the power module 13, the negative input end of the first comparator circuit 141 is connected with the first reference voltage V ref1, the output end of the first comparator circuit 141 is connected with the control module 12, and when the voltage of the input end of the power module 13 is smaller than the first reference voltage V ref1, the first comparator circuit 141 outputs a power-off signal;
The positive input end of the second comparator circuit 142 is connected with the first end of the capacitor C, the negative input end of the second comparator circuit 142 is connected with the second reference voltage V ref2, the output end of the second comparator circuit 142 is connected with the control module 12, and when the voltage of the first end of the capacitor C is smaller than the second reference voltage V ref2, the second comparator circuit 142 outputs a voltage abnormality signal;
And the positive input end of the third comparator circuit 143 is connected with the grid electrode g of the third NMOS stack Q 3, the negative input end of the third comparator circuit 143 is connected with the third reference voltage V ref3, the output end of the third comparator circuit 143 is connected with the control module 12, and when the voltage of the input end of the grid electrode g is larger than the third reference voltage V ref3, the third comparator circuit 143 outputs a high-level signal for indicating that the voltage signal exists at the input end of the grid electrode g.
The off state of the GCT may be divided into a static off state and a dynamic off state, where the dynamic off state is a process of switching the GCT from the on state to the static off state, and the duration of the dynamic off state is very short, usually in microsecond level, based on which a preset duration T of the normal dynamic off state may be set.
According to the illustration in FIG. 1, when GCT is normally turned off, current flows from the source s to the drain d of NMOS stack, no current flows after the gate is turned off, and the gate G is grounded; as shown in fig. 2, when the GK of the GCT is short-circuited, a current flows from the drain d to the source s of the NMOS stack, and it is known that the gate G is grounded in different states, and when the GK of the GCT is short-circuited, the gate G is raised; in addition, when the GK of the GCT is short-circuited, the voltage at the first end of the capacitor C is also reduced when the power supply voltage is dropped, so that the detection module 14 may detect the voltage signals of the power supply module 13, the third NMOS stack Q 3, and the capacitor C, and send detection signals to the control module 12 based on the voltage signals, so that the control module 12 determines whether the power semiconductor device is short-circuited based on the detection signals.
As an example, the control module 12 is further configured to: judging whether the power semiconductor device is short-circuited or not based on the detection signal when the power semiconductor device is in static turn-off;
When the control module 12 receives the power-down signal and the detection signal of the voltage abnormality signal, the control module 12 judges that the power semiconductor device is short-circuited; or alternatively
When the control module 12 receives the detection signal of the high level signal, the control module 12 determines that the power semiconductor device is shorted.
As another example, the control module 12 is further configured to: judging whether the power semiconductor device is in a short circuit or not based on the detection signal when the power semiconductor device is in a dynamic off state;
When the control module 12 receives the power-down signal and the detection signal of the voltage abnormality signal, the control module 12 judges that the power semiconductor device is short-circuited; or alternatively
When the control module 12 receives the detection signal of the high level signal and the duration of the high level signal is longer than the preset duration, the control module 12 determines that the power semiconductor device is short-circuited.
As another example, referring to fig. 7, fig. 7 shows a schematic diagram of a power semiconductor device protection circuit provided in another embodiment of the present invention, which is different from the power semiconductor device protection circuit shown in fig. 6 mainly in that a switching element 15 is further provided, the switching element 15 is connected between a gate and a cathode of the power semiconductor device, and as a specific example, the switching element 15 may be a relay K, JFET or a MOSFET. Taking the relay K as a power semiconductor device protection circuit of the switching element 15 as an example, when the power semiconductor device is electrified, the control module 12 controls the relay K to be closed, and controls the relay K to be opened after the electrification is completed; when the power semiconductor device is powered down, the control module 12 controls the relay K to be closed, so that a short circuit is formed between the gate electrode and the cathode electrode of the power semiconductor device, and the power semiconductor device is ensured not to be damaged due to overhigh withstand voltage or overlarge voltage change rate of the cathode and anode parts. It should be noted that, since the protection circuit 12 has a faster turn-off speed relative to the relay K, when receiving the instruction for indicating the power semiconductor device to be shorted, the short circuit between the gate and the cathode of the power semiconductor device can be preferentially realized by the protection circuit 12, so that the circuit protection can be performed more quickly and effectively.
The power semiconductor device protection circuit provided in the embodiment of the invention comprises a turn-off module 10, a protection module 11 and a control module 12. Wherein, the control module 12 is configured to control the turn-off module 10 to act to turn off the turn-off circuit in response to an instruction for indicating a short circuit of the power semiconductor device, so that after the GCT fails or the external cause causes the GK to short circuit, the MOS device on the turn-off circuit can still be protected; in addition, the protection module 11 is controlled to act to turn on the protection circuit so as to realize GK short circuit, effectively improve the bearing capacity and the boosting rate of the power semiconductor device, ensure the safety of the whole power semiconductor drive turn-off circuit such as the protection circuit, the protection GCT device, the third MOS stack and the like to be rapidly turned on under the condition that the GK short circuit is caused by external factors, and improve the applicability, the reliability and the repeated applicability of the power semiconductor device.
The above provides a power semiconductor device protection circuit according to the embodiment of the present invention, and correspondingly, the present invention also provides a control method of the power semiconductor device protection circuit, and please refer to the description of the second embodiment.
Example two
Referring to fig. 8, fig. 8 is a schematic flow chart showing a control method of a power semiconductor device protection circuit according to an embodiment of the present invention, where the method is implemented based on the power semiconductor device protection circuit in the first embodiment, and includes:
step S801: the turn-off module is controlled to act to turn off the turn-off circuit and the protection circuit is controlled to act to turn on the protection circuit in response to an instruction of a short circuit of the power semiconductor device.
As shown in fig. 6, the power semiconductor device may be an IGCT device, and the turn-off module 10 may include a third NMOS stack Q 3 and a capacitor C, where a gate G of the third NMOS stack Q 3 is connected to the control module 12, a drain d of the third NMOS stack Q 3 is connected to the gate G, and a source s of the third NMOS stack Q 3 is grounded.
The protection module may include:
The first end of the first resistor R 1 and the first end of the first resistor R 1 are connected with the control module 12;
The grid g of the first NMOS stack Q 1 is connected with the second end of the first resistor R 1, the drain d of the first NMOS stack Q 1 is connected with the cathode K, and the source s of the first NMOS stack Q 1 is grounded;
The first end of the second resistor R 2 and the second resistor R 2 are connected with the control module 12;
And a gate G of the second NMOS stack Q 2, a drain d of the second NMOS stack Q 2 and the gate G of the second NMOS stack Q 2 are connected to the second end of the second resistor R 2, and a source s of the second NMOS stack Q 2 is grounded.
In the embodiment of the present invention, before executing step S801, it may further be determined that the GCT is normally turned off, turned on, or abnormally turned off, that is, whether the GCT is shorted, which may further include, as an example, before executing step S801:
receiving detection signals of the power supply module, the third MOS stack and the capacitor;
judging whether the power semiconductor device is short-circuited or not based on the detection signal;
When the power semiconductor device is in a static off state, judging that the power semiconductor device is short-circuited when a power-down signal of the power module and a voltage abnormality signal of the capacitor are received; or alternatively
When a high level signal of the third MOS stack is received, the power semiconductor device is judged to be short-circuited.
As another example, before performing step S801, it may further include:
receiving detection signals of the power supply module, the third MOS stack and the capacitor;
judging whether the power semiconductor device is short-circuited or not based on the detection signal;
When the power semiconductor device is in a dynamic off state, judging that the power semiconductor device is short-circuited when a power-down signal of the power module and a voltage abnormality signal of the capacitor are received; or alternatively
And judging that the power semiconductor device is short-circuited when the high-level signal of the third MOS stack is received and the duration time of the high-level signal is longer than the preset duration time.
As a specific example, the first comparator 142 may be used to detect the input terminal of the power module 13, where vin_drop represents the power-down signal of the input terminal; detecting the voltage of the first terminal of the capacitor C by using the second comparator circuit 142, wherein VK_OK represents the voltage normal signal of the first terminal, and VK_ERROR represents the voltage abnormal signal of the first terminal; the voltage at the input end g of the gate electrode g of the third NMOS stack Q 3 is detected by the third comparator 143, when the output of the third comparator 143 is at a low level, vmos_on represents that the input end of the gate electrode g has no voltage signal, and when the output of the third comparator 143 is at a high level, vmos_off represents that the input end of the gate electrode g has a voltage signal.
When the GCT is in static off: receiving vk_ok and vmos_on, detecting that the hard shutdown signal HOFF is output to the third NMOS stack Q 3, and not outputting a control instruction to the protection module 11, and judging that the GCT is in a normal shutdown state; receiving VMOS_OFF, judging that GK is short-circuited, and when GCT is in an abnormal OFF state, outputting a hard OFF signal HOFF to realize the disconnection of an OFF circuit by controlling the gate voltage of a third NMOS stack Q 3, and simultaneously outputting a control instruction to a protection module 11 to conduct a first NMOS stack Q 1 and a second NMOS stack Q 2, so that the safety of the whole circuit can be still protected under the condition of GK short circuit caused by non-device failure; in addition, when vk_error and vin_drop signals are received, it is determined that GK is shorted, and GCT is in an abnormal off state, at this time, a hard off signal HOFF is output to realize the disconnection of the off circuit by controlling the gate voltage of the third NMOS stack Q 3, and at the same time, a control instruction is output to the protection module 11 to turn on the first NMOS stack Q 1 and the second NMOS stack Q 2, so that the safety of the whole circuit can be still protected under the condition of GK short circuit caused by non-device failure.
When the GCT is on: receiving vk_ok and vmos_off, and not detecting the hard shutdown signal HOFF, and not outputting a control instruction to the protection module 11, and judging that the GCT is normally turned on; if the GK is shorted during the turn-on process, the detection signal is continued and not processed.
When the GCT is in dynamic off: receiving vk_ok and vmos_off, and after vmos_off is maintained for a period of time, receiving vmos_on, detecting that the hard shutdown signal HOFF is output to the third NMOS stack Q 3, and not outputting a control instruction to the protection module 11, and judging that the GCT is normally shutdown; when the duration of VMOS_OFF exceeds the normal turn-OFF time, namely the preset time T, judging that GK is short-circuited and abnormal turn-OFF occurs, outputting a hard turn-OFF signal HOFF to realize turn-OFF of the turn-OFF circuit by controlling the gate voltage of the third NMOS stack Q 3, and simultaneously outputting a control instruction to the protection module 11 to turn on the first NMOS stack Q 1 and the second NMOS stack Q 2, so that the safety of the whole circuit can be still protected under the condition of GK short circuit caused by non-device failure; in addition, when vk_error and vin_drop signals are received, it is determined that GK is shorted, and GCT is in an abnormal off state, at this time, a hard off signal HOFF is output to realize the disconnection of the off circuit by controlling the gate voltage of the third NMOS stack Q 3, and at the same time, a control instruction is output to the protection module 11 to turn on the first NMOS stack Q 1 and the second NMOS stack Q 2, so that the safety of the whole circuit can be still protected under the condition of GK short circuit caused by non-device failure.
The above is a control method of a power semiconductor device protection circuit provided in the embodiment of the present invention, where the method is implemented based on the power semiconductor device protection circuit described in the above embodiment one, and the turn-off module 10 is controlled to act to turn off the turn-off circuit in response to an instruction for instructing a short circuit of the power semiconductor device, so that after a GCT failure or a GK short circuit caused by an external cause, a MOS device on a turn-off circuit can still be protected; meanwhile, the protection module 11 is controlled to act to switch on the protection circuit so as to ensure that the GK short circuit is realized, the pressure bearing capacity and the pressure boosting rate of the power semiconductor device are effectively improved, the safety of the whole power semiconductor drive switch-off circuit such as the protection circuit, the protection GCT device and the third MOS stack can be rapidly switched on under the condition that the GK short circuit is caused by external factors, and the applicability, the reliability and the repeated applicability of the power semiconductor device are improved.
In another aspect of the present application, there is provided a storage medium having stored thereon a computer program which, when executed by a processor, is capable of realizing the control method of the power semiconductor device protection circuit as described in the second embodiment.
In another aspect of the present application, an apparatus is provided, referring to fig. 9, fig. 9 shows a schematic structural diagram of an apparatus provided in an embodiment of the present application, which includes:
A memory 91 and a controller 92, the memory 91 storing a computer program which, when executed by the controller 92, enables the control method of the power semiconductor device protection circuit described in the above second embodiment to be implemented.
The processes, functions, methods and/or software described above may be recorded, stored or fixed in one or more computer-readable storage media that include program instructions that are to be computer-implemented to cause a processor to execute the program instructions. The storage media may also include program instructions, data files, data structures, and the like, alone or in combination. The storage media or program instructions may be specially designed and construed by those skilled in the computer software arts, and may be of the kind well known and available to those having skill in the computer software arts. Examples of the computer readable storage medium include: magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CDROM discs and DVDs; magneto-optical media, such as optical disks; and hardware devices, specifically configured to store and execute program instructions, such as read-only memory (ROM), random Access Memory (RAM), flash memory, and the like. Examples of program instructions include both machine code, such as produced by a compiler, and files containing higher level code that may be executed by the computer using an interpreter. The described hardware devices may be configured to act as one or more software modules to perform the operations and methods described above, and vice versa. In addition, the computer readable storage medium may be distributed among networked computer systems, and the computer readable code or program instructions may be stored and executed in a decentralized manner.
It is noted that the device may include one or more controllers and memory, which may be connected via a bus or other means. The memory is used as a non-volatile computer readable storage medium for storing non-volatile software programs, non-volatile computer executable programs, and modules. The controller executes various functional applications of the apparatus and data processing by running nonvolatile software programs, instructions, and modules stored in the memory, that is, implements the control method of the power semiconductor device protection circuit as described above.
Although the embodiments of the present invention are disclosed above, the embodiments are only used for the convenience of understanding the present invention, and are not intended to limit the present invention. Any person skilled in the art can make any modification and variation in form and detail without departing from the spirit and scope of the present disclosure, but the scope of the present disclosure is still subject to the scope of the present disclosure as defined by the appended claims.
Claims (8)
1. A power semiconductor device protection circuit, comprising: the device comprises a turn-off module, a protection module, a control module, a power supply module and a detection module;
The control module is connected with the turn-off module and the protection module, and is configured to respond to an instruction of short circuit of the power semiconductor device to control the turn-off module to act so as to turn off the turn-off circuit and control the protection module to act so as to turn on the protection circuit;
The turn-off module is connected between a gate and a cathode of the power semiconductor device and comprises a third MOS stack and a capacitor, wherein a gate of the third MOS stack is connected with the control module, a drain of the third MOS stack is connected with the gate, a source of the third MOS stack is grounded, a first end of the capacitor is connected with the cathode, a second end of the capacitor is grounded, and the turn-off module is configured to disconnect the turn-off circuit in response to a control instruction of the control module;
The protection module is connected between the gate electrode and the cathode electrode of the power semiconductor device and comprises a first resistor, and the first end of the first resistor is connected with the control module; the grid electrode of the first MOS stack is connected with the second end of the first resistor, the drain electrode of the first MOS stack is connected with the cathode, and the source electrode of the first MOS stack is grounded; the first end of the second resistor is connected with the control module; a second MOS stack, a grid electrode of the second MOS stack is connected with a second end of the second resistor, a drain electrode of the second MOS stack is connected with the gate electrode, a source electrode of the second MOS stack is grounded, and the protection module is configured to be connected with the protection circuit in response to a control instruction of the control module;
a power module configured to provide a voltage to the capacitor;
The detection module is configured to detect voltage signals of the power supply module, the grid electrode of the third MOS stack and the capacitor respectively, and send detection signals to the control module based on the voltage signals, so that the control module judges whether the power semiconductor device is short-circuited or not based on the detection signals under the condition that the power semiconductor device is turned off.
2. The power semiconductor device protection circuit of claim 1, wherein the detection module comprises:
the positive input end of the first comparator circuit is connected with the input end of the power supply module, the negative input end of the first comparator circuit is connected with a first reference voltage, the output end of the first comparator circuit is connected with the control module, and when the voltage of the input end of the power supply module is smaller than the first reference voltage, the first comparator circuit outputs a power-off signal;
the positive input end of the second comparator circuit is connected with the first end of the capacitor, the negative input end of the second comparator circuit is connected with a second reference voltage, the output end of the second comparator circuit is connected with the control module, and when the voltage of the first end of the capacitor is smaller than the second reference voltage, the second comparator circuit outputs a voltage abnormality signal;
And the positive input end of the third comparator circuit is connected with the grid electrode of the third MOS stack, the negative input end of the third comparator circuit is connected with a third reference voltage, the output end of the third comparator circuit is connected with the control module, and when the voltage of the input end of the grid electrode is larger than the third reference voltage, the third comparator circuit outputs a high-level signal for indicating that the input end of the grid electrode has a voltage signal.
3. The power semiconductor device protection circuit of claim 1, wherein the power semiconductor device comprises: the gate commutating thyristor, the emitter turn-off thyristor, the gate commutating thyristor and the gate turn-off thyristor are integrated.
4. A control method of a power semiconductor device protection circuit, characterized in that the method is implemented based on a power semiconductor device protection circuit according to any of the preceding claims 1 to 3, comprising:
the turn-off module is controlled to act to turn off the turn-off circuit and the protection module is controlled to act to turn on the protection circuit in response to an instruction of a short circuit of the power semiconductor device.
5. The method of claim 4, wherein prior to said controlling the shutdown module to operate to open the shutdown circuit and controlling the protection module to operate to close the protection circuit in response to an instruction to short the power semiconductor device, the method further comprises:
receiving detection signals of the power supply module, the third MOS stack and the capacitor;
judging whether the power semiconductor device is short-circuited or not based on the detection signal;
When the power semiconductor device is in a static off state, judging that the power semiconductor device is short-circuited when a power-down signal of the power module and a voltage abnormality signal of the capacitor are received; or alternatively
And when the high-level signal of the third MOS stack is received, judging that the power semiconductor device is short-circuited.
6. The method of claim 4, wherein prior to said controlling the shutdown module to operate to open the shutdown circuit and controlling the protection module to operate to close the protection circuit in response to an instruction to short the power semiconductor device, the method further comprises:
receiving detection signals of the power supply module, the third MOS stack and the capacitor;
judging whether the power semiconductor device is short-circuited or not based on the detection signal;
when the power semiconductor device is in a dynamic off state, judging that the power semiconductor device is short-circuited when a power-down signal of the power module and a voltage abnormality signal of the capacitor are received; or alternatively
And judging that the power semiconductor device is short-circuited when the high-level signal of the third MOS stack is received and the duration time of the high-level signal is longer than a preset duration time.
7. A storage medium having stored thereon a computer program which, when executed by a processor, is capable of implementing a method of controlling a power semiconductor device protection circuit according to any one of claims 4 to 6.
8. An apparatus, comprising: a memory and a controller, the memory having stored thereon a computer program which, when executed by the controller, enables the control method of the power semiconductor device protection circuit as claimed in any one of claims 4 to 6.
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| CN115085705A (en) * | 2022-05-11 | 2022-09-20 | 清华大学 | Drive protection circuit of power semiconductor device and control method |
| CN117459040B (en) * | 2023-12-21 | 2024-04-09 | 天津航空机电有限公司 | Circuit structure and method for shutdown failure protection and quick closing based on active control |
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