CN112788833A

CN112788833A - Printed circuit board and method for detecting interlayer position offset of printed circuit board

Info

Publication number: CN112788833A
Application number: CN202110034209.XA
Authority: CN
Inventors: 陆威; 唐明茹; 林佳德
Original assignee: ASE Shanghai Inc
Current assignee: ASE Shanghai Inc
Priority date: 2021-01-12
Filing date: 2021-01-12
Publication date: 2021-05-11

Abstract

The embodiment of the application relates to a printed circuit board and a method for detecting interlayer position offset of the printed circuit board. According to an embodiment of the present application, there is provided a printed circuit board including: a core layer, a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer. The first metal layer has a first graphic indicia and the second metal layer has a second graphic indicia. The first and second graphic marks constitute a layer offset detection area, and a distance between the first graphic mark and the second graphic mark in a projection plane of the first surface along a length direction of the printed circuit board is equal to a first preset offset value minus an amount of undercut of the first metal layer and the second metal layer, the first preset offset value being a first value that allows interlayer offset between the first metal layer and the second metal layer. The method for detecting the interlayer position offset of the printed circuit board can accurately and efficiently detect the interlayer of the multilayer printed circuit board by a simple method.

Description

Printed circuit board and method for detecting interlayer position offset of printed circuit board

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a printed circuit board and a method for detecting a position offset between layers of the printed circuit board.

Background

With the rapid development of semiconductor technology, the requirement for alignment between layers of a multilayer printed circuit board is higher and higher. The target-shaped icons of the traditional printed circuit board only serve as basic functions of positioning, contraposition and the like in the lamination process of the multilayer printed circuit board, and cannot accurately identify whether the multilayer printed circuit board has interlayer offset or not.

Therefore, there are many technical problems to be solved in the art regarding how to accurately detect the position offset between the layers of the printed circuit board.

Disclosure of Invention

An object of the present invention is to provide a printed circuit board and a method for detecting a position offset between layers of the printed circuit board, which can perform interlayer detection of a multi-layer printed circuit board more accurately and efficiently by a simple method.

An embodiment of the present application provides a printed circuit board, which includes: a core layer, a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer. The first metal layer is located on the first surface of the core layer and is provided with a first graphic mark. The second metal layer is disposed proximate to the first metal layer and distal to the first surface of the core layer, the second metal layer having a second graphic indicia. And the third metal layer is positioned on the second surface of the core layer, and the second surface is opposite to the first surface. The fourth metal layer is disposed proximate to the third metal layer and distal to the second surface of the core layer. The first graphic mark and the second graphic mark form a layer deviation detection area, the center of the first graphic mark and the center of the second graphic mark are both on a first straight line perpendicular to the first surface, the distance between the first graphic mark and the second graphic mark in the projection plane of the first surface along the length direction of the printed circuit board is equal to a first preset deviation value minus the corrosion amount of the first metal layer and the corrosion amount of the second metal layer, and the first preset deviation value is a first value allowing interlayer deviation between the first metal layer and the second metal layer.

In some embodiments of the present application, the third metal layer is formed simultaneously in correspondence with the first metal layer, the fourth metal layer is formed simultaneously in correspondence with the second metal layer, wherein the layer deviation detection region further includes a third graphic mark on one of the first metal layer and the second metal layer and a fourth graphic mark on one of the third metal layer and the fourth metal layer formed without corresponding to the metal layer having the third graphic mark, centers of the third graphic mark and the fourth graphic mark are both on a second straight line perpendicular to the first surface, and the distance between the third graphic mark and the fourth graphic mark in the projection plane of the first surface along the length direction of the printed circuit board is equal to the first preset offset value minus the bite etching amount of the metal layer where the third graphic mark is located and the bite etching amount of the metal layer where the fourth graphic mark is located.

In some embodiments of the present application, the printed circuit board includes four layer deviation detection regions, two of the layer deviation detection regions are symmetrically disposed at an upper end portion and a lower end portion of a left side of the printed circuit board, and the other two layer deviation detection regions are symmetrically disposed at an upper end portion and a lower end portion of a right side of the printed circuit board.

Another embodiment of the present application provides a printed circuit board, which includes: the metal core comprises a core layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a fifth metal layer and a sixth metal layer. The first metal layer is located on the first surface of the core layer and is provided with a first graphic mark. The second metal layer is disposed proximate to the first metal layer and distal to the first surface of the core layer, the second metal layer having a second graphic indicia. The third metal layer is disposed proximate to the second metal layer and distal to the first metal layer, the third metal layer having a third graphic indicia. The fourth metal layer is located on a second surface of the core layer, the second surface being opposite to the first surface. The fifth metal layer is disposed proximate to the fourth metal layer and distal from the second surface of the core layer. The sixth metal layer is disposed proximate to the fifth metal layer and distal to the fourth metal layer. The first graphic mark, the second graphic mark and the third graphic mark form a layer deviation detection area, the center of the first graphic mark, the center of the second graphic mark and the center of the third graphic mark are all on a first straight line perpendicular to the first surface, the distance between the first graphic mark and the second graphic mark in the projection plane of the first surface along the length direction of the printed circuit board and the distance between the second graphic mark and the third graphic mark in the projection plane of the first surface along the length direction of the printed circuit board are respectively equal to the sum of a first preset deviation value and the corrosion amount of a metal layer where the corresponding graphic mark is located, and the first preset deviation value is a first value allowing interlayer deviation between two adjacent metal layers.

In some embodiments of the present application, wherein the fourth metal layer is simultaneously formed corresponding to the first metal layer, the fifth metal layer is simultaneously formed corresponding to the second metal layer, the sixth metal layer is simultaneously formed corresponding to the third metal layer, the layer deviation detection area further includes a fourth graphic mark, a fifth graphic mark, and a sixth graphic mark, the fourth graphic mark is located on one of the first metal layer, the second metal layer, and the third metal layer, the fifth graphic mark and the sixth graphic mark are respectively located on both of the fourth metal layer, the fifth metal layer, and the sixth metal layer which are formed not corresponding to the metal layer having the fourth graphic mark, wherein a center of the fourth graphic mark, a center of the fifth graphic mark, and a center of the sixth graphic mark are all on a second straight line perpendicular to the first surface, and a distance between the fourth graphic mark and the fifth graphic mark in a projection plane of the first surface along a length direction of the printed circuit board and a distance between the fifth graphic mark and the sixth graphic mark in the projection plane of the first surface The distances of the six graphic marks in the projection plane of the first surface along the length direction of the printed circuit board are respectively equal to the sum of the first preset offset value minus the etching amount of the metal layer where the corresponding graphic mark is located.

In some embodiments of the present application, the layer deviation detection region further includes a seventh graphic mark, an eighth graphic mark, and a ninth graphic mark, the seventh graphic mark is located on one of the first metal layer, the second metal layer, and the third metal layer excluding the metal layer having the fourth graphic mark, the eighth graphic mark and the ninth graphic mark are located on both of the fourth metal layer, the fifth metal layer, and the sixth metal layer formed not corresponding to the metal layer having the seventh graphic mark, respectively, wherein a center of the seventh graphic mark, a center of the eighth graphic mark, and a center of the ninth graphic mark are all on a third straight line perpendicular to the first surface, and a distance between the seventh graphic mark and the eighth graphic mark in a length direction of the printed circuit board in a projection plane of the first surface and a distance between the seventh graphic mark and the ninth graphic mark in the length direction of the printed circuit board in the projection plane of the first surface are respectively Equal to the sum of the first preset offset value minus the amount of undercut of the metal layer on which the corresponding graphic mark is located.

In some embodiments of the present application, the layer bias detection region further comprises: the third graphic mark is positioned on the second metal layer, and the fourth graphic mark is positioned on the third metal layer, wherein the center of the fourth graphic mark, the center of the fifth graphic mark and the center of the sixth graphic mark are all on a fourth straight line perpendicular to the first surface, the distance between the fifth graphic mark and the sixth graphic mark in the projection plane of the first surface along the length direction of the printed circuit board is equal to the sum of a second preset offset value minus the undercut amount of the metal layer on which the corresponding graphic mark is positioned, and the second preset offset value is a second value allowing interlayer offset between two adjacent metal layers.

In some embodiments of the present application, wherein the layer deviation detection region further comprises a thirteenth graphic mark, a fourteenth graphic mark and a fifteenth graphic mark, the thirteenth graphic mark is located on the metal layer having the fourth graphic mark, the fourteenth graphic mark is located on the metal layer having the fifth graphic mark, the fifteenth graphic mark is located on the metal layer having the sixth graphic mark,

and the distance between the thirteenth graphic mark and the fourteenth graphic mark in the projection plane of the first surface along the length direction of the printed circuit board and the distance between the fourteenth graphic mark and the fifteenth graphic mark in the projection plane of the first surface along the length direction of the printed circuit board are respectively equal to the sum of the second preset offset value minus the bite amount of the metal layer where the corresponding graphic mark is located.

In some embodiments of the present application, the layer deviation detection region further comprises a sixteenth graphic mark located on the metal layer having the seventh graphic mark, a seventeenth graphic mark located on the metal layer having the eighth graphic mark, and an eighteenth graphic mark located on the metal layer having the ninth graphic mark, wherein a center of the sixteenth graphic mark, a center of the seventeenth graphic mark, and a center of the eighteenth graphic mark are all on a sixth line perpendicular to the first surface, and the distance between the sixteenth graphic mark and the seventeenth graphic mark in the projection plane of the first surface along the length direction of the printed circuit board and the distance between the seventeenth graphic mark and the eighteenth graphic mark in the projection plane of the first surface along the length direction of the printed circuit board are respectively equal to the sum of the second preset offset value minus the bite amount of the metal layer where the corresponding graphic mark is located.

In some embodiments of the present application, the layer bias detection region further comprises: and the nineteenth graphic mark, the twentieth graphic mark and the twenty-first graphic mark are positioned on a seventh straight line perpendicular to the first surface, the distance between the nineteenth graphic mark and the twentieth graphic mark in the projection plane of the first surface along the length direction of the printed circuit board and the distance between the twentieth graphic mark and the twenty-first graphic mark in the projection plane of the first surface along the length direction of the printed circuit board are respectively equal to the sum of a third preset offset value minus the etching amount of the metal layer on which the corresponding graphic mark is positioned, and the third preset offset value is a third value which allows interlayer offset between two adjacent metal layers to occur.

In some embodiments of the present application, the layer bias detection region further includes a twenty-second graphic mark located on the metal layer having the fourth graphic mark, a twenty-third graphic mark located on the metal layer having the fifth graphic mark, and a twenty-fourth graphic mark located on the metal layer having the sixth graphic mark,

and the distance between the twenty-second graphic mark and the twenty-third graphic mark in the projection plane of the first surface along the length direction of the printed circuit board and the distance between the twenty-third graphic mark and the twenty-fourth graphic mark in the projection plane of the first surface along the length direction of the printed circuit board are respectively equal to the sum of the third preset offset value minus the bite amount of the metal layer where the corresponding graphic mark is located.

In some embodiments of the application, the layer deviation detection area further includes a twenty-fifth graphic mark, a twenty-sixth graphic mark, and a twenty-seventh graphic mark, the twenty-fifth graphic mark is located on the metal layer having the seventh graphic mark, the twenty-sixth graphic mark is located on the metal layer having the eighth graphic mark, the twenty-seventh graphic mark is located on the metal layer having the ninth graphic mark, wherein a center of the twenty-fifth graphic mark, a center of the twenty-sixth graphic mark, and a center of the twenty-seventh graphic mark are all on a ninth straight line perpendicular to the first surface, and a distance between the twenty-fifth graphic mark and the twenty-sixth graphic mark in a projection plane of the first surface along a length direction of the printed circuit board and a distance between the twenty-sixth graphic mark and the twenty-seventh graphic mark in the projection plane of the first surface along the length direction of the printed circuit board are respectively equal to a third preset offset value minus a distance between the metal layers where the corresponding graphic marks are located The sum of the bite amount.

In some embodiments of the present application, the first, second and third preset offset values are different.

In some embodiments of the present application, the first predetermined offset value may be 50 microns, the second predetermined offset value may be 65 microns, and the third predetermined offset value may be 75 microns.

In some embodiments of the present application, each graphic mark may be triangular, square, or annular, and is disposed at a board edge area of the printed circuit board.

In some embodiments of the present application, the smallest diameter annular indicia may be a solid circle.

In some embodiments of the present application, the graphic indicia is made of copper.

Another embodiment of the present application provides a method for detecting a position offset between layers of a printed circuit board, which includes providing a printed circuit board as described in any of the above embodiments, irradiating the printed circuit board with X-rays, and observing whether adjacent graphic marks in the layer offset detection region are tangent or intersect.

In some embodiments of the present application, observing whether there is a tangency or intersection of adjacent graphic indicia in the layer bias detection zone comprises: it is observed whether there is a tangency or an intersection of the graphical marks having the same preset offset value.

According to the printed circuit board and the method for detecting the interlayer position offset of the printed circuit board, the interlayer detection of the multilayer printed circuit board can be carried out more accurately and efficiently by a simple method.

Drawings

FIG. 1A is a schematic diagram of a longitudinal structure of a printed circuit board according to an embodiment of the present application

FIG. 1B is a schematic diagram of a top view of the printed circuit board shown in FIG. 1A

FIG. 1C is a schematic top perspective view of the layer offset detection zone of the printed circuit board shown in FIG. 1B

FIG. 2A is a schematic diagram of a longitudinal structure of a printed circuit board according to another embodiment of the present application

FIG. 2B is a schematic diagram of a top view of the printed circuit board shown in FIG. 2A

FIG. 2C is a schematic top perspective view of a portion of a layer offset detection zone of the printed circuit board shown in FIG. 2B

FIG. 2D is a schematic top perspective view of the layer offset detection zone of the printed circuit board shown in FIG. 2B

Detailed Description

In order that the spirit of the invention may be better understood, some preferred embodiments of the invention are described below.

Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The examples of the present application should not be construed as limiting the present application.

As used herein, the terms "about", "substantially", "essentially" are used to describe and describe small variations. When used in conjunction with an event or circumstance, the terms can refer to both an instance in which the event or circumstance occurs precisely as well as an instance in which the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the terms can refer to a range of variation of less than or equal to ± 10% of the numerical value, such as less than or equal to ± 5%, less than or equal to ± 0.5%, or less than or equal to ± 0.05%. For example, two numerical values may be considered "substantially" the same if the difference between the two numerical values is less than or equal to ± 10% of the mean of the values.

Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.

In this application, unless specified or limited otherwise, "disposed," "connected," "coupled," "secured," and words of similar import are used broadly and those skilled in the art will understand that the words used above apply to situations in which, for example, a fixed connection, a removable connection, or an integrated connection; it may also be a mechanical or electrical connection; it may also be directly connected or indirectly connected through intervening structures; or may be internal to both components.

The prior art uses a target pattern to detect approximately whether a severe interlayer offset between layers of printed circuit boards has occurred. However, each layer of the circuit board may shrink or expand to some extent in the actual manufacturing process, so that the target pattern detection is not accurate enough, and the result of the interlayer offset detection cannot reflect the actual layer offset condition. In addition, for interlayer offset detection of a printed circuit board having more than four layers, particularly more than six layers, since the number of layers is too large, direct measurement by a machine is more difficult, and therefore, a simple, efficient and accurate interlayer offset detection method is sought in the industry.

In view of the above problems, embodiments of the present invention provide a printed circuit board and a method for detecting interlayer position offset of the printed circuit board, which can achieve interlayer offset detection in a more precise manner by setting different graphic marks on each metal layer of the printed circuit board and setting the size of each graphic mark according to the specific etching amount of the metal layer on which the graphic mark is located. In addition, for the detection of the interlayer offset between printed circuit boards with more layers, particularly more than six layers, the embodiment of the application provides a more convenient and efficient detection method.

Fig. 1A is a schematic longitudinal structure diagram of a printed circuit board 10 according to an embodiment of the present application. Fig. 1B is a schematic top view of the printed circuit board 10 shown in fig. 1A. Fig. 1C is a schematic top perspective view of the layer offset detection area M1 of the printed circuit board 10 shown in fig. 1B.

As shown in fig. 1A, 1B, and 1C, the printed circuit board 10 provided according to the embodiment of fig. 1A, 1B, and 1C may include: a core layer 100, a first metal layer 101, a second metal layer 102, a third metal layer 103, and a fourth metal layer 104.

The printed circuit board 10 has a length in the X direction, a height in the Y direction perpendicular to the X direction, and a width in the Z direction perpendicular to a plane in which the X direction and the Y direction lie. The entire area S of the printed circuit board 10 may be collectively configured by the board edge area S1 and the middle area S2. Structures located within the intermediate region S2, such as, but not limited to, the core layer 100, the first metal layer 101, the second metal layer 102, the third metal layer 103, and the fourth metal layer 104, may be included in the final product structure of the printed circuit board 10. The structure located within the board edge area S1 does not constitute the final product structure of the printed circuit board 10.

The core layer 100 may be any core layer commonly used in the art, and its thickness and material may be set according to specific needs. The core layer 100 has a first surface 100a and a second surface 100b opposite the first surface 100 a.

The first metal layer 101 may be located at the first surface 100a of the core layer 100. The material of first metal layer 101 disposed in intermediate region S2 may be any suitable metal in the art, such as, but not limited to, copper. The material of the first metal layer 101 disposed at the board edge region S1 may also comprise any suitable non-metallic material. The thickness of the first metal layer 101 may be set according to specific needs.

The second metal layer 102 may be disposed close to the first metal layer 101 and away from the first surface 100a of the core layer 100. The material of second metal layer 102 disposed in intermediate region S2 may be any suitable metal in the art, such as, but not limited to, copper. The material of the second metal layer 102 disposed at the plate edge region S1 may comprise any suitable non-metallic material. The thickness of second metal layer 102 may be set according to specific needs. The thickness and material of second metal layer 102 may be the same as or different from first metal layer 101.

The third metal layer 103 may be located at the second surface 100b of the core layer 100. The material of the third metal layer 103 disposed in the middle region S2 may be any suitable metal in the art, such as, but not limited to, copper. The material of the third metal layer 103 disposed at the board edge region S1 may comprise any suitable non-metallic material. The third metal layer 103 may be simultaneously formed corresponding to the first metal layer 101.

The fourth metal layer 104 may be disposed proximate to the third metal layer 103 and distal from the second surface 100b of the core layer 100. The material of the fourth metal layer 104 disposed in the middle region S2 may be any suitable metal in the art, such as, but not limited to, copper. The material of the fourth metal layer 104 disposed at the plate edge region S1 may comprise any suitable non-metallic material. Fourth metal layer 104 may be formed simultaneously corresponding to second metal layer 102.

The first metal layer 101 may have a first graphic mark 111. First graphic indicia 111 may be disposed on first metal layer 101 in edge region S1 by any suitable means such as, but not limited to, etching or plating. The first graphic indicia 111 may be made of copper. The first graphic indicia 111 may also be made of any suitable metallic material. The first graphic mark 111 may have a circular shape in a plane in which the X direction and the Z direction are located. The first graphic indicia 111 may also be any suitable shape such as, but not limited to, triangular, square, or circular. The size of the circular ring-shaped first graphic mark 111 provided at the board edge area S1 of the printed circuit board 10 may be set according to specific needs.

Second metal layer 102 may have second graphic indicia 113. Second graphic indicia 113 may be disposed on second metal layer 102 in edge region S1 by any suitable means such as, but not limited to, etching or plating. The second graphic mark 113 may be made of copper. The second graphic indicia 113 may also be made of any suitable metallic material. The second graphic mark 113 may be a solid circle in a plane in which the X direction and the Z direction are located. The second graphic indicia 113 may also be any suitable shape, such as, but not limited to, triangular, circular, or square. The ring-shaped mark having the smallest diameter of the first graphic mark 111 and the second graphic mark 113 may be a solid circle. The size of the circular second graphic mark 113 provided at the board edge area S1 of the printed circuit board 10 may be set according to specific needs, which may be smaller than the size of the first graphic mark 111. In other embodiments of the present application, the size of the first graphic mark 111 may be smaller than the size of the second graphic mark 113.

The center C1 of the first graphic mark 111 and the center C2 of the second graphic mark 113 are both on a first line L1 perpendicular to the first surface 100 a. The first line L1 is parallel to the Y direction. The pitch P1 of the first graphic mark 111 and the second graphic mark 113 in the projection plane (i.e., the plane in which the X direction and the Z direction lie) of the first surface 100a along the length direction of the printed circuit board 10, i.e., the X direction, is equal to a first preset offset value minus the amount of the bite of the first metal layer 111 and the amount of the bite of the second metal layer 113, where the first preset offset value is a first value that allows interlayer offset to occur between the first metal layer 111 and the second metal layer 113. The first value may be set according to specific needs. The "bite amount" is defined herein as the dimension of the plane in which the X-direction and Z-direction change along the X-direction after the metal layer expands or contracts. The amount of undercut is not a fixed value, but has different values depending on the different materials and thicknesses of the metal layer. For ease of understanding, this is exemplified herein. Assuming that the first value allowing the interlayer offset between the first metal layer 111 and the second metal layer 113 is 50 micrometers and the amounts of the biting of the first metal layer 111 and the second metal layer 113 are 20 micrometers and 10 micrometers, respectively, P1 is equal to the sum of the first preset offset value (50 micrometers) minus the amount of the biting of the first metal layer 111 (20 micrometers) and the amount of the biting of the second metal layer 113 (10 micrometers), i.e., P1 is equal to 20 micrometers.

The first and second

graphical indicia

111, 113 may constitute a layer deviation detection zone M1. After the printed circuit board 10 is formed, the printed circuit board 10 may be irradiated with X-rays in order to detect interlayer shift between the respective metal layers in the printed circuit board 10. The presence of tangency or intersection between adjacent graphic indicia, i.e., the first graphic indicia 111 and the second graphic indicia 113, in the layer deviation detection zone M1 may be visually or machine observed. If there is a tangent or an intersection, it means that the interlayer offset between the metal layers where the two graphic marks where the tangent or the intersection occurs is beyond the maximum allowed value.

The printed circuit board 10 may include at least one layer bias detection zone M1. To further improve the detection accuracy, the printed circuit board 10 may preferably include four layer deviation detection regions M1, two of which are symmetrically disposed at the upper end portion and the lower end portion of the left side of the printed circuit board 10, and the other two of which are symmetrically disposed at the upper end portion and the lower end portion of the right side of the printed circuit board, as shown in fig. 2C.

The printed circuit board 10 may further include an insulating layer 120 disposed between the first metal layer 101 and the second metal layer 102, between the third metal layer 103 and the fourth metal layer 104, on a surface of the second metal layer 102, and on a surface of the fourth metal layer 104. The material of the insulating layer 120 may be an insulating material commonly used in the art, such as, but not limited to, resin. The outermost insulating layer 120 may be provided with one or more metal pads, which may be made of any suitable metal material, such as, but not limited to, nickel or gold, to electrically connect with the second metal layer 102 near the uppermost side of the printed circuit board 10 and the fourth metal layer 104 near the lowermost side of the printed circuit board 10, respectively.

The printed circuit board 10 may further include a via 130 penetrating the core layer 100, the first metal layer 101, the second metal layer 102, the third metal layer 103, the fourth metal layer 104, and the insulating layer 120.

Applicants have noted that certain processes of the printed circuit board 10 may cause the metal layers to expand or contract to some degree. The layer deviation detection area M1 formed by the first graphic mark 111 and the second graphic mark 113 according to the embodiment of the present application sets the preset deviation value in consideration of the etching amounts of different metal layers, which enables detection of layer deviation with higher accuracy and precision.

For higher accuracy and precision of the interlayer offset detection, the interlayer offset detection region M1 may further include a third graphic mark 115 and a fourth graphic mark 117. A third graphic mark 115 may be located on the second metal layer 102. The fourth graphic mark 117 may be located on the third metal layer 103. In other embodiments of the present application, the third graphic mark 115 may be located on one of the first and

second metal layers

101 and 102, and the fourth graphic mark 117 may be located on one of the third and

fourth metal layers

103 and 104 formed not corresponding to the metal layer having the third graphic mark 115. The material range and arrangement method of the third graphic mark 115 and the fourth graphic mark 117 may be similar to those of the first graphic mark 111.

The center C3 of the third graphic mark 115 and the center C4 of the fourth graphic mark 117 are both on a second straight line L2 perpendicular to the first surface 100 a. The second line L2 is parallel to the Y direction and is spaced a suitable distance from the first line L1. The distance P1 between the third graphic mark 115 and the fourth graphic mark 117 in the projection plane (i.e., the plane in which the X direction and the Z direction are located) of the first surface 100a along the length direction of the printed circuit board 10, i.e., the X direction, is equal to the first preset offset value minus the amount of the bite of the metal layer on which the third graphic mark 115 is located and the amount of the bite of the metal layer on which the fourth graphic mark 117 is located.

By further setting the layer deviation detection area M1 to include the third graphic mark 115 and the fourth graphic mark 117, the embodiment of the present application can further improve the accuracy of the interlayer detection.

Fig. 2A is a schematic longitudinal structure diagram of a printed circuit board 20 according to another embodiment of the present application. Fig. 2B is a schematic top view of the printed circuit board 20 shown in fig. 2A. Fig. 2C is a schematic top perspective view of a portion of the layer offset detection zone N1 of the printed circuit board 20 shown in fig. 2B. Fig. 2D is a schematic top perspective view of the layer bias detection region N1 of the pcb shown in fig. 2B.

As shown in fig. 2A, 2B, 2C, and 2D, the printed circuit board 20 provided according to the embodiments of fig. 2A, 2B, 2C, and 2D may include: a core layer 200, a first metal layer 201, a second metal layer 202, a third metal layer 203, a fourth metal layer 204, a fifth metal layer 205, and a sixth metal layer 206.

The printed circuit board 20 has a length in the X direction, a height in the Y direction perpendicular to the X direction, and a width in the Z direction perpendicular to a plane in which the X direction and the Y direction lie. The entire area S' of the printed circuit board 20 may be composed of the board edge area S3 and the middle area S4 together. Structures located within the intermediate region S4, such as, but not limited to, the core layer 200, the first metal layer 201, the second metal layer 202, the third metal layer 203, the fourth metal layer 204, the fifth metal layer 205, and the sixth metal layer 206, may be included in the final product structure of the printed circuit board 20. The structure located within the board edge area S3 does not constitute the final product structure of the printed circuit board 20.

The core layer 200 may be any core layer commonly used in the art, and its thickness and material may be set according to specific needs. The core layer 200 has a first surface 200a and a second surface 200b opposite the first surface 200 a.

The first metal layer 201 may be located at the first surface 200a of the core layer 200. The material of the first metal layer 201 disposed in the middle region S4 may be any suitable metal in the art, such as, but not limited to, copper. The material of the first metal layer 201 disposed at the plate edge region S3 may comprise any suitable non-metallic material. The thickness of the first metal layer 201 may be set according to specific needs.

The second metal layer 202 may be disposed proximate to the first metal layer 201 and away from the first surface 200a of the core layer 200. The material of the second metal layer 202 disposed in the middle region S4 may be any suitable metal in the art, such as, but not limited to, copper. The material of the second metal layer 202 disposed at the plate edge region S3 may comprise any suitable non-metallic material. The thickness of the second metal layer 202 may be set according to specific needs. The thickness and material of the second metal layer 202 may be the same as or different from the first metal layer 201.

Third metal layer 203 may be disposed proximate to second metal layer 202 and distal to first metal layer 201. The material of third metal layer 203 disposed in intermediate region S4 may be any suitable metal in the art, such as, but not limited to, copper. The material of the third metal layer 203 disposed at the plate edge region S3 may comprise any suitable non-metallic material. The thickness of the third metal layer 203 may be set according to specific needs. The thickness and material of the third metal layer 203 may be the same as or different from the first metal layer 201.

The fourth metal layer 204 may be located at the second surface 200b of the core layer 200. The material of the fourth metal layer 204 disposed in the middle region S4 may be any suitable metal in the art, such as, but not limited to, copper. The material of the fourth metal layer 204 disposed at the plate edge region S3 may comprise any suitable non-metallic material. The fourth metal layer 204 may be simultaneously formed corresponding to the first metal layer 201.

The fifth metal layer 205 may be disposed proximate to the fourth metal layer 204 and away from the second surface 200b of the core layer 200. The material of the fourth metal layer 204 disposed in the middle region S4 may be any suitable metal in the art, such as, but not limited to, copper. The material of the fourth metal layer 204 disposed at the plate edge region S3 may comprise any suitable non-metallic material. Fifth metal layer 205 is formed simultaneously with second metal layer 202.

Sixth metal layer 206 may be disposed proximate to fifth metal layer 205 and distal to fourth metal layer 204. The material of sixth metal layer 206 disposed in intermediate region S4 may be any suitable metal in the art, such as, but not limited to, copper. The material of the sixth metal layer 206 disposed at the board edge region S3 may comprise any suitable non-metallic material. The sixth metal layer 206 is formed simultaneously with the third metal layer 203.

The first metal layer 201 may have a first graphic mark 211. The first graphic indicia 211 may be disposed on the first metal layer 201 in the edge region S3 by any suitable means such as, but not limited to, etching or plating. The first graphic indicia 211 may be made of copper. The first graphic indicia 211 may also be made of any suitable metallic material. The first graphic mark 211 may have a circular shape in a plane in which the X direction and the Z direction are located. The first graphic indicia 211 may also be any suitable shape, such as, but not limited to, triangular or square. The size of the circular ring-shaped first graphic mark 211 provided at the board edge area S3 of the printed circuit board 20 may be set according to specific needs.

The second metal layer 202 may have a second graphic mark 213. The second graphic indicia 213 may be disposed on the second metal layer 202 in the edge region S3 by any suitable means such as, but not limited to, etching or plating. The second graphic mark 213 may be made of copper. The second graphic indicia 213 may also be made of any suitable metallic material. The second graphic mark 213 may have a circular shape in a plane in which the X direction and the Z direction are located. The second graphical indicia 213 may also be any suitable shape, such as, but not limited to, a triangle or square. The size of the circular ring-shaped second graphic mark 213 provided at the board edge area S3 of the printed circuit board 20 may be set according to specific needs, which may be smaller than the size of the first graphic mark 211. In other embodiments of the present application, the size of the first graphic mark 211 may be smaller than the size of the second graphic mark 213.

The third metal layer 203 may have third graphic indicia 215. The third graphic indicia 215 may be disposed on the third metal layer 202 in the edge region S3 by any suitable means such as, but not limited to, etching or plating. Third metal layer 203 may be made of copper. Third metal layer 203 may also be made of any suitable metal material. The third graphic indicia 215 may be a solid circle in the plane of the X-direction and the Z-direction. The third graphic indicia 215 may also be any suitable shape, such as, but not limited to, a triangular shape or a circular shape. The ring-shaped mark having the smallest diameter among the first graphic mark 211, the second graphic mark 113, and the third graphic mark 215 may be a solid circle. The size of the circular third graphic mark 215 disposed at the board edge area S3 of the printed circuit board 20 may be set according to specific needs, which may be smaller than the size of the second graphic mark 213. In other embodiments of the present application, the size of the second graphic mark 213 may be smaller than the size of the third graphic mark 215.

The center E1 of the first graphic mark 211, the center E2 of the second graphic mark 213 and the center E3 of the third graphic mark 215 are all on a first straight line F1 perpendicular to the first surface 200 a. The first line F1 is parallel to the Y direction. The pitch P1 in the X direction, which is the length direction of the printed circuit board 20 in the projection plane of the first surface 200a (i.e., the plane in which the X direction and the Z direction are located), of the first graphic mark 211 and the second graphic mark 213 is equal to the first preset offset value minus the amount of the bite of the first metal layer 201 and the amount of the bite of the second metal layer 203, and the pitch P1 in the X direction, which is the length direction of the printed circuit board 20 in the projection plane of the first surface 200a (i.e., the plane in which the X direction and the Z direction are located), of the second graphic mark 213 and the third graphic mark 215 is equal to the first preset offset value minus the amount of the bite of the second metal layer 203 and the amount of the bite of the third metal layer 203. The first preset offset value is a first value that allows an interlayer offset to occur between the first metal layer 201 and the second metal layer 203. The first preset offset value is also a first value that allows interlayer offset to occur between the second metal layer 203 and the third metal layer 203. The first value may be set according to specific needs. For example, the first predetermined offset value may be about 50 microns.

The first 211, second 213, and third 215 graphical indicia may constitute a deflection detection zone N1. After the printed circuit board 20 is formed, the printed circuit board 20 may be irradiated with X-rays in order to detect an interlayer shift between the respective metal layers in the printed circuit board 20. The presence of tangency or intersection between adjacent graphic indicia, i.e., the first graphic indicia 211 and the second graphic indicia 213, and the second graphic indicia 213 and the third graphic indicia 215, in the layer deviation detection zone N1 may be observed visually or by machine. If there is a tangent or an intersection, it means that the interlayer offset between the metal layers where the two graphic marks where the tangent or the intersection occurs is beyond the maximum allowed value.

The printed circuit board 20 may include at least one layer deflection detection zone N1. To further improve the detection accuracy, the printed circuit board 20 may preferably include four layer deviation detection regions N1, two of which are symmetrically disposed at the upper end portion and the lower end portion of the left side of the printed circuit board 20, and the other two of which are symmetrically disposed at the upper end portion and the lower end portion of the right side of the printed circuit board, as shown in fig. 2B.

Printed circuit board 20 may also include an insulating layer 220 disposed between first metal layer 201 and second metal layer 202, between second metal layer 202 and third metal layer 203, between fourth metal layer 204 and fifth metal layer 205, between fifth metal layer 205 and sixth metal layer 206, on the surface of third metal layer 203, and on the surface of sixth metal layer 206. The material of the insulating layer 220 may be an insulating material commonly used in the art, such as, but not limited to, resin. The outermost insulating layer 220 may be provided with one or more metal pads, which may be made of any suitable metal material, such as, but not limited to, nickel or gold, to electrically connect with the uppermost third metal layer 203 near the printed circuit board 20 and the lowermost sixth metal layer 206 near the printed circuit board 20, respectively.

The printed circuit board 20 may also include a via 230 passing through the core layer 200, the first metal layer 201, the second metal layer 202, the third metal layer 203, the fourth metal layer 204, the fifth metal layer 205, the sixth metal layer 206, and the insulating layer 220.

Some processes of the printed circuit board 20 may cause the metal layers to expand or contract to some extent, and the layer deviation detection region N1 formed by the first graphic mark 211, the second graphic mark 213, and the third graphic mark 215 according to the embodiment of the present disclosure sets the predetermined deviation value in consideration of the etching amount of different metal layers, which enables the interlayer deviation detection with higher accuracy and precision.

Also, in order to obtain interlayer offset detection with higher accuracy and precision, the interlayer offset detection area N1 may be further provided to include a fourth graphic mark 217, a fifth graphic mark 219, and a sixth graphic mark 221. The fourth graphic mark 217 may be located on the second metal layer 202. Fifth graphic indicia 219 may be located on fourth metal layer 204. The sixth graphic mark 221 may be located on the sixth metal layer 206. In other embodiments of the present application, the fourth graphic mark 217 may be located on one of the first metal layer 201, the second metal layer 202, and the third metal layer 203. Fifth graphic mark 219 and sixth graphic mark 221 are located on two of fourth metal layer 204, fifth metal layer 205, and sixth metal layer 206, respectively, which are formed not corresponding to the metal layer having fourth graphic mark 217.

The center E4 of the fourth graphic mark 217, the center E5 of the fifth graphic mark 219 and the center E6 of the sixth graphic mark 221 are on a second straight line F2 perpendicular to the first surface 200 a. The second straight line F2 is parallel to the Y direction and is spaced a suitable distance from the first straight line F1. The pitch P1 in the length direction of the printed circuit board 20, i.e., the X direction, of the fourth graphic mark 217 and the fifth graphic mark 219 in the projection plane (i.e., the plane in which the X direction and the Z direction lie) of the first surface 200a is equal to the first preset offset value minus the amount of the bite of the second metal layer 202 and the amount of the bite of the fourth metal layer 204. The pitch P1 of the fifth graphic mark 219 and the sixth graphic mark 221 in the projection plane (i.e., the plane in which the X direction and the Z direction lie) of the first surface 200a in the lengthwise direction of the printed circuit board 20, i.e., the X direction, is equal to the first preset offset value minus the amount of the bite of the fourth metal layer 204 and the amount of the bite of the sixth metal layer 206.

By further setting the fourth graphic mark 217, the fifth graphic mark 219, and the sixth graphic mark 221, the embodiment of the present application can further improve the accuracy of interlayer detection.

For higher accuracy and precision of interlayer offset detection, the interlayer offset detection zone N1 may be further configured to include a seventh graphic mark 223, an eighth graphic mark 225, and a ninth graphic mark 227. The seventh graphic mark 223 may be located on the third metal layer 203. An eighth graphic indicia 225 may be located on the fourth metal layer 204. The ninth graphical indicia 227 may be located on the fifth metal layer 205. In other embodiments of the present application, the seventh graphic mark 223 may be located on one of the first metal layer 201, the second metal layer 202, and the third metal layer 203 excluding the metal layer having the fourth graphic mark 217, and the eighth graphic mark 225 and the ninth graphic mark 227 may be located on two of the fourth metal layer 204, the fifth metal layer 205, and the sixth metal layer 206, respectively, which are formed not corresponding to the metal layer having the seventh graphic mark 223.

The center E7 of the seventh graphic mark 223, the center E8 of the eighth graphic mark 225 and the center E9 of the ninth graphic mark 227 are on a third straight line F3 perpendicular to the first surface 200 a. The third line F3 is parallel to the Y direction and is spaced a suitable distance from the second line F2. The pitch P1 of the seventh graphic mark 223 and the eighth graphic mark 225 in the projection plane (i.e., the plane in which the X direction and the Z direction are located) of the first surface 200a in the lengthwise direction of the printed circuit board 20, i.e., the X direction, is equal to the first preset offset value minus the sum of the amounts of undercut of the metal layers in which the seventh graphic mark 223 and the eighth graphic mark 225 are located. The pitch P1 of the eighth graphic mark 225 and the ninth graphic mark 227 in the projection plane (i.e., the plane in which the X direction and the Z direction are located) of the first surface 200a in the lengthwise direction of the printed circuit board 20, i.e., the X direction, is equal to the first preset offset value minus the sum of the amounts of undercut of the metal layers in which the eighth graphic mark 225 and the ninth graphic mark 227 are located.

Detection between layers of the multi-layer board often leads to redundancy and complexity in the detection process due to excessive layers, the detection result is not accurate enough, and the detection difficulty is large. In the embodiment of the application, three different metal layers positioned on the first side of the core layer 200 are selected as a first group for detection; selecting one of three different metal layers located at a first side of the core layer 200 and two metal layers located at a second side of the core layer 200 and formed without corresponding to the selected metal layer as a second group for detection; and one of the other two metal layers except the one with the two graphic marks is further selected from the three metal layers on the first side of the core layer 200, and the two metal layers formed on the second side of the core layer 200 and not corresponding to the selected metal layers are further selected as a third group for detection, so that the purpose of multilayer plate layer deviation detection is achieved in the most convenient and efficient manner and the most accurate effect.

For higher accuracy and precision of interlayer offset detection, the interlayer offset detection zone N1 may be further configured to include the tenth graphic mark 231, the eleventh graphic mark 233, and the twelfth graphic mark 235. The tenth graphic mark 231 may be located on the first metal layer 201. The eleventh graphic mark 233 may be located on the second metal layer 202. The twelfth graphic mark 235 may be located on the third metal layer 203. In other embodiments of the present application, the tenth graphic mark 231, the eleventh graphic mark 233, and the twelfth graphic mark 235 may be located at any one of the fourth metal layer 204, the fifth metal layer 205, and the sixth metal layer 206, respectively.

The center E10 of the tenth graphic mark 231, the center E11 of the eleventh graphic mark 233 and the center E12 of the twelfth graphic mark 235 are all on a fourth straight line perpendicular to the first surface 200 a. The fourth straight line may be at the same position in the X direction as the first straight line F1. The pitch P2 (not shown, P2 is measured in the same manner as P1) of the tenth graphic mark 231 and the eleventh graphic mark 233 in the lengthwise direction of the printed circuit board 20 in the projection plane (i.e., the plane in which the X direction and the Z direction are located) of the first surface 200a is equal to the sum of the second preset offset value minus the amount of undercut of the metal layer in which the tenth graphic mark 231 and the eleventh graphic mark 233 are located. The pitch P2 of the eleventh and twelfth

graphic marks

233 and 235 in the projection plane (i.e., the plane in which the X-direction and the Z-direction lie) of the first surface 200a along the length direction of the printed circuit board 20, i.e., the X-direction, is equal to the second preset offset value minus the sum of the amounts of undercut of the metal layers in which the eleventh and twelfth

graphic marks

233 and 235 lie. The second predetermined offset value is a second value that allows for an interlayer offset between two adjacent metal layers. The second preset offset value may be about 65 microns. By setting a second preset offset value different from the first preset offset value, the embodiment of the present application can substantially determine the range of the layer deviation after performing the layer deviation detection for the same printed circuit board 20 for one time. For example, if no tangency or intersection occurs at the tenth graphic mark 231, the eleventh graphic mark 233, and the twelfth graphic mark 235, but tangency or intersection occurs at the first graphic mark 211, the second graphic mark 213, and the third graphic mark 215, it may be determined that the layers of the respective layers of the printed circuit board 20 at which tangency or intersection occurs are more than the first preset offset value, but less than the second preset offset value. If tangency or intersection also occurs at the tenth graphic mark 231, the eleventh graphic mark 233, and the twelfth graphic mark 235, it may be determined that the layer deviation of the respective layers of the printed circuit board 20 at which tangency or intersection occurs is greater than the second preset offset value.

The layer deflection detection zone N1 may also further include a thirteenth graphic indicia 237, a fourteenth graphic indicia 239, and a fifteenth graphic indicia 241. A thirteenth graphic indicia 237 may be located on the metal layer having the fourth graphic indicia 217. The fourteenth graphic mark 239 may be located on the metal layer having the fifth graphic mark 219. The fifteenth graphic mark 241 may be located on the metal layer having the sixth graphic mark 221.

The center E13 of the thirteenth graphic mark 237, the center E14 of the fourteenth graphic mark 239, and the center E15 of the fifteenth graphic mark are all on a fifth straight line perpendicular to the first surface 200 a. The fifth line may be at the same position in the X direction as the second line F2. A pitch P2 (not shown, P2 is measured in the same manner as P1) of the thirteenth graphic mark 237 and the fourteenth graphic mark 239 in the longitudinal direction of the printed circuit board 20, that is, in the X direction in the projection plane (i.e., the plane in which the X direction and the Z direction are located) of the first surface 200a is equal to the sum of the second preset offset value minus the amount of undercut of the metal layers in which the thirteenth graphic mark 237 and the fourteenth graphic mark 239 are located. The pitch P2 of the fourteenth graphic mark 239 and the fifteenth graphic mark 241 in the projection plane (i.e., the plane in which the X direction and the Z direction are located) of the first surface 200a along the length direction of the printed circuit board 20, i.e., the X direction, is equal to the second preset offset value minus the sum of the amounts of undercut of the metal layers in which the fourteenth graphic mark 239 and the fifteenth graphic mark 241 are located.

The layer deviation detection zone N1 may further include sixteenth graphical indicia 243, seventeenth graphical indicia 245, and eighteenth graphical indicia 247. The sixteenth graphic mark 243 may be located on the metal layer having the seventh graphic mark 223. The seventeenth graphic indicia 245 may be located on the metal layer having the eighth graphic indicia 225. An eighteenth graphic mark 247 may be located on the metal layer having the ninth graphic mark 227.

The center E16 of the sixteenth graphic mark 243, the center E17 of the seventeenth graphic mark 245 and the center E18 of the eighteenth graphic mark 247 are all on a sixth straight line perpendicular to the first surface 200 a. The fifth line may be at the same position in the X direction as the third line F3. The pitch P2 (not shown, P2 is measured in the same manner as P1) of the sixteenth graphic mark 243 and the seventeenth graphic mark 245 in the projection plane (i.e., the plane in which the X direction and the Z direction are located) of the first surface 200a along the length direction of the printed circuit board 20, i.e., the X direction, is equal to the sum of the second preset offset value minus the amount of undercut of the metal layers on which the sixteenth graphic mark 243 and the seventeenth graphic mark 245 are located. The pitch P2 of the seventeenth graphic mark 245 and the eighteenth graphic mark 247 in the projection plane (i.e., the plane in which the X direction and the Z direction are located) of the first surface 200a in the lengthwise direction of the printed circuit board 20, i.e., the X direction, is equal to the second preset offset value minus the sum of the amounts of undercut of the metal layers in which the seventeenth graphic mark 245 and the eighteenth graphic mark 247 are located.

The layer deviation detection zone N1 may further include a nineteenth graphic indicia 249, a twentieth graphic indicia 251, and a twenty-first graphic indicia 253. A nineteenth graphic mark 249 may be located on the first metal layer 201. The twentieth graphic mark 251 may be located on the second metal layer 202. The twenty-first graphic mark 253 may be located on the third graphic mark 203. In other embodiments of the present application, the nineteenth, twentieth, and twenty-first

graphic indicia

249, 251, and 253 may be located in any of the fourth, fifth, and

sixth metal layers

204, 205, and 206, respectively.

The center E19 of the nineteenth graphic mark 249, the center E20 of the twentieth graphic mark 251, and the center E21 of the twenty-first graphic mark 253 are all on a seventh straight line perpendicular to the first surface 200 a. The seventh straight line may be at the same position as the first straight line F1 in the X direction. The pitch P3 (not shown, P3 is measured in the same manner as P1) of the nineteenth and twentieth

graphic marks

249, 251 in the longitudinal direction of the printed circuit board 20 in the projection plane (i.e., the plane in which the X and Z directions lie) of the first surface 200a is equal to the sum of the third preset offset value minus the amount of undercut of the metal layer in which the nineteenth and twentieth

graphic marks

249, 251 are located. The pitch P3 in the projection plane (i.e., the plane in which the X direction and the Z direction) of the twentieth graphic mark 251 and the twenty-first graphic mark 253 on the first surface 200a along the length direction of the printed circuit board 20, i.e., the X direction, is equal to the third preset offset value minus the sum of the amounts of biting of the metal layers in which the twentieth graphic mark 251 and the twenty-first graphic mark 253 are located. The third predetermined offset value is a third value that allows for an interlayer offset between two adjacent metal layers. The third preset offset value may be about 75 microns. The first, second and third preset offset values may be different. The third predetermined offset value may be greater than the second predetermined offset value, and the second predetermined offset value may be greater than the first predetermined offset value. By setting a third preset offset value different from the first preset offset value and the second preset offset value, the embodiment of the present application can substantially determine the range of the layer deviation after performing the layer deviation detection for the same printed circuit board 20 for one time. For example, if no tangency or intersection occurs at the nineteenth, twentieth, and twenty-first

graphic marks

249, 251, and 253, but at the tenth, eleventh, and twelfth

graphic marks

231, 233, and 235, it may be determined that the layer deviation of the respective layers of the printed circuit board 20 at which tangency or intersection occurs is greater than the second preset offset value, but less than the third preset offset value.

The layer deviation detection zone N1 may further include a twenty-second graphic indicia 255, a twenty-third graphic indicia 257, and a twenty-fourth graphic indicia 259. A twenty-second graphic indicia 255 may be located on the metal layer having the fourth graphic indicia 217. The twenty-third graphic mark 257 may be located on the metal layer having the fifth graphic mark 219. The twenty-fourth graphic mark 259 may be located on the metal layer having the sixth graphic mark 221.

The center E22 of the twenty-second graphic mark 255, the center E23 of the twenty-third graphic mark 257, and the center E24 of the twenty-fourth graphic mark 259 are all on an eighth straight line perpendicular to the first surface 200 a. The eighth line may be at the same position as the second line F2 in the X direction. The pitch P3 (not shown, P3 is measured in the same manner as P1) of the twenty-second pattern mark 255 and the twenty-third pattern mark 257 in the lengthwise direction of the printed circuit board 20 in the projection plane (i.e., the plane in which the X direction and the Z direction are located) of the first surface 200a is equal to the sum of the third preset offset value minus the amount of undercut of the metal layer in which the twenty-second pattern mark 255 and the twenty-third pattern mark 257 are located. The pitch P3 of the twenty-third graphic mark 257 and the twenty-fourth graphic mark 259 in the projection plane (i.e., the plane in which the X direction and the Z direction are located) of the first surface 200a along the length direction of the printed circuit board 20, i.e., the X direction, is equal to the sum of the third preset offset value minus the amount of undercut of the metal layer in which the twenty-third graphic mark 257 and the twenty-fourth graphic mark 259 are located.

The layer deviation detection zone N1 may further include a twenty-fifth graphical indicia 261, a twenty-sixth graphical indicia 263, and a twenty-seventh graphical indicia 265. The twenty-fifth graphic indicia 261 may be located on the metal layer having the seventh graphic indicia 223. The twenty-sixth graphic indicia 263 may be located on the metal layer having the eighth graphic indicia 225. The twenty-seventh graphic indicia 265 may be located on the metal layer having the ninth graphic indicia 227.

The center E25 of the twenty-fifth graphic mark 261, the center E26 of the twenty-sixth graphic mark 263 and the center E27 of the twenty-seventh graphic mark 265 are all on a ninth straight line perpendicular to the first surface 200 a. The ninth line may be at the same position as the third line F3 in the X direction. The pitch P3 (not shown, P3 is measured in the same manner as P1) of the twenty-fifth graphic mark 261 and the twenty-sixth graphic mark 263 in the projection plane (i.e., the plane in which the X direction and the Z direction) of the first surface 200a along the length direction of the printed circuit board 20, i.e., the X direction, is equal to the sum of the third preset offset value minus the amount of undercut of the metal layers on which the twenty-fifth graphic mark 261 and the twenty-sixth graphic mark 263 are located. The pitch P3 of the twenty-sixth graphic mark 263 and the twenty-seventh graphic mark 265 in the projection plane (i.e., the plane in which the X direction and the Z direction are located) of the first surface 200a along the length direction of the printed circuit board 20, i.e., the X direction, is equal to the third preset offset value minus the sum of the amounts of undercut of the metal layers in which the twenty-sixth graphic mark 263 and the twenty-seventh graphic mark 265 are located.

The embodiment of the application enables the layer deviation detection to have more detailed and flexible detection effect by designing the pattern detection of three different preset deviation values, and improves the precision and flexibility of the layer deviation detection. Meanwhile, for interlayer offset detection between printed circuit boards with more layers, particularly more than six layers, in the embodiment of the application, three different metal layers positioned on the first side of the core layer 200 are selected as a first group for detection; selecting one of three different metal layers located at a first side of the core layer 200 and two metal layers located at a second side of the core layer 200 and formed without corresponding to the selected metal layer as a second group for detection; and one of the other two metal layers except the one with the two graphic marks is further selected from the three metal layers on the first side of the core layer 200, and the two metal layers formed on the second side of the core layer 200 and not corresponding to the selected metal layers are further selected as a third group for detection, so that the purpose of multilayer plate layer deviation detection is achieved in the most convenient and efficient manner and the most accurate effect.

The embodiment of the application also provides a method for detecting the interlayer position offset of the printed circuit board. The method includes providing a printed circuit board provided according to an embodiment of the application, and then irradiating a layer deviation detection area of the printed circuit board with X-rays to observe whether tangency or intersection exists between adjacent graphic marks in the layer deviation detection area. If the tangency or the intersection exists, the corresponding metal layer which is tangent or intersected is judged to be out of the allowable range, and the printed circuit board is unqualified. If the graphic marks have deviation but are not tangent or intersected, the layer deviation of the corresponding metal layer is judged not to exceed the allowable range, and the printed circuit board is qualified.

The method may further comprise observing whether there is a tangency or intersection of graphical indicia having the same preset offset value. If the third preset deviation value is larger than the second preset deviation value and the second preset deviation value is larger than the first preset deviation value, whether the graphic marks with the first preset deviation value are tangent or intersected or not can be observed, and if the graphic marks with the first preset deviation value are not tangent or intersected, the layer deviation of the printed circuit board is judged to meet the first preset deviation value. If there is a tangency or intersection of graphical indicia having a first predetermined offset value, then the graphical indicia having a second predetermined offset value may continue to be observed for the presence of tangency or intersection. And if the graphic marks with the second preset deviation value are not tangent or intersected, judging that the layer deviation of the printed circuit board meets the second preset deviation value. If there is a tangency or intersection of the graphical marks having the second predetermined offset value, it can be observed whether there is a tangency or intersection of the graphical marks having the third predetermined offset value. And if the graphic marks with the third preset deviation value are not tangent or intersected, judging that the layer deviation of the printed circuit board meets the third preset deviation value. If the graphic marks with the third preset deviation value are tangent or intersected, the layer of the printed circuit board is judged to be larger and does not meet the third preset deviation value.

The method for detecting the interlayer position offset of the printed circuit board can quickly identify whether the printed circuit board with more layers has the layer offset or not simply by irradiating the layer offset detection area of the printed circuit board, and can generally judge the approximate situation of the layer offset, so that the method has the advantages of high detection efficiency, accurate detection result and the like.

The technical content and technical features of the present application have been disclosed as above, however, those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the present application without departing from the spirit of the present application. Therefore, the protection scope of the present application should not be limited to the disclosure of the embodiments, but should include various alternatives and modifications without departing from the scope of the present application, which is encompassed by the claims of the present application.

Claims

1. A printed circuit board, comprising:

a core layer,

a first metal layer on a first surface of the core layer, the first metal layer having a first graphic indicia,

a second metal layer disposed proximate to the first metal layer and distal from the first surface of the core layer, the second metal layer having a second graphic indicia,

a third metal layer on a second surface of the core layer, the second surface being opposite to the first surface,

a fourth metal layer disposed proximate to the third metal layer and distal from the second surface of the core layer,

wherein the first graphic mark and the second graphic mark constitute a layer deviation detection area, a center of the first graphic mark and a center of the second graphic mark are both on a first straight line perpendicular to the first surface, and a distance between the first graphic mark and the second graphic mark in a projection plane of the first surface along a length direction of the printed circuit board is equal to a first preset deviation value minus a biting amount of the first metal layer and a biting amount of the second metal layer, the first preset deviation value being a first value that allows interlayer deviation between the first metal layer and the second metal layer.

2. The printed circuit board of claim 1, wherein the third metal layer is formed simultaneously corresponding to the first metal layer and the fourth metal layer is formed simultaneously corresponding to the second metal layer, wherein the layer deviation detection area further comprises a third graphic mark located on one of the first metal layer and the second metal layer and a fourth graphic mark located on one of the third metal layer and the fourth metal layer formed not corresponding to the metal layer having the third graphic mark,

the center of the third graphic mark and the center of the fourth graphic mark are both on a second straight line perpendicular to the first surface, and the distance between the third graphic mark and the fourth graphic mark in the projection plane of the first surface along the length direction of the printed circuit board is equal to the first preset offset value minus the bite amount of the metal layer where the third graphic mark is located and the bite amount of the metal layer where the fourth graphic mark is located.

3. The printed circuit board according to claim 1 or 2, wherein the printed circuit board includes four layer deviation detection regions, two of which are symmetrically disposed at an upper end portion and a lower end portion of a left side of the printed circuit board, and the other two of which are symmetrically disposed at an upper end portion and a lower end portion of a right side of the printed circuit board.

4. A printed circuit board, comprising:

a core layer,

a third metal layer disposed proximate to the second metal layer and distal to the first metal layer, the third metal layer having a third graphic indicia,

a fourth metal layer on a second surface of the core layer, the second surface being opposite to the first surface,

a fifth metal layer disposed proximate to the fourth metal layer and distal from the second surface of the core layer, an

A sixth metal layer disposed proximate to the fifth metal layer and distal to the fourth metal layer,

the first graphic mark, the second graphic mark and the third graphic mark form a layer deviation detection area, the center of the first graphic mark, the center of the second graphic mark and the center of the third graphic mark are all on a first straight line perpendicular to the first surface, the distance between the first graphic mark and the second graphic mark in the projection plane of the first surface along the length direction of the printed circuit board and the distance between the second graphic mark and the third graphic mark in the projection plane of the first surface along the length direction of the printed circuit board are respectively equal to the sum of a first preset deviation value minus the undercut amount of the metal layer where the corresponding graphic mark is located, and the first preset deviation value is a first value allowing interlayer deviation between two adjacent metal layers.

5. The printed circuit board of claim 4, wherein the fourth metal layer is formed simultaneously corresponding to the first metal layer, the fifth metal layer is formed simultaneously corresponding to the second metal layer, the sixth metal layer is formed simultaneously corresponding to the third metal layer,

the layer deviation detection region further includes a fourth graphic mark, a fifth graphic mark, and a sixth graphic mark, the fourth graphic mark being located on one of the first metal layer, the second metal layer, and the third metal layer, the fifth graphic mark and the sixth graphic mark being respectively located on two of the fourth metal layer, the fifth metal layer, and the sixth metal layer formed so as not to correspond to the metal layer having the fourth graphic mark,

wherein the center of the fourth graphic mark, the center of the fifth graphic mark and the center of the sixth graphic mark are all on a second straight line perpendicular to the first surface, and the distance between the fourth graphic mark and the fifth graphic mark in the projection plane of the first surface along the length direction of the printed circuit board and the distance between the fifth graphic mark and the sixth graphic mark in the projection plane of the first surface along the length direction of the printed circuit board are respectively equal to the sum of the first preset offset value minus the bite amount of the metal layer on which the corresponding graphic mark is located.

6. The printed circuit board of claim 5, wherein the layer deviation detection area further comprises a seventh graphic mark, an eighth graphic mark, and a ninth graphic mark, the seventh graphic mark being located on one of the first metal layer, the second metal layer, and the third metal layer excluding the metal layer having the fourth graphic mark, the eighth graphic mark and the ninth graphic mark being located on two of the fourth metal layer, the fifth metal layer, and the sixth metal layer, respectively, which are formed not corresponding to the metal layer having the seventh graphic mark,

wherein a center of the seventh graphic mark, a center of the eighth graphic mark, and a center of the ninth graphic mark are all on a third straight line perpendicular to the first surface, and a distance between the seventh graphic mark and the eighth graphic mark in a projection plane of the first surface along a length direction of the printed circuit board and a distance between the seventh graphic mark and the ninth graphic mark in the projection plane of the first surface along the length direction of the printed circuit board are respectively equal to a sum of the first preset offset value minus a bite amount of a metal layer on which the corresponding graphic mark is located.

7. The printed circuit board of claim 6, wherein the layer bias detection zone further comprises:

a tenth graphic mark on the first metal layer,

an eleventh graphic mark on the second metal layer, an

A twelfth graphic mark on the third metal layer,

wherein the center of the tenth graphic mark, the center of the eleventh graphic mark and the center of the twelfth graphic mark are all on a fourth straight line perpendicular to the first surface, and the distance between the tenth graphic mark and the eleventh graphic mark in the projection plane of the first surface along the length direction of the printed circuit board and the distance between the eleventh graphic mark and the twelfth graphic mark in the projection plane of the first surface along the length direction of the printed circuit board are respectively equal to the sum of a second preset offset value minus the bite amount of the metal layer on which the corresponding graphic mark is located, and the second preset offset value is a second value allowing interlayer offset between two adjacent metal layers.

8. The printed circuit board of claim 7, wherein the layer deviation detection zone further comprises a thirteenth graphical indicia, a fourteenth graphical indicia, and a fifteenth graphical indicia,

the thirteenth graphic mark is located on the metal layer having the fourth graphic mark, the fourteenth graphic mark is located on the metal layer having the fifth graphic mark, the fifteenth graphic mark is located on the metal layer having the sixth graphic mark,

wherein, the center of the thirteenth graphic mark, the center of the fourteenth graphic mark and the center of the fifteenth graphic mark are all on a fifth straight line perpendicular to the first surface, and the distance between the thirteenth graphic mark and the fourteenth graphic mark in the projection plane of the first surface along the length direction of the printed circuit board and the distance between the fourteenth graphic mark and the fifteenth graphic mark in the projection plane of the first surface along the length direction of the printed circuit board are respectively equal to the sum of the second preset offset value minus the bite amount of the metal layer on which the corresponding graphic mark is located.

9. The printed circuit board of claim 8, wherein the layer deviation detection zone further comprises a sixteenth graphical indicia, a seventeenth graphical indicia, and an eighteenth graphical indicia,

the sixteenth graphic mark is located on the metal layer having the seventh graphic mark, the seventeenth graphic mark is located on the metal layer having the eighth graphic mark, the eighteenth graphic mark is located on the metal layer having the ninth graphic mark,

wherein, the center of the sixteenth graphic mark, the center of the seventeenth graphic mark and the center of the eighteenth graphic mark are all on a sixth straight line perpendicular to the first surface, and the distance between the sixteenth graphic mark and the seventeenth graphic mark in the projection plane of the first surface along the length direction of the printed circuit board and the distance between the seventeenth graphic mark and the eighteenth graphic mark in the projection plane of the first surface along the length direction of the printed circuit board are respectively equal to the sum of the second preset offset value minus the bite amount of the metal layer where the corresponding graphic mark is located.

10. The printed circuit board of claim 9, wherein the layer bias detection zone further comprises:

a nineteenth graphic mark located on the first metal layer,

a twentieth graphic mark on the second metal layer, an

A twenty-first graphic mark on the third metal layer,

wherein the center of the nineteenth graphic mark, the center of the twentieth graphic mark and the center of the twenty-first graphic mark are all on a seventh straight line perpendicular to the first surface, and the distance between the nineteenth graphic mark and the twentieth graphic mark in the projection plane of the first surface in the length direction of the printed circuit board and the distance between the twentieth graphic mark and the twenty-first graphic mark in the projection plane of the first surface in the length direction of the printed circuit board are respectively equal to a sum of a third preset offset value minus the amount of undercut of the metal layer on which the corresponding graphic mark is located, and the third preset offset value is a third value that allows interlayer offset between two adjacent metal layers.

11. The printed circuit board of claim 10, wherein the layer deviation detection zone further comprises a twenty-second graphic indicia, a twenty-third graphic indicia, and a twenty-fourth graphic indicia,

the twenty-second graphic mark is located on the metal layer having the fourth graphic mark, the twenty-third graphic mark is located on the metal layer having the fifth graphic mark, the twenty-fourth graphic mark is located on the metal layer of the sixth graphic mark,

wherein the center of the twenty-second graphic mark, the center of the twenty-third graphic mark and the center of the twenty-fourth graphic mark are all on an eighth straight line perpendicular to the first surface, and the distance between the twenty-second graphic mark and the twenty-third graphic mark in the projection plane of the first surface along the length direction of the printed circuit board and the distance between the twenty-third graphic mark and the twenty-fourth graphic mark in the projection plane of the first surface along the length direction of the printed circuit board are respectively equal to the sum of the third preset offset value minus the undercut amount of the metal layer on which the corresponding graphic mark is located.

12. The printed circuit board of claim 11, wherein the layer deviation detection zone further comprises a twenty-fifth graphical indicia, a twenty-sixth graphical indicia, and a twenty-seventh graphical indicia,

the twenty-fifth graphic mark is located on the metal layer having the seventh graphic mark, the twenty-sixth graphic mark is located on the metal layer having the eighth graphic mark, the twenty-seventh graphic mark is located on the metal layer having the ninth graphic mark,

the center of the twenty-fifth graphic mark, the center of the twenty-sixth graphic mark and the center of the twenty-seventh graphic mark are all on a ninth straight line perpendicular to the first surface, and the distance between the twenty-fifth graphic mark and the twenty-sixth graphic mark in the projection plane of the first surface along the length direction of the printed circuit board and the distance between the twenty-sixth graphic mark and the twenty-seventh graphic mark in the projection plane of the first surface along the length direction of the printed circuit board are respectively equal to the sum of the third preset offset value minus the undercut amount of the metal layer where the corresponding graphic mark is located.

13. The printed circuit board of claim 12, wherein the first, second, and third preset offset values are different.

14. The printed circuit board of claim 13, wherein the first preset offset value may be 50 microns, the second preset offset value may be 65 microns, and the third preset offset value may be 75 microns.

15. The printed circuit board of any of claims 1-14, wherein each graphic indicia may be triangular, square, or circular and is disposed at a board edge area of the printed circuit board.

16. The printed circuit board of claim 15, wherein the ring-shaped mark of smallest diameter may be a solid circle.

17. The printed circuit board of any of claims 1-14, wherein the printed circuit board includes four of the layer deviation detection regions, two of which are symmetrically disposed at an upper end and a lower end of a left side of the printed circuit board and the other two of which are symmetrically disposed at an upper end and a lower end of a right side of the printed circuit board.

18. The printed circuit board of any of claims 1-14, wherein the graphic indicia is made of copper.

19. A method of detecting printed circuit board layer-to-layer position offset, comprising:

providing a printed circuit board according to any of claims 1-18,

the printed circuit board is irradiated with X-rays,

observing whether adjacent graphic marks in the layer deviation detection area are tangent or intersected.

20. The method of detecting printed circuit board layer position offset of claim 19, wherein observing whether adjacent graphic indicia in the layer offset detection zone are tangent or intersect comprises:

it is observed whether there is a tangency or an intersection of the graphical marks having the same preset offset value.