CN112787643A - Crosstalk suppression circuit and method of silicon carbide field effect tube - Google Patents
Crosstalk suppression circuit and method of silicon carbide field effect tube Download PDFInfo
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Abstract
The application discloses a crosstalk suppression circuit and method of a silicon carbide field effect tube, which are used for solving the technical problem of crosstalk in the existing bridge arm circuit. The circuit comprises: an upper bridge arm circuit and a lower bridge arm circuit; the upper bridge arm circuit comprises an upper switching tube S _ H and a first low-impedance loop; one end of the first low-impedance loop is connected with the second pole of the upper switch tube S _ H, and the other end of the first low-impedance loop is connected with the third pole of the upper switch tube S _ H and simultaneously connected with the first pole of the lower switch tube S _ L; the first low-impedance loop is used for inhibiting positive crosstalk voltage and negative crosstalk voltage between the second pole and the third pole of the upper switching tube S _ H; the lower bridge arm circuit comprises a lower switching tube S _ L and a second low-impedance loop; the second low impedance loop is used for suppressing a positive crosstalk voltage and a negative crosstalk voltage between the second pole and the third pole of the lower switch tube S _ L. The crosstalk suppression between the upper and lower switching tubes is realized through the circuit.
Description
Technical Field
The present disclosure relates to electronic circuits, and particularly, to a crosstalk suppression circuit and method for a silicon carbide field effect transistor.
Background
The silicon carbide field effect transistor has the characteristics of high switching speed, low switching loss, high voltage resistance and the like, and is widely applied to high-power electronic circuits. Among them, the most common is a bridge arm circuit composed of a silicon carbide field effect tube.
However, in the bridge arm circuit, due to the existence of various parasitic parameters, the switching action of one fet may adversely affect the other fet, i.e., crosstalk occurs. If this crosstalk phenomenon is not effectively suppressed, damage to the silicon carbide power fet or accelerated degradation of the silicon carbide power fet may easily occur.
Disclosure of Invention
The embodiment of the application provides a crosstalk suppression circuit and method for a silicon carbide field effect tube, and aims to solve the technical problem that crosstalk occurs between the silicon carbide field effect tubes in the existing bridge arm circuit.
In one aspect, an embodiment of the present application provides a crosstalk suppression circuit for a silicon carbide field effect transistor, including: an upper bridge arm circuit and a lower bridge arm circuit; the upper bridge arm circuit comprises an upper switching tube S _ H and a first low-impedance loop; one end of the first low-impedance loop is connected with the second pole of the upper switch tube S _ H, and the other end of the first low-impedance loop is connected with the third pole of the upper switch tube S _ H and simultaneously connected with the first pole of the lower switch tube S _ L; the first low-impedance loop is used for inhibiting positive crosstalk voltage and negative crosstalk voltage between the second pole and the third pole of the upper switching tube S _ H; the lower bridge arm circuit comprises a lower switching tube S _ L and a second low-impedance loop; one end of the second low-impedance loop is connected with the second pole of the lower switch tube S _ L, and the other end of the second low-impedance loop is connected with the third pole of the lower switch tube S _ L; the second low impedance loop is used for suppressing a positive crosstalk voltage and a negative crosstalk voltage between the second pole and the third pole of the lower switch tube S _ L.
The embodiment of the application provides a crosstalk suppression circuit and method of silicon carbide field effect transistor, through above-mentioned first low impedance return circuit, second low impedance return circuit, under the prerequisite that does not influence silicon carbide field effect transistor switching performance, not only avoided going up the misleading problem of switch tube or lower switch tube, prevented moreover that negative voltage from exceeding silicon carbide field effect transistor's bearing scope, and then avoided the negative voltage breakdown problem of going up switch tube or lower switch tube, thereby realized silicon carbide field effect transistor's crosstalk suppression problem.
In one implementation of the present application, the first low impedance loop includes a first upper capacitor C1_ H, a second upper capacitor C2_ H, a third upper diode D3_ H, a third upper switch tube S3_ H, and a first upper voltage source U1_ H; the second pole of the upper switch tube S _ H is connected with one end of the upper driving resistor Rin _ H; the other end of the upper driving resistor Rin _ H is connected with the cathode of the third upper diode D3_ H and is also connected with one end of the second upper capacitor C2_ H; the other end of the second upper capacitor C2_ H is connected with the first pole of the third upper switch tube S3_ H; a third pole of the third upper switching tube S3_ H is connected with the negative pole of the first upper voltage source U1_ H; the positive electrode of the first upper voltage source U1_ H is connected with the third pole of the upper switching tube S _ H, and is simultaneously connected with the first pole of the lower switching tube S _ L; the anode of the third upper diode D3_ H is connected to one end of the first upper capacitor C1_ H; the other end of the first upper capacitor C1_ H is connected to the positive electrode of the first upper voltage source U1_ H, and is also connected to the third pole of the upper switch tube S _ H, and is also connected to the first pole of the lower switch tube S _ L.
In one implementation manner of the present application, the upper bridge arm circuit further includes a first voltage circuit, where the first voltage circuit includes a first positive power supply Uon1, a first negative power supply Uoff1, a first upper switch tube S1_ H, and a second upper switch tube S2_ H; the first positive power supply Uon1 is connected to the first pole of the first upper switch tube S1_ H; the third pole of the first upper switch tube S1_ H is connected with the first pole of the second upper switch tube S2_ H; the third pole of the second upper switching tube S2_ H is connected to the first negative supply source Uoff 1.
In one implementation manner of the present application, the upper bridge arm circuit further includes a first resistance driving circuit; the input end of the first resistance driving circuit is connected with the output end of the first voltage circuit, and the output end of the first resistance driving circuit is connected with the second pole of the upper switch tube S _ H; the first resistance driving circuit comprises a first upper diode D1_ H, a first upper resistor R1_ H, a second upper diode D2_ H and a second upper resistor R2_ H; the cathode of the first upper diode D1_ H is connected to one end of the first upper resistor R1_ H; the other end of the first upper resistor R1_ H is connected with the anode of the second upper diode D2_ H and is also connected with the second pole of the switch tube S _ H; the cathode of the second upper diode D2_ H is connected to one end of the second upper resistor R2_ H; the other end of the second upper resistor R2_ H is connected to the anode of the first upper diode D1_ H, the third pole of the first upper switch S1_ H, and the first pole of the second upper switch S2_ H.
In one implementation manner of the present application, the upper switch tube S _ H, the first upper switch tube S1_ H, and the third upper switch tube S3_ H all use N-type silicon carbide field effect tubes; the second upper switch tube S2_ H adopts a P-type silicon carbide field effect tube; the first electrode is a drain electrode of the N-type field effect transistor or a drain electrode of the P-type field effect transistor, the second electrode is a grid electrode of the N-type field effect transistor or a grid electrode of the P-type field effect transistor, and the third electrode is a source electrode of the N-type field effect transistor or a source electrode of the P-type field effect transistor.
In one implementation of the present application, the first low impedance loop includes a third upper resistor R3_ H, a fourth upper resistor R4_ H, a third upper diode D3_ H, an upper triode Q _ H, and a first upper voltage source U1_ H; the second pole of the upper switch tube S _ H is connected with one end of the upper driving resistor Rin _ H; the other end of the upper driving resistor Rin _ H is connected with the cathode of the third upper diode D3_ H and is also connected with one end of the fourth upper resistor R4_ H; the other end of the fourth upper resistor R4_ H is connected with the collector of the upper triode Q _ H; the emitter of the upper triode Q _ H is connected with the cathode of a first upper voltage source U1_ H; the positive electrode of the first upper voltage source U1_ H is connected with the third pole of the upper switching tube S _ H, and is simultaneously connected with the first pole of the lower switching tube S _ L; an anode of the third upper diode D3_ H is connected to one end of the third upper resistor R3_ H; the other end of the third upper resistor R3_ H is connected with the anode of the first upper voltage source U1_ H, and is also connected with the third pole of the upper switch tube S _ H and is also connected with the first pole of the lower switch tube S _ L; the upper triode Q _ H adopts an NPN type triode.
In one implementation manner of the present application, the lower bridge arm circuit includes a lower switching tube S _ L and a second low impedance loop; one end of the second low-impedance loop is connected with the second pole of the lower switch tube S _ L, and the other end of the second low-impedance loop is connected with the third pole of the lower switch tube S _ L; the second low impedance loop comprises a first lower capacitor C1_ L, a second lower capacitor C2_ L, a third lower diode D3_ L, a third lower switch tube S3_ L and a first lower voltage source U1_ L; the second pole of the lower switch tube S _ L is connected with one end of the lower driving resistor Rin _ L; the other end of the lower driving resistor Rin _ L is connected with the cathode of the third lower diode D3_ L and is also connected with one end of the second lower capacitor C2_ L; the other end of the second lower capacitor C2_ L is connected with the first pole of the third lower switch tube S3_ L; a third pole of the third lower switching tube S3_ L is connected with the negative pole of the first lower voltage source U1_ L; the positive electrode of the first lower voltage source U1_ L is connected with the third pole of the lower switching tube S _ L; the anode of the third lower diode D3_ L is connected with one end of the first lower capacitor C1_ L; the other end of the first lower capacitor C1_ L is connected with the anode of a first lower voltage source U1_ L and is also connected with the third pole of the lower switch tube S _ L; the third pole of the lower switch tube S _ L is grounded.
In one implementation of the present application, the first pole of the lower switch tube S _ L is connected to the third pole of the upper switch tube S _ H, and is simultaneously connected to the positive pole of the first upper voltage source U1_ H, and is simultaneously connected to one end of the first upper capacitor C1_ H.
On the other hand, an embodiment of the present application further provides a crosstalk suppression method for a silicon carbide field effect transistor, where the crosstalk suppression circuit for a silicon carbide field effect transistor is applied, and the method includes: before the lower switching tube S _ L is conducted, a first low-impedance loop in the upper bridge arm circuit is started to apply negative voltage between the second pole and the third pole of the upper switching tube S _ H; at the moment when the lower switching tube S _ L is conducted, forward crosstalk voltage is generated between the second pole and the third pole of the upper switching tube S _ H; positive crosstalk voltage and negative voltage are mutually superposed to obtain inhibition; at the moment when the lower switch tube S _ L is turned off, a negative crosstalk voltage is generated between the second pole and the third pole of the upper switch tube S _ H, and the negative crosstalk voltage is suppressed through the first low-impedance loop in the upper bridge arm circuit.
In one implementation of the present application, the method further comprises: before the upper switching tube S _ H is conducted, a second low-impedance loop in the lower bridge arm circuit is started to apply negative voltage between a second pole and a third pole of the lower switching tube S _ L; at the moment when the upper switch tube S _ H is conducted, a forward crosstalk voltage is generated between the second pole and the third pole of the lower switch tube S _ L; the positive crosstalk voltage and the negative voltage are mutually superposed to obtain inhibition; at the moment when the upper switch tube S _ H is turned off, negative crosstalk voltage is generated between the second pole and the third pole of the lower switch tube S _ L, and the negative crosstalk voltage is restrained through a second low-impedance loop in the lower bridge arm circuit.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a circuit diagram of a crosstalk suppression circuit of a silicon carbide field effect transistor according to an embodiment of the present disclosure;
fig. 2 is a circuit diagram of a crosstalk suppression circuit of another silicon carbide field effect transistor according to an embodiment of the present disclosure;
fig. 3 is a waveform timing diagram of each switching tube in the crosstalk suppression circuit of the silicon carbide field effect transistor according to the embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The embodiment of the application provides a crosstalk suppression circuit and method of a silicon carbide field effect transistor, wherein a first low-impedance loop is connected in parallel between a second pole and a third pole of an upper switch tube, and a second low-impedance loop is connected in parallel between the second pole and the third pole of the lower switch tube, so that the phenomenon of false conduction in the moment that the upper switch tube is conducted in the lower switch tube is avoided, the moment that the lower switch tube is conducted is also ensured, the negative voltage between the second pole and the third pole of the upper switch tube cannot exceed the negative voltage bearing range of the upper switch tube, and further the crosstalk suppression process between the silicon carbide field effect transistors is realized.
The technical solutions proposed in the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Fig. 1 is a circuit diagram of a crosstalk suppression circuit of a silicon carbide field effect transistor according to an embodiment of the present disclosure. As shown in fig. 1, the crosstalk suppression circuit provided in the embodiment of the present application includes an upper bridge arm circuit and a lower bridge arm circuit; and the structures and the connection relations of circuit components of the upper bridge arm circuit and the lower bridge arm circuit are completely the same.
As shown in fig. 1, the upper arm circuit includes: the circuit comprises an upper switch tube, a first low-impedance loop, a first resistance driving circuit and a first voltage circuit. The input end of the first resistance driving circuit is connected with the output end of the first voltage circuit, and the output end of the first resistance driving circuit is connected with the second pole of the upper switch tube S _ H. And one end of the first low-impedance loop is connected with the second pole of the upper switch tube S _ H, and the other end of the first low-impedance loop is connected with the third pole of the upper switch tube S _ H and simultaneously connected with the first pole of the lower switch tube S _ L.
As shown in fig. 1, the first voltage circuit includes: the power supply system comprises a first positive power supply Uon1, a first negative power supply Uoff1, a first upper switch tube S1_ H and a second upper switch tube S2_ H. The first positive power supply Uon1 is connected to the first pole of the first upper switch tube S1_ H; the third pole of the first upper switch tube S1_ H is connected with the first pole of the second upper switch tube S2_ H; the third pole of the second upper switching tube S2_ H is connected to the first negative supply source Uoff 1.
Further, the first resistor driving circuit includes a first upper diode D1_ H, a first upper resistor R1_ H, a second upper diode D2_ H, and a second upper resistor R2_ H. Wherein, the cathode of the first upper diode D1_ H is connected with one end of the first upper resistor R1_ H; the other end of the first upper resistor R1_ H is connected with the anode of the second upper diode D2_ H and is also connected with the second pole of the switch tube S _ H; the cathode of the second upper diode D2_ H is connected to one end of the second upper resistor R2_ H; the other end of the second upper resistor R2_ H is connected to the anode of the first upper diode D1_ H, the third pole of the first upper switch S1_ H, and the first pole of the second upper switch S2_ H.
Further, the first low impedance loop includes a first upper capacitor C1_ H, a second upper capacitor C2_ H, a third upper diode D3_ H, a third upper switch tube S3_ H, and a first upper voltage source U1_ H. The second pole of the upper switch tube S _ H is connected with one end of the upper driving resistor Rin _ H; the other end of the upper driving resistor Rin _ H is connected to the cathode of the third upper diode D3_ H and to one end of the second upper capacitor C2_ H. The other end of the second upper capacitor C2_ H is connected with the first pole of the third upper switch tube S3_ H; a third pole of the third upper switching tube S3_ H is connected with the negative pole of the first upper voltage source U1_ H; the positive pole of the first upper voltage source U1_ H is connected to the third pole of the upper switching tube S _ H, and is also connected to the first pole of the lower switching tube S _ L. The anode of the third upper diode D3_ H is connected to one end of the first upper capacitor C1_ H; the other end of the first upper capacitor C1_ H is connected to the positive electrode of the first upper voltage source U1_ H, and is also connected to the third pole of the upper switch tube S _ H, and is also connected to the first pole of the lower switch tube S _ L.
It should be noted that, as shown in fig. 1, the first pole of the upper switch tube S _ H is connected to the second voltage source U2, the upper gate-drain capacitor Cgd _ H is connected between the first pole and the second pole of the upper switch tube S _ H, the upper gate-source capacitor Cgs _ H is connected between the second pole and the third pole of the upper switch tube S _ H, and the upper drain-source capacitor Cds _ H is connected between the first pole and the third pole of the upper switch tube S _ H.
It should be further noted that in the crosstalk suppression circuit provided in this embodiment of the application, the lower arm circuits have the same structure as the upper arm circuits, that is, the lower arm circuits include a second voltage circuit, a second resistance driving circuit, a second ground impedance circuit, and a lower switching tube S _ L. As shown in fig. 1, in the lower arm circuit, the connection relationship of the second voltage circuit is completely the same as that of the first voltage circuit, the connection relationship of the second resistance driving circuit is completely the same as that of the first resistance driving circuit, and the connection relationship of the second low impedance circuit is completely the same as that of the first low impedance circuit. Therefore, the connection relationship between the second voltage circuit and the second resistance driving circuit in the lower bridge arm circuit is not described in detail in the embodiments of the present application.
As shown in fig. 1, the second low impedance loop includes a first lower capacitor C1_ L, a second lower capacitor C2_ L, a third lower diode D3_ L, a third lower switch tube S3_ L, and a first lower voltage source U1_ L; the second pole of the lower switch tube S _ L is connected with one end of the lower driving resistor Rin _ L; the other end of the lower driving resistor Rin _ L is connected with the cathode of the third lower diode D3_ L and is also connected with one end of the second lower capacitor C2_ L; the other end of the second lower capacitor C2_ L is connected with the first pole of the third lower switch tube S3_ L; a third pole of the third lower switching tube S3_ L is connected with the negative pole of the first lower voltage source U1_ L; the positive electrode of the first lower voltage source U1_ L is connected with the third pole of the lower switching tube S _ L; the anode of the third lower diode D3_ L is connected with one end of the first lower capacitor C1_ L; the other end of the first lower capacitor C1_ L is connected with the anode of a first lower voltage source U1_ L and is also connected with the third pole of the lower switch tube S _ L; the third pole of the lower switch tube S _ L is grounded.
As will be understood by those skilled in the art, as shown in fig. 1, the first pole of the lower switch tube S _ L is connected to the third pole of the upper switch tube S _ H, and is also connected to the positive pole of the first upper voltage source U1_ H, and is also connected to one end of the first upper capacitor C1_ H; the third pole of the lower switch tube S _ L is grounded. A lower gate-drain capacitor Cgd _ L is connected between the first and second poles of the lower switch tube S _ L, a lower gate-source capacitor Cgs _ L is connected between the second and third poles of the lower switch tube S _ L, and a lower drain-source capacitor Cds _ L is connected between the first and third poles of the lower switch tube S _ L.
In one embodiment of the present application, the upper switch tube S _ H and the lower switch tube S _ L, the first upper switch tube S1_ H and the first lower switch tube S1_ L, and the third upper switch tube S3_ H and the third lower switch tube S3_ L are all N-type silicon carbide fets; the second upper switch tube S2_ H and the second lower switch tube S2_ L are P-type silicon carbide fets. The first electrode is a drain electrode of the N-type field effect transistor or a drain electrode of the P-type field effect transistor, the second electrode is a gate electrode of the N-type field effect transistor or a gate electrode of the P-type field effect transistor, and the third electrode is a source electrode of the N-type field effect transistor or a source electrode of the P-type field effect transistor.
In addition, the embodiment of the present application further provides another low impedance loop, which can also achieve the effect of suppressing the crosstalk phenomenon between the upper switch tube and the lower switch tube, compared with the first low impedance loop and the second low impedance loop. The circuit connection relationship is shown in fig. 2.
Fig. 2 is a circuit diagram of a crosstalk suppression circuit of another silicon carbide field effect transistor according to an embodiment of the present disclosure. As shown in fig. 2, the structures and the connection relations of the first voltage circuit and the second voltage circuit are kept unchanged, the structures and the connection relations of the first resistance driving circuit and the second resistance driving circuit are kept unchanged, and the connection relations of the upper switch tube S _ H and the lower switch tube S _ L are kept unchanged. The first low impedance loop and the second low impedance loop are modified as follows:
as shown in fig. 2, the first low impedance loop includes: a third upper resistor R3_ H, a fourth upper resistor R4_ H, a third upper diode D3_ H, an upper triode Q _ H, and a first upper voltage source U1_ H. The second pole of the upper switch tube S _ H is connected with one end of the upper driving resistor Rin _ H; the other end of the upper driving resistor Rin _ H is connected to the cathode of the third upper diode D3_ H, and is also connected to one end of the fourth upper resistor R4_ H. The other end of the fourth upper resistor R4_ H is connected with the collector of the upper triode Q _ H; the emitter of the upper triode Q _ H is connected with the cathode of a first upper voltage source U1_ H; the positive pole of the first upper voltage source U1_ H is connected to the third pole of the upper switching tube S _ H, and is also connected to the first pole of the lower switching tube S _ L. An anode of the third upper diode D3_ H is connected to one end of the third upper resistor R3_ H; the other end of the third upper resistor R3_ H is connected to the positive electrode of the first upper voltage source U1_ H, and is also connected to the third pole of the upper switch tube S _ H, and is also connected to the first pole of the lower switch tube S _ L.
Further, the second low impedance loop comprises: the diode comprises a third lower resistor R3_ L, a fourth lower resistor R4_ L, a third lower diode D3_ L, a lower triode Q _ L and a first lower voltage source U1_ L. The second pole of the lower switch tube S _ L is connected with one end of the lower driving resistor Rin _ L; the other end of the lower driving resistor Rin _ L is connected to the cathode of the third lower diode D3_ L, and is also connected to one end of the fourth lower resistor R4_ L. The other end of the fourth lower resistor R4_ L is connected with the collector of the lower triode Q _ L; the emitter of the lower triode Q _ L is connected with the cathode of a first lower voltage source U1_ L; the positive electrode of the first lower voltage source U1_ L is connected to the third pole of the lower switching tube S _ L. The anode of the third lower diode D3_ L is connected with one end of the third lower resistor R3_ L; the other end of the third lower resistor R3_ L is connected with the anode of the first lower voltage source U1_ L and is also connected with the third pole of the lower switch tube S _ L; the third pole of the lower switch tube S _ L is grounded.
In an embodiment of the present application, the upper transistor Q _ H and the lower transistor Q _ L both employ NPN transistors.
It should be noted that, the second pole of the third upper switch tube S3_ H and the second pole of the third lower switch tube S3_ L may be respectively connected to a controllable power source, and whether the controllable power source supplies power to the third upper switch tube S3_ H or the third lower switch tube S3_ L is determined by the on/off state of the upper switch tube S _ H or the lower switch tube S _ L. As will be apparent to those skilled in the art, when the controllable power source supplies power to the third upper switch tube S3_ H or the third lower switch tube S3_ L, the third upper switch tube S3_ H or the third lower switch tube S3_ L is turned on. It should be further noted that, when the third upper switch tube S3_ H and the third lower switch tube S3_ L are replaced by the upper transistor Q _ H and the lower transistor Q _ L, a controllable power source may be respectively connected to the base of the upper transistor Q _ H and the base of the lower transistor Q _ L, and when the controllable power source supplies power to the upper transistor Q _ H or the lower transistor Q _ L, the upper transistor Q _ H or the lower transistor Q _ L is turned on.
The foregoing is a structure and a connection relationship of a crosstalk suppression circuit of a silicon carbide field effect transistor provided in this embodiment of the present application. Based on the crosstalk suppression circuit, the embodiment of the application further provides a crosstalk suppression method for the silicon carbide field effect transistor, and the specific implementation process is as follows:
at the moment when the upper switch tube S _ H is conducted: a positive crosstalk voltage is generated between the second pole and the third pole of the lower switch tube S _ L, so that the second pole of the lower switch tube S _ L bears a larger positive voltage; at this time, the second lower switch tube S2_ L and the third lower switch tube S3_ L in the lower bridge arm circuit are turned on to generate a negative voltage between the second pole and the third pole of the lower switch tube S _ L, so that the voltage of the third pole of the lower switch tube S _ L is raised, and further, the positive crosstalk voltage between the gate sources and the negative voltage are mutually superposed to be suppressed.
At the moment when the upper switch tube S _ H is turned off, a negative crosstalk voltage is generated between the second pole and the third pole of the lower switch tube S _ L, and the negative crosstalk voltage causes the second pole of the lower switch tube S _ L to bear a large negative voltage; at this time, the negative crosstalk voltage is suppressed through the first lower capacitor C1_ L and the third lower diode D3_ L.
It should be noted that, at the moment that the upper switch tube S _ H is turned off, if the first lower capacitor C1_ L and the third lower diode D3_ L are not present in the lower bridge arm circuit, the negative crosstalk voltage between the second pole and the third pole of the lower switch tube S _ L is i (R1_ L + Rin _ L), where i is a negative crosstalk current value; when the first lower capacitor C1_ L and the third lower diode D3_ L are present in the crosstalk circuit, the negative crosstalk voltage between the second pole and the third pole of the lower switch tube S _ L is reduced to i x (Rin _ L), and is suppressed.
Further, at the moment when the lower switching tube S _ L is turned on: a positive crosstalk voltage is generated between the second pole and the third pole of the upper switch tube S _ H, so that the second pole of the upper switch tube S _ H bears a larger positive voltage; at this time, the second upper switch tube S2_ H and the third upper switch tube S3_ H in the upper bridge arm circuit are turned on to generate a negative voltage between the second pole and the third pole of the upper switch tube S _ H, so that the voltage of the third pole of the upper switch tube S _ H is raised, and further, the positive crosstalk voltage between the gate sources and the negative voltage are mutually superposed to be suppressed.
At the moment when the lower switching tube S _ L is turned off, a negative crosstalk voltage is generated between the second pole and the third pole of the upper switching tube S _ H, and the negative crosstalk voltage causes the second pole of the upper switching tube S _ H to bear a large negative voltage; at this time, the negative crosstalk voltage is suppressed through the first upper capacitor C1_ H and the third upper diode D3_ H.
It should be noted that, at the moment that the lower switching tube S _ L is turned off, if the first upper capacitor C1_ H and the third upper diode D3_ H are not present in the upper bridge arm circuit, the negative crosstalk voltage between the second pole and the third pole of the upper switching tube S _ H is i × R1_ H + Rin _ H, where i is a negative crosstalk current value; when the first upper capacitor C1_ H and the third upper diode D3_ H are present in the crosstalk circuit, the negative crosstalk voltage between the second pole and the third pole of the upper switch tube S _ H is reduced to i × Rin _ H, and is further suppressed.
A timing diagram corresponding to the crosstalk suppression process described above is shown in fig. 3. Fig. 3 is a waveform timing diagram of each switching tube in the crosstalk suppression circuit of the silicon carbide field effect transistor according to the embodiment of the present application. As shown in fig. 3:
period t0-t 1: the second upper switch tube S2_ H is switched on, the first negative power supply Uoff1 supplies power to the upper switch tube S _ H, and the upper switch tube S _ H is switched off; the second lower switch tube S2_ L is turned on, the second negative power supply Uoff2 supplies power to the lower switch tube S _ L, and the lower switch tube S _ L is turned off.
Period t1-t 2: the first upper switch tube S1_ H is turned on, the first forward power supply Uon1 supplies power to the upper switch tube S _ H, and the upper switch tube S _ H is turned on; the second lower switching tube S2_ L is switched on, a second negative power supply Uoff2 supplies power to the lower switching tube S _ L, and the lower switching tube S _ L is switched off; meanwhile, the third lower switch S3_ L is turned on, and the first lower voltage source U1_ L provides a negative voltage to the lower switch S _ L to suppress a positive crosstalk voltage between the second and third poles of the lower switch S _ L.
Period t2-t 3: the second upper switch tube S2_ H is switched on, the first negative power supply Uoff1 supplies power to the upper switch tube S _ H, and the upper switch tube S _ H is switched off; the second lower switch tube S2_ L is turned on, the second negative power supply Uoff2 supplies power to the lower switch tube S _ L, and the lower switch tube S _ L is turned off.
Period t3-t 4: the first lower switch tube S1_ L is turned on, the second positive power supply Uon2 supplies power to the lower switch tube S _ L, and the lower switch tube S _ L is turned on; the second upper switch tube S2_ H is switched on, the first negative power supply Uoff1 supplies power to the upper switch tube S _ H, and the upper switch tube S _ H is switched off; meanwhile, the third upper switch tube S3_ H is turned on, and the first upper voltage source U1_ H provides a negative voltage to the upper switch tube S _ H to suppress a positive crosstalk voltage between the second pole and the third pole of the upper switch tube S _ H.
Period t4-t 5: the second upper switch tube S2_ H is switched on, the first negative power supply Uoff1 supplies power to the upper switch tube S _ H, and the upper switch tube S _ H is switched off; the second lower switch tube S2_ L is turned on, the second negative power supply Uoff2 supplies power to the lower switch tube S _ L, and the lower switch tube S _ L is turned off.
That is, the time t1 corresponds to the turn-on moment of the upper switch tube S _ H, and the time t2 corresponds to the turn-off moment of the upper switch tube S _ H; the time t3 corresponds to the moment when the lower switching tube S _ L is turned on, and the time t4 corresponds to the moment when the lower switching tube S _ L is turned off.
Therefore, as shown in fig. 3, at time t1, the third lower switch tube S3_ L is turned from the off state to the on state, so that the first lower voltage source U1_ L provides a negative voltage between the second pole and the third pole of the lower switch tube S _ L to suppress the positive crosstalk voltage. At time t2, the third lower switch S3_ L is turned from the on state to the off state, so that the negative crosstalk voltage between the second pole and the third pole of the lower switch S _ L is suppressed by the first lower capacitor C1_ L and the third lower diode D3_ L.
Further, at time t3, the third upper switch S3_ H is turned from off to on state, so that the first upper voltage source U1_ H provides a negative voltage between the second and third poles of the upper switch S _ H to suppress the positive crosstalk voltage. At time t4, the third upper switch S3_ H is turned from the on state to the off state, so that the negative crosstalk voltage between the second pole and the third pole of the upper switch S _ H is suppressed by the first upper capacitor C1_ H and the third upper diode D3_ H.
It should be noted that, in the embodiment of the present application, a voltage direction in which the second pole of the upper switch tube S _ H or the lower switch tube S _ L points to the third pole is a positive voltage direction, and a voltage direction in which the third pole of the upper switch tube S _ H or the lower switch tube S _ L points to the second pole is a negative voltage direction.
The embodiments in the present application are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A crosstalk suppression circuit for a silicon carbide field effect transistor, the circuit comprising: an upper bridge arm circuit and a lower bridge arm circuit;
the upper bridge arm circuit comprises an upper switching tube (S _ H) and a first low-impedance loop; one end of the first low-impedance loop is connected with the second pole of the upper switch tube (S _ H), and the other end of the first low-impedance loop is connected with the third pole of the upper switch tube (S _ H) and the first pole of the lower switch tube (S _ L); the first low impedance loop is used for inhibiting a positive crosstalk voltage and a negative crosstalk voltage between the second pole and the third pole of the upper switch tube (S _ H);
the lower bridge arm circuit comprises a lower switching tube (S _ L) and a second low-impedance loop; one end of the second low impedance loop is connected with the second pole of the lower switch tube (S _ L), and the other end of the second low impedance loop is connected with the third pole of the lower switch tube (S _ L); the second low impedance loop is used for suppressing a positive crosstalk voltage and a negative crosstalk voltage between the second pole and the third pole of the lower switch tube (S _ L).
2. The cross talk suppression circuit of silicon carbide field effect transistor according to claim 1, wherein the first low impedance loop comprises a first upper capacitor (C1_ H), a second upper capacitor (C2_ H), a third upper diode (D3_ H), a third upper switch (S3_ H), and a first upper voltage source (U1_ H);
wherein, the second pole of the upper switch tube (S _ H) is connected with one end of the upper driving resistor (Rin _ H); the other end of the upper driving resistor (Rin _ H) is connected to the cathode of the third upper diode (D3_ H) and also connected to one end of the second upper capacitor (C2_ H);
the other end of the second upper capacitor (C2_ H) is connected with the first pole of the third upper switch tube (S3_ H); a third pole of the third upper switching tube (S3_ H) is connected with the negative pole of the first upper voltage source (U1_ H); the positive electrode of the first upper voltage source (U1_ H) is connected with the third pole of the upper switching tube (S _ H) and is simultaneously connected with the first pole of the lower switching tube (S _ L);
an anode of the third upper diode (D3_ H) is connected to one end of the first upper capacitor (C1_ H); the other end of the first upper capacitor (C1_ H) is connected with the positive electrode of the first upper voltage source (U1_ H), the third electrode of the upper switch tube (S _ H) and the first electrode of the lower switch tube (S _ L).
3. The crosstalk suppression circuit of a silicon carbide field effect transistor according to claim 1, wherein said upper bridge arm circuit further comprises a first voltage circuit;
the first voltage circuit comprises a first positive power supply (Uon1), a first negative power supply (Uoff1), a first upper switch tube (S1_ H) and a second upper switch tube (S2_ H);
the first positive power supply (Uon1) is connected with the first pole of a first upper switch tube (S1_ H); a third pole of the first upper switch tube (S1_ H) is connected with a first pole of the second upper switch tube (S2_ H); a third pole of the second upper switching tube (S2_ H) is connected to the first negative supply source (Uoff 1).
4. The crosstalk suppression circuit of the silicon carbide field effect transistor according to claim 3, wherein the upper bridge arm circuit further comprises a first resistance driving circuit; the input end of the first resistance driving circuit is connected with the output end of the first voltage circuit, and the output end of the first resistance driving circuit is connected with the second pole of the upper switch tube (S _ H);
the first resistance driving circuit includes a first upper diode (D1_ H), a first upper resistor (R1_ H), a second upper diode (D2_ H), and a second upper resistor (R2_ H);
a cathode of the first upper diode (D1_ H) is connected to one end of the first upper resistor (R1_ H); the other end of the first upper resistor (R1_ H) is connected with the anode of the second upper diode (D2_ H) and is also connected with the second pole of the upper switch tube (S _ H);
a cathode of the second upper diode (D2_ H) is connected to one end of the second upper resistor (R2_ H); the other end of the second upper resistor (R2_ H) is connected with the anode of the first upper diode (D1_ H), and is also connected with the third pole of the first upper switch tube (S1_ H), and is also connected with the first pole of the second upper switch tube (S2_ H).
5. The crosstalk suppression circuit of SiC FET according to claim 4, wherein said upper switch (S _ H), said first upper switch (S1_ H) and said third upper switch (S3_ H) are N-type SiC FETs;
the second upper switch tube (S2_ H) adopts a P-type silicon carbide field effect tube;
the first pole is the drain electrode of N type field effect transistor or the drain electrode of P type field effect transistor, the second pole is the grid of N type field effect transistor or the grid of P type field effect transistor, the third pole is the source electrode of N type field effect transistor or the source electrode of P type field effect transistor.
6. The cross talk suppression circuit of silicon carbide FET according to claim 1, wherein the first low impedance loop comprises a third upper resistor (R3_ H), a fourth upper resistor (R4_ H), a third upper diode (D3_ H), an upper triode (Q _ H), and a first upper voltage source (U1_ H);
wherein, the second pole of the upper switch tube (S _ H) is connected with one end of the upper driving resistor (Rin _ H); the other end of the upper driving resistor (Rin _ H) is connected to the cathode of the third upper diode (D3_ H) and also connected to one end of the fourth upper resistor (R4_ H);
the other end of the fourth upper resistor (R4_ H) is connected with the collector of the upper triode (Q _ H); the emitter of the upper triode (Q _ H) is connected with the negative electrode of the first upper voltage source (U1_ H); the positive electrode of the first upper voltage source (U1_ H) is connected with the third pole of the upper switching tube (S _ H) and is simultaneously connected with the first pole of the lower switching tube (S _ L);
an anode of the third upper diode (D3_ H) is connected to one end of the third upper resistor (R3_ H); the other end of the third upper resistor (R3_ H) is connected with the positive electrode of the first upper voltage source (U1_ H), the third pole of the upper switch tube (S _ H) and the first pole of the lower switch tube (S _ L);
the upper triode (Q _ H) adopts an NPN type triode.
7. The crosstalk suppression circuit of silicon carbide field effect transistor according to claim 1, wherein said lower bridge arm circuit comprises a lower switch tube (S _ L) and a second low impedance loop; one end of the second low impedance loop is connected with the second pole of the lower switch tube (S _ L), and the other end of the second low impedance loop is connected with the third pole of the lower switch tube (S _ L);
the second low impedance loop comprises a first lower capacitor (C1_ L), a second lower capacitor (C2_ L), a third lower diode (D3_ L), a third lower switch tube (S3_ L) and a first lower voltage source (U1_ L);
wherein, the second pole of the lower switch tube (S _ L) is connected with one end of the lower driving resistor (Rin _ L); the other end of the lower driving resistor (Rin _ L) is connected with the cathode of the third lower diode (D3_ L) and is also connected with one end of the second lower capacitor (C2_ L);
the other end of the second lower capacitor (C2_ L) is connected with the first pole of the third lower switch tube (S3_ L); a third pole of the third lower switching tube (S3_ L) is connected to the negative pole of the first lower voltage source (U1_ L); the positive electrode of the first lower voltage source (U1_ L) is connected with the third pole of the lower switching tube (S _ L);
an anode of the third lower diode (D3_ L) is connected to one end of the first lower capacitor (C1_ L); the other end of the first lower capacitor (C1_ L) is connected with the positive electrode of the first lower voltage source (U1_ L) and is also connected with the third electrode of the lower switch tube (S _ L);
the third pole of the lower switching tube (S _ L) is grounded.
8. The crosstalk suppression circuit of SiC FET according to claim 7, wherein said first pole of said lower switch (S _ L) is connected to said third pole of said upper switch (S _ H), and is simultaneously connected to said positive pole of said first upper voltage source (U1_ H), and is simultaneously connected to one end of said first upper capacitor (C1_ H).
9. A method for suppressing crosstalk of a silicon carbide field effect transistor, applying the crosstalk suppression circuit of the silicon carbide field effect transistor according to any one of claims 1 to 8,
before a lower switch tube (S _ L) is conducted, a first low-impedance loop in the upper bridge arm circuit is started to apply negative voltage between a second pole and a third pole of the upper switch tube (S _ H);
generating a forward crosstalk voltage between the second pole and the third pole of the upper switch tube (S _ H) at the moment when the lower switch tube (S _ L) is conducted; the positive crosstalk voltage and the negative voltage are mutually superposed to obtain inhibition;
at the moment when the lower switch tube (S _ L) is turned off, negative crosstalk voltage is generated between the second pole and the third pole of the upper switch tube (S _ H), and the negative crosstalk voltage is restrained through a first low-impedance loop in the upper bridge arm circuit.
10. A method for suppressing crosstalk of a silicon carbide field effect transistor, applying the crosstalk suppression circuit of the silicon carbide field effect transistor according to any one of claims 1 to 8,
before an upper switch tube (S _ H) is conducted, a second low-impedance loop in the lower bridge arm circuit is started to apply negative voltage between a second pole and a third pole of the lower switch tube (S _ L);
at the moment when the upper switch tube (S _ H) is conducted, generating a forward crosstalk voltage between the second pole and the third pole of the lower switch tube (S _ L); the positive crosstalk voltage and the negative voltage are mutually superposed to obtain inhibition;
at the moment when the upper switch tube (S _ H) is turned off, negative crosstalk voltage is generated between the second pole and the third pole of the lower switch tube (S _ L), and the negative crosstalk voltage is restrained through a second low-impedance loop in the lower bridge arm circuit.
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Application publication date: 20210511 |